Intersil CDP1853CD3 High-reliability cmos n-bit 1 of 8 decoder Datasheet

CDP1853C/3
High-Reliability CMOS N-Bit 1 of 8 Decoder
March 1997
Features
Description
• Provides Direct Control of Up to 7 Input and 7 Output
Devices When used with a CDP1800-Series Microprocessor
The CDP1853/3 and CDP1853C/3 are high-reliability 1 of 8
decoders designed for use in general purpose microprocessor systems. These devices, which are functionally identical,
are specifically designed for use as gated N-bit decoders
and interface directly with the 1800-Series microprocessors
without additional components. The CDP1853/3 has a recommended operating voltage range of 4V to 10.5V, and the
CDP1853C/3 has a recommended operating voltage range
of 4V to 6.5V.
• CHIP ENABLE (CE) Allows Easy Expansion for Multilevel I/O Systems
Ordering Information
PACKAGE
TEMP. RANGE
5V
SBDIP
-55oC to +125oC CDP1853CD3
10V
PKG.
NO.
-
D16.3
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low
transition) to the trailing edge of CLOCK B (high-to-low
transition). All outputs will be low when the device is not
selected (CE = 0) and during conditions of CLOCK A and
CLOCK B as shown in Figure 2. The CDP1853/3 inputs N0,
N1, N2, CLOCK A, and CLOCK B are connected to 1800series microprocessor outputs N0, N1, N2, TPA, and TPB
respectively, when used to decode I/O commands as shown
in Figure 5. The CHIP ENABLE (CE) input provides the capability for multiple levels of decoding as shown in Figure 6.
The CDP1853/3 can also be used as a general purpose 1 of
8 decoder for I/O and memory system applications as shown
in Figure 4.
Pinout
16 LEAD SBDIP
TOP VIEW
16 VDD
CLK A 1
N0 2
15 CLK B
N1 3
14 N2
OUT 0 4
13 CE
OUT 1 5
12 OUT 4
OUT 2 6
11 OUT 5
OUT 3 7
10 OUT 6
VSS 8
9 OUT 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-40
File Number
1713.2
CDP1853/3, CDP1853C/3
CDP1853/3 Functional Diagram
TRUTH TABLE
4
N0
2
5
6
N1
N2
3
1 OF 8
DECODER
7
12
11
14
10
EN
9
CE
CL A
CL B
EN
1
0
0
Qn-1(Note 2)
1
0
1
1
1
1
0
0
OUT 4
1
1
1
1
OUT 5
0
X
X
0
OUT 0
OUT 1
OUT 2
OUT 3
OUT 6
OUT 7
13
CE
1
QN
CLOCK
A
(TPA)
N2
N1
N0
EN
0
1
2
3
4
5
6
7
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
1
0
15
1
1
1
1
0
0
0
0
0
0
0
1
CLOCK
B
(TPB)
X
X
X
0
0
0
0
0
0
0
0
0
NOTES:
FIGURE 1.
1. 1 = High level, 0 = Low level, X = Don’t care.
2. Qn-1 = Enable remains in previous state.
4-41
CDP1853/3, CDP1853C/3
Static Electrical Specifications
CONDITIONS
LIMITS
-55oC, +25oC
PARAMETER
VIN
(V)
VDD
(V)
MIN
MAX
MIN
MAX
UNITS
-
0, 5
5
-50
-
-100
-
µA
-
0, 10
10
-500
-
-1000
-
µA
0.4
-
5
2.3
-
1.6
-
mA
0.5
-
10
3.7
-
2.6
-
mA
4.6
-
5
-
-1.7
-
-1.2
mA
9.5
-
10
-
-3.7
-
-2.6
mA
-
0, 5
5
-
0.1
-
0.2
V
-
0, 10
10
-
0.1
-
0.2
V
-
0, 5
5
4.9
-
4.8
-
V
-
0, 10
10
9.9
-
9.8
-
V
0.8, 4.2
-
5
-
1.5
-
1.5
V
1, 9
-
10
-
3
-
3
V
0.8, 4.2
-
5
3.5
-
3.5
-
V
1, 9
-
10
7
-
7
-
V
-
0
5
-1
-
-5
-
µA
-
0
10
-1
-
-5
-
µA
-
5
5
-
1
-
5
µA
-
10
10
-
1
-
5
µA
CIN (Note 2)
-
-
-
-
10
-
10
pF
COUT (Note 2)
-
-
-
-
15
-
15
pF
SYMBOL
Quiescent Device
Current
ISS
(Note 1)
Output Low Drive
(Sink) Current
IOL
Output High Drive
(Source) Current
IOH
Output Voltage
Low-Level
VOL
(Note 2)
Output Voltage
High-Level
VOH
(Note 2)
Input Low Voltage
VIL
Input High Voltage
VIH
Input Leakage Low
IIL
Input Leakage High
Input Capacitance
Output Capacitance
+125oC
VO
(V)
IIH
NOTES:
1. The CDP1853C meets all 5V static electrical characteristics of the CDP1853 except quiescent device current for which the limits are:
ISS = -500µA at -55oC and +25oC and ISS = -1000µA at +125oC.
2. Guaranteed but not tested.
Dynamic Electrical Specifications
See Figure 2, CL = 100pF, tR, tF = 15ns
LIMITS
-55oC, +25oC
PARAMETER
Propagation Delay Time:
Chip Enable (CE) to Output High
+125oC
SYMBOL
VDD
(V)
MIN
MAX
MIN
MAX
UNITS
tEOH
5
-
175
-
275
ns
10
-
90
-
150
ns
4-42
CDP1853/3, CDP1853C/3
Dynamic Electrical Specifications
See Figure 2, CL = 100pF, tR, tF = 15ns
LIMITS
-55oC, +25oC
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
tEOL
5
-
295
-
400
ns
10
-
200
-
250
ns
5
-
225
-
315
ns
10
-
120
-
165
ns
5
-
210
-
300
ns
10
-
110
-
150
ns
5
-
295
-
400
ns
10
-
200
-
250
ns
5
50
-
75
-
ns
10
25
-
50
-
ns
5
50
-
75
-
ns
10
25
-
50
-
ns
Disable to Output Low
N Input to Output
tNO
Clock A to Output Low
tAO
Clock B to Output Low
tBO
Pulse Width:
tCACA
Clock A
Clock B
tCBCB
Recommended Operating Conditions
+125oC
VDD
(V)
At TA = Full Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
LIMITS
CDP1853/3
PARAMETER
DC Operating Voltage Range
Input voltage Range
CDP1853C/3
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
VSS
VDD
VSS
VDD
V
4-43
CDP1853/3, CDP1853C/3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1853/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1853C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
85
22
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Timing Diagrams
N0 - N2
CE
OUTPUT 0 - 7
OUTPUT 0 - 7
TN0
FIGURE 2B. CE TO OUTPUT DELAY TIME
FIGURE 2A. N - INPUTS TO OUTPUTS DELAY TIME
MIN. CLOCK A
PULSE WIDTH
MIN. CLOCK B
PULSE WIDTH
TEOL
TEOH
TCACA
TCBCB
CLOCK A
OUTPUT 0 - 7
CLOCK B
TAO
OUTPUT 0 - 7
(SEE NOTE 1)
NOTE:
TBO
1. To measure TAO, Clock B must be tied low.
FIGURE 2C. CLOCK B TO OUTPUT DELAY TIME
FIGURE 2D. CLOCK A TO OUTPUT DELAY TIME
FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS
TPA
OUT 0
TPB
CE
EN
(NOTE 1)
OUTPUT
A
N0
OUT 1
B
N1
OUT 2
C
N2
OUT 3
CHIP ENABLE
CE
OUT 4
VDD
NOTE:
CLK B OUT 5
CLK A OUT 6
1. Output enabled when EN = high. Internal signal shown for reference only (see Figure 1).
FIGURE 3. TIMING DIAGRAM
OUT 7
FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER
4-44
CDP1853/3, CDP1853C/3
CDP1802 CPU
TPA
TPB
N0 N1 N2 TPB MRD
VDD
CLOCK A CLOCK B CE N0 N1 N2
CDP1853
0 1 2-6 7
CS1 CS2
DATA
AVAILABLE
DATA
CDP1852
OUTPUT
PORT 7
DATA BUS
LOAD VIA
67 INSTRUCTION
CS1 CS2
CDP1852
INPUT
PORT 7
SR
MODE TPB
VDD
READ VIA
6F INSTRUCTION
DATA
MODE
STROBE
CLOCK
5 CDP1852 INPUT AND OUTPUT PORTS
LOAD VIA
61 INSTRUCTION
AVAILABLE
CS2 CS1
CS1 CS2
CDP1852
OUTPUT
PORT 1
CDP1852
INPUT
PORT 1
SR
MODE TPB
READ VIA
69 INSTRUCTION
MODE
VDD
STROBE
CLOCK
7 OUTPUT PORTS
7 INPUT PORTS
FIGURE 5. N-BIT DECODER IN A ONE LEVEL I/O SYSTEM
4-45
DATA
CDP1853/3, CDP1853C/3
N0 N1 N2
CDP1800 SERIES
MRD BUS
TPA TPB
DATA BUS
CL CS1
TPA
CDP1853
1
DECODED
“61” INSTRUCTION
CS2 CDP1852
CLOCK A
CLOCK B
CE
NO, N1, N2
I/O
7 INPUT,
6 OUTPUT
PORTS
CDP1853
“62 - 6F”
INST.
CLOCK A
CLOCK B
CE
NO, N1, N2
I/O
7 INPUT,
6 OUTPUT
PORTS
CDP1853
“62 - 6F”
INST.
SECTIONS 3 - 7
CLOCK A
CLOCK B
CE
NO, N1, N2
I/O
7 INPUT,
6 OUTPUT
PORTS
CDP1853
“62 - 6F”
INST.
NOTE:
1. System shown will select up to 56 input and 48 output ports. With additional decoding, the total number of input and output ports can be
further expanded.
FIGURE 6. TWO LEVEL I/O USING CDP1853 AND CDP1852
Bias/Static Burn-In Circuit
VDD
VSS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
TYPE
VDD
CDP1853C
VDD
TEMPERATURE
7V
+125oC
TIME
160 Hrs.
VSS
VDD
NOTE:
1. All resistors are 47kΩ ±20%.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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