PulseCore ASM2P3807AG-20-AT 3.3v cmos 1-to-10 clock driver Datasheet

ASM2P3807A
November 2006
rev 0.3
3.3V CMOS 1-TO-10 CLOCK DRIVER
Features
Product Description
•
0.5 MICRON CMOS Technology
•
Guaranteed low skew < 350pS (max.)
•
Very low duty cycle distortion < 350pS (max.)
offers 1:10 fanout. The large fanout from a single input
•
High speed: propagation delay < 3nS (max.)
reduces loading on the preceding driver and provides an
•
Very low CMOS power levels
•
TTL compatible inputs and outputs
noise margins. Multiple power and grounds reduce noise.
•
1:10 fanout
Typical applications are clock and signal distribution.
•
Maximum output rise and fall time < 1.5nS (max.)
•
Low input capacitance: 4.5pF typical
•
Operates with 3.3V ± 0.3V Supply
•
Inputs can be driven from 3.3V or 5V components
•
Available in SSOP, SOIC, and QSOP Packages
The ASM2P3807A 3.3V clock driver is built using advanced
dual metal CMOS technology. This low skew clock driver
efficient clock distribution network. The ASM2P3807A
offers low capacitance inputs with hysteresis for improved
Block Diagram
O1
O2
O3
O4
O5
IN
O6
O7
O8
O9
O10
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
ASM2P3807A
November 2006
rev 0.3
Pin Configuration
IN
1
20
VCC
GND
2
19
O10
O1
3
18
O9
17
GND
16
O8
15
VCC
14
O7
13
GND
12
O6
11
O5
A
S
M
2
P
3
8
0
7
A
4
VCC
O2
5
GND
6
O3
7
VCC
8
O4
9
10
GND
SOIC / SSOP/ QSOP Packages
TOP VIEW
Pin Description
Pin#
Pin Names
Description
1
IN
Clock Inputs
3,5,7,9,11,12,14,16,18,19
O 1-O10
Clock Outputs
2,6,10,13,17
GND
Ground
4,8,15,20
Vcc
Power
Absolute Maximum Ratings
Symbol
Description
Max
Unit
VTERM1
Terminal Voltage with Respect to GND
-0.5 to +4.6
V
VTERM2
Terminal Voltage with Respect to GND
-0.5 to +7
V
VTERM3
Terminal Voltage with Respect to GND
-0.5 to VCC+0.5
V
TSTG
Storage Temperature
-65 to +150
°C
IOUT
DC Output Current
-60 to +60
mA
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
NOTES:
1. VCC terminals.
2. Input terminals.
3. Outputs and I/O terminals.
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
2 of 18
ASM2P3807A
November 2006
rev 0.3
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
Parameter1
Conditions
Typ
Max
Unit
CIN
Input Capacitance
VIN= 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
Note:1. This parameter is measured at characterization but not tested.
Power Supply Characteristics
Symbol
Parameter
Test Conditions1
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC= Max.
Min
VIN = VCC –0.6V3
Typ2
Max
Unit
10
30
µA
0.31
0.45
mA/
MHz
15.5
22.8
VCC= Max.
ICCD
Dynamic Power Supply
Current4
Input toggling
VIN = VCC
50% Duty Cycle
VIN = GND
Outputs Open
VCC= Max.
Input toggling
IC
Total Power Supply Current
6
50% Duty Cycle
Outputs Open
VIN = VCC
VIN = GND
5
mA
fi = 50MHz
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fi = Input Frequency
All currents are in milliamps and all frequencies are in megahertz.
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
3 of 18
ASM2P3807A
November 2006
rev 0.3
DC Electrical Characteristics over Operating Range
Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V
Symbol
VIH
VIL
IIH
IIL
Parameter
Test Conditions1
Input HIGH Level (Input pins)
Guaranteed Logic HIGH Level
Input HIGH Level (I/O pins)
Input LOW Level
Guaranteed Logic LOW Level
(Input and I/O pins)
Input HIGH Current (Input pins)
VCC= Max
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
VCC= Max
Input LOW Current (I/O pins)
IOZH
High Impedence Output Current
IOZL
(3-State Output Pins)
VIK
Clamp Diode Voltage
IODH
Output HIGH Current
IODL
Output LOW Current
VOH
Output HIGH Voltage
VOL
Min
VCC= Max
5.5
V
2
VCC+ 0.5
-0.5
0.8
VI = VCC
±1
VI = GND
±1
VI = GND
±1
VO = VCC
±1
VO = GND
±1
VCC= 3.3V, VIN = VIH or VIL,
VO = 1.5V3
VCC= 3.3V, VIN = VIH or VIL,
VO = 1.5V3
VCC= Min.
IOH= –0.1mA
VIN = VIH or VIL
IOH= –8mA
VCC= Min
IOL= 0.1mA
Input Power Off Leakage
4
VCC= Max., VO = GND
VH
Input Hysteresis
-
ICCL
Quiescent Power Supply Current
µA
µA
-1.2
V
-36
-60
-110
mA
50
90
200
mA
VCC-0.2
5
2.4
V
3
0.2
IOL= 16mA
0.2
0.4
IOL= 24mA
0.3
0.5
3
V
-0.7
VCC= 0V, VIN = 4.5V
Short Circuit Current
ICCZ
2
±1
IOS
ICCH
Unit
VI = 5.5V
VIN = VIH or VIL
IOFF
Max
VCC= Min., IIN = –18mA
Output LOW Voltage
Typ
-60
VCC= Max.
VIN = GND or VCC
-135
±1
µA
-240
mA
150
0.1
V
mV
10
µA
NOTES:
1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = Vcc - 0.6V at rated current.
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
4 of 18
ASM2P3807A
November 2006
rev 0.3
Switching Characteristics Over Operating Range – Commercial3,4
Symbol
tPLH
tPHL
Propagation Delay
tR
Output Rise Time
tF
Output Fall Time
tSK(O)
tSK(P)
tSK(T)
Conditions1
Parameter
Min2
ASM2P3807A
1.5
50Ω to VCC/2
CL= 10pF
Output skew: skew
between outputs of
same package (same
transition)
Pulse skew: skew
between opposite
transitions of same
output (|tPHL – tPLH|)
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
package type and
speed grade
(See figure 1)
or 10Ω AC
Max
Unit
3
nS
1.5
nS
1.5
nS
0.35
nS
0.35
nS
0.65
nS
termination,
CL= 50pF
(See figure 2)
f≤ 100MHz
Outputs
connected in
groups of two
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
5 of 18
ASM2P3807A
November 2006
rev 0.3
Symbol
tPLH
tPHL
Parameter
Propagation Delay
tR
Output Rise Time
tF
Output Fall Time
tSK(O)
tSK(P)
tSK(T)
Symbol
tPLH
tPHL
Conditions1
ASM2P3807A
Min2
Max
1.5
Output skew: skew between outputs of
same package (same transition)
CL= 30pF
Pulse skew: skew between opposite
transitions of same output (|tPHL – tPLH|)
(See figure 3)
f≤ 67MHz
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Parameter
Conditions1
Propagation Delay
Unit
4
nS
1.5
nS
1.5
nS
0.45
nS
0.45
nS
0.75
nS
ASM2P3807A
Unit
Min2
Max
1.5
4.3
nS
tR
Output Rise Time
1.5
nS
tF
Output Fall Time
1.5
nS
0.35
nS
0.35
nS
0.75
nS
tSK(O)
Output skew: skew between outputs of
same package (same transition)
tSK(P)
Pulse skew: skew between opposite
transitions of same output (|tPHL – tPLH|)
tSK(T)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
CL= 50pF
f≤ 40MHz
(See figure 4)
NOTES:1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delays
limits do not imply skew.
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
6 of 18
ASM2P3807A
November 2006
rev 0.3
Switching Characteristics Over Operating Range - Industrial3,4
Symbol
tPLH
tPHL
Propagation Delay
tR
Output Rise Time
tF
Output Fall Time
tSK(O)
tSK(P)
Conditions1
Parameter
Max
50Ω to VCC/2
CL= 10pF
Output skew: skew
between outputs of
same package (same
transition)
Pulse
skew:
skew
between
opposite
transitions of same
output (|tPHL – tPLH|)
tSK(T)
Symbol
Parameter
tPHL
ASM2P3807A
1.5
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
package
type
and
speed grade
tPLH
Min2
Unit
3
nS
1.5
nS
1.5
nS
0.45
nS
0.45
nS
0.65
nS
(See figure 1)
or 50Ω AC
termination,
CL= 10pF
(See figure 2)
f≤ 100MHz
Outputs
connected in
groups of two
Conditions1
Propagation Delay
Min2
ASM2P3807A
1.5
Max
Unit
4
nS
tR
Output Rise Time
1.5
nS
tF
Output Fall Time
1.5
nS
tSK(O)
Output skew: skew
between outputs of
same package (same
transition)
0.45
nS
0.45
nS
0.75
nS
tSK(P)
tSK(T)
Pulse
skew:
skew
between
opposite
transitions of same
output (|tPHL - tPLH|)
CL= 30pF
f≤ 67MHz
(See figure 3)
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
package type and
speed grade
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
7 of 18
ASM2P3807A
November 2006
rev 0.3
Symbol
tPLH
Conditions1
Parameter
Propagation Delay
Min2
ASM2P3807A
1.5
tPHL
Max
Unit
4.3
nS
tR
Output Rise Time
1.5
nS
tF
Output Fall Time
1.5
nS
Output skew: skew
between outputs of
same package (same
transition)
0.45
nS
0.45
nS
0.75
nS
tSK(O)
tSK(P)
Pulse
skew:
skew
between
opposite
transitions of same
output (|tPHL - tPLH|)
tSK(T)
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
package
type
and
speed grade
CL= 50pF
f≤ 40MHz
(See figure 4)
NOTES:1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min and Max limit is due to VCC, operating temperature and process parameters. These propagation delay limits
do not imply skew.
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
8 of 18
ASM2P3807A
November 2006
rev 0.3
Test Circuits
VCC
VCC
100Ω
VN
VOUT
PULSE
GENERATOR
D.U.T
10pF
100Ω
RT
Figure 1. ZO = 50Ω to VCC/2, CL = 10pF
VCC
VCC
100Ω
VN
VOUT
PULSE
GENERATOR
D.U.T
10pF
RT
50Ω
220pF
Figure 2. ZO = 50Ω AC Termination, CL = 10pF
The capacitor value for ac termination is determined by the operating frequency.
For very low frequencies a higher capacitor value should be selected.
VCC
VN
VOUT
PULSE
GENERATOR
D.U.T
30pF
RT
CL
Figure 3. CL = 30pF Circuit
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
9 of 18
ASM2P3807A
November 2006
rev 0.3
VCC
VN
VOUT
PULSE
GENERATOR
O.U.T
50pF
RT
CL
Figure 3. CL = 50pF Circuit
6V
VCC
GND
500Ω
VN
VOUT
PULSE
GENERATOR
O.U.T
50pF
RT
CL
500Ω
Figure 5. Enable and Disable Time Circuit
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
10 of 18
ASM2P3807A
November 2006
rev 0.3
Enable and Disable Time
Switch Position
Test
Switch
Disable LOW
6V
Enable LOW
Disable HIGH
GND
Enable HIGH
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Waveforms
3V
1.5V
INPUT
tPLH
OV
tPHL
VOH
2.0 V
1.5 V
0.8 V
OUTPUT
tR
VOL
tF
Package Delay
1.5V
INPUT
OV
tPLH
tPLH
VOH
1.5 V
OUTPUT
3V
tSK(p) =[ tPHL – tPLH ]
VOL
Pulse Skew - tSK(P)
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
11 of 18
ASM2P3807A
November 2006
rev 0.3
3V
1.5V
INPUT
tPLH 1
tPLHL
OV
1
VOH
1.5 V
OUTPUT 2
VOL
tSK(0)
tSK(O
VOH
1.5 V
OUTPUT 1
VOL
tPHL2
tPLH2
tSK(O) =[ tPLH2 – tPLH 1 ] or [tPHL2 - tPHL1 ]
Output Skew - tSK(O)
3V
1.5V
INPUT
tPLH 1
tPLHL
OV
1
VOH
1.5 V
PACKAGE 1 OUTPUT
VOL
tSK(t)
tSK(t)
VOH
1.5 V
PACKAGE 2 OUTPUT
tPLH2
tPHL2
VOL
tSK(t) =[ tPLH2 – tPLH 1 ] or [tPHL2 - tPHL1 ]
Package Skew - tSK(T)
Package 1 and Package 2 are same device type and speed grade
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
12 of 18
ASM2P3807A
November 2006
rev 0.3
ENABLE
DISABLE
3V
1.5V
CONTROL
INPUT
0V
tPLZ
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
tPLZ
OUTPUT
NORMALLY
HIGH
3.5V
3.5V
1.5V
SWITCH
OPEN
VOL
tPLZ
1.5V
0V
Enable and Disable Times
0.3V
VOH
0V
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f ≤1.0MHz; tF ≤2.5nS; tR ≤2.5nS
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
13 of 18
ASM2P3807A
November 2006
rev 0.3
Package Information
20-lead SSOP ( 150 mil )
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
0.053
0.069
1.346
1.753
A1
0.004
0.010
0.102
0.254
A2
….
0.059
….
1.499
D
0.337
0.344
8.560
8.738
c
0.007
0.011
0.178
0.274
E
0.228
0.244
5.791
6.198
E1
0.150
0.157
3.810
3.988
L
0.016
0.035
0.406
0.890
L1
0.010 BASIC
0.254 BASIC
b
0.008
0.014
0.203
0.356
R1
0.003
….
0.08
…..
a
0°
8°
0°
8°
e
0.025 BASIC
0.635 BASIC
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
14 of 18
ASM2P3807A
November 2006
rev 0.3
20L SOIC Package (300 mil)
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
0.093
0.104
2.35
2.65
A1
0.004
0.012
0.10
0.30
A2
0.088
0.094
2.25
2.40
D
0.496
0.512
12.60
13.00
L
0.016
0.050
0.40
1.27
E1
0.291
0.299
7.40
7.60
R1
0.003
….
0.08
…..
b
0.013
0.022
0.33
0.56
c
0.009
0.015
0.23
0.38
E
0.394
0.419
10.00
10.65
e
a
0.050 BSC
0°
1.27 BSC
8°
0°
8°
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
15 of 18
ASM2P3807A
November 2006
rev 0.3
20-lead QSOP Package
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
0.060
0.068
1.52
1.73
A1
0.004
0.008
0.10
0.20
b
0.009
0.012
0.23
0.30
c
0.007
0.010
0.18
0.25
D
0.337
0.344
8.56
8.74
E
0.150
0.157
3.81
3.99
e
0.025 BSC
0.64 BSC
H
0.230
0.244
5.84
6.20
h
0.010
0.016
0.25
0.41
L
0.014
0.030
0.35
0.75
S
0.056
0.060
1.42
1.52
a
0°
8°
0°
8°
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
16 of 18
ASM2P3807A
November 2006
rev 0.3
Ordering Information
Part Number
Marking
Package Type
Temperature
ASM2P3807AG-20-AR
2P3807AG
20-Pin SSOP, TAPE & REEL, Green
Commercial
ASM2P3807AG-20-AT
2P3807AG
20-Pin SSOP, TUBE, Green
Commercial
ASM2P3807AG-20-DR
2P3807AG
20-Pin QSOP, TAPE & REEL, Green
Commercial
ASM2P3807AG-20-DT
2P3807AG
20-Pin QSOP, TUBE, Green
Commercial
ASM2P3807AG-20-SR
2P3807AG
20-Pin SOIC, TAPE & REEL, Green
Commercial
ASM2P3807AG-20-ST
2P3807AG
20-Pin SOIC, TUBE, Green
Commercial
ASM2I3807AG-20-AR
2I3807AG
20-Pin SSOP, TAPE & REEL, Green
Industrial
ASM2I3807AG-20-AT
2I3807AG
20-Pin SSOP, TUBE, Green
Industrial
ASM2I3807AG-20-DR
2I3807AG
20-Pin QSOP, TAPE & REEL, Green
Industrial
ASM2I3807AG-20-DT
2I3807AG
20-Pin QSOP, TUBE, Green
Industrial
ASM2I3807AG-20-SR
2I3807AG
20-Pin SOIC, TAPE & REEL, Green
Industrial
ASM2I3807AG-20-ST
2I3807AG
20-Pin SOIC, TUBE, Green
Industrial
Device Ordering Information
A S M 2 P 3 8 0 7 A G - 2 0 - A T
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent Nos 5,488,627 and 5,631,920.
3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
17 of 18
ASM2P3807A
November 2006
rev 0.3
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Copyright © PulseCore Semiconductor
All Rights Reserved
Preliminary Information
Part Number: ASM2P3807A
Document Version: v0.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct
this data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
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3.3V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
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