a High Performance ISM Band ASK/FSK/GFSK Transmitter IC ADF7010 FEATURES Single Chip Low Power UHF Transmitter 902 MHz–928 MHz Frequency Band On-Chip VCO and Fractional-N PLL 2.3 V–3.6 V Supply Voltage Programmable Output Power –16 dBm to +12 dBm, 0.3 dB Steps Data Rates up to 76.8 kbps Low Current Consumption 28 mA at 8 dBm Output Power-Down Mode (<1 A) 24-Lead TSSOP Package GENERAL DESCRIPTION The ADF7010 is a low power OOK/ASK/FSK/GFSK UHF transmitter designed for use in ISM band systems. It contains an integrated VCO and sigma-delta fractional-N PLL. The output power, channel spacing, and output frequency are programmable with four 24-bit registers. The fractional-N PLL enables the user to select any channel frequency within the U.S. 902 MHz–928 MHz band, allowing the use of the ADF7010 in frequency hopping systems. It is possible to choose from the four different modulation schemes: Binary or Gaussian Frequency Shift Keying (FSK/ GFSK), Amplitude Shift Keying (ASK), or On/Off Keying (OOK). The device also features a crystal compensation register that can provide 1 ppm resolution in the output frequency. Indirect temperature compensation of the crystal can be accomplished inexpensively using this register. APPLICATIONS Low Cost Wireless Data Transfer Wireless Metering Remote Control/Security Systems Keyless Entry Control of the four on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.3 V to 3.6 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM CREG CLKOUT CPVDD OSC2 OSC1 CPGND VCOGND CVCO OOK/ASK CLK VCO PA VDD RFOUT RFGND DVDD R PFD/ CHARGE PUMP DGND CREG LDO REGULATOR OOK/ASK TxCLK TxDATA FRACTIONAL N SIGMA-DELTA FSK/GFSK LOCK DETECT LE DATA SERIAL INTERFACE MUXOUT FREQUENCY COMPENSATION MUXOUT RSET CENTER FREQUENCY CLK CE AGND TEST REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 = 2.3 V to 3.6 V, GND = 0 V, T = T to T are at V = 3 V, T = 25C.) ADF7010–SPECIFICATIONS1 (Vspecifications DD A DD Parameter Min RF CHARACTERISTICS Output Frequency Ranges U.S. ISM Band Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Transmit Rate FSK ASK GFSK Frequency Shift Keying FSK Separation2, 3 Gaussian Filter t Amplitude Shift Keying Depth On/Off Keying Output Power Output Power Variation Max Power Setting LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage CLKOUT Rise/Fall Time CLKOUT Mark: Space Ratio POWER SUPPLIES Voltage Supply DVDD Transmit Current Consumption –20 dBm (0.01 mW) –10 dBm (0.1 mW) 0 dBm (1 mW) +8 dBm (6.3 mW) +12 dBm (16 mW) Crystal Oscillator Block Current Consumption Regulator Current Consumption Power-Down Mode Low Power Sleep Mode MAX, unless otherwise noted. Typical Max Unit 902 3.625 928 20 MHz MHz @ 928 MHz 0.3 0.3 0.3 76.8 9.6 76.8 kbps kbps kbps 1 4.88 110 620 kHz, Using 3.625 MHz PFD kHz, Using 20 MHz PFD 30 40 dB, Max Output Power 2 dBm dB 0.5 9 Programmable Step Size –16 dBm to +12 dBm LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance Control Clock Input Typ MIN A 12 11 9.5 dBm, VDD = 3.6 V dBm, VDD = 3.0 V dBm, VDD = 2.3 V 0.3125 dB 0.7 VDD 0.2 VDD 1 10 50 V V mA pF MHz 0.4 V, IOH = 500 mA V, IOL = 500 mA ns, FCLK = 4.8 MHz into 10 pF 3.6 V DVDD – 0.4 16 50:50 2.3 12 15 20 28 40 mA mA mA mA mA 190 380 mA mA 0.2 –2– 1 mA REV. 0 ADF7010 Parameter Min PHASE-LOCKED LOOP VCO Gain Phase Noise (In-Band)4 Phase Noise (Out of Band)5 Spurious Integer Boundary6 Reference Harmonics7 Second Harmonic VDD = 3.0 V Third Harmonic VDD = 3.0 V All Other Harmonics REFERENCE INPUT Crystal Reference External Oscillator Input Level, High Voltage Input Level, Low Voltage FREQUENCY COMPENSATION Pull In Range of Register Typ Unit –14 –18 –18 –35 MHz/V @ 915 MHz dBc/Hz @ 5 kHz Offset dBc/Hz @ 1 MHz Offset 100 kHz Loop BW dBc, 50 kHz Loop dBc dBc dBc dBc dBc 80 –80 –100 –55 –50 –27 –21 3.625 3.625 0.7 VDD 20 40 1 PA CHARACTERISTICS RF Output Impedance High Range Amplifier 16 – j33 TIMING INFORMATION Chip Enabled to Regulator Ready7 Crystal Oscillator to CLKOUT OK 50 2 TEMPERATURE RANGE, TA Max –40 0.2 VDD MHz MHz V V 100 ppm W, ZREF = 50 W 200 ms ms, 19.2 MHz Xtal +85 C NOTES 1 Operating temperature range is as follows: –40∞C to +85∞C. 2 Frequency Deviation = (PFD Frequency Mod Deviation )/2 12. 3 GFSK Frequency Deviation = (PFD Frequency 2m )/212 where m = Mod Control. 4 VDD = 3 V, PFD = 19.2 MHz, PA = 8 dBm 5 VDD = 3 V, Loop Filter BW = 100 kHz 6 Measured >1 MHz away from integer channel. See Successful Design with ADF7010 Transmitter application note. 7 Not production tested. Based on characterization. Specifications subject to change without notice. REV. 0 –3– ADF7010 TIMING CHARACTERISTICS (V DD = 3 V 10%, VGND = 0 V, TA = 25C, unless otherwise noted.) Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 t2 t3 t4 t5 t6 10 10 25 25 10 20 ns min ns min ns min ns min ns min ns min DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth Guaranteed by design but not production tested. t3 t4 CLOCK t1 DATA DB23 (MSB) t2 DB22 DB1 (CONTROL BIT C2) DB2 DB0 (LSB) (CONTROL BIT C1) t6 LE t5 Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS 1, 2 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of <1 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = CPGND = RFGND = DGND = AGND = 0 V. (TA = 25∞C, unless otherwise noted.) VDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.0 V VCOVDD, RFVDD, CPVDD to GND . . . . . –0.3 V to +7 V Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40∞C to +85∞C Storage Temperature Range . . . . . . . . . . . . –65∞C to +125∞C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C TSSOP JA Thermal Impedance . . . . . . . . . . . . . . 150.4∞C/W CSP JA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . . 122∞C/W CSP JA (Paddle Not Soldered) . . . . . . . . . . . . . . . . . 216∞C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235∞C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240∞C ORDERING GUIDE Model Temperature Range Package Option ADF7010BRU –40ºC to +85ºC RU-24 (TSSOP) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF7010 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0 ADF7010 PIN CONFIGURATION RSET 1 24 CREG CPVDD 2 23 CVCO CPGND 3 CPOUT 4 CE 5 22 VCOIN TSSOP 21 AGND ADF7010 20 RFOUT 19 RFGND DATA 6 TOP VIEW CLK 7 (Not to Scale) LE 8 18 DVDD 17 TEST TxDATA 9 16 VCOGND TxCLK 10 15 OSC1 MUXOUT 11 14 OSC2 DGND 12 13 CLKOUT PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 4.7 kW as default: I CP MAX = 9.5 RSET So, with RSET = 4.7 kW, ICPMAX = 2.02 mA. 2 CPVDD Charge Pump Supply. This should be biased at the same level as RFVDD and DVDD. The pin should be decoupled with a 0.1 mF capacitor as close to the pin as possible. 3 CPGND Charge Pump Ground 4 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 5 CE Chip Enable. A logic low applied to this pin powers down the part. This must be high for the part to function. This is the only way to power down the regulator circuit. 6 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. 7 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input. 8 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 9 TxDATA Digital data to be transmitted is input on this pin. 10 TxCLK GFSK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the ADF7010. The clock is provided at the same frequency as the data rate. 11 MUXOUT This multiplexer output allows either the digital lock detect (most common), the scaled RF, or the scaled reference frequency to be accessed externally. Used commonly for system debug. See Function Register Map. 12 DGND Ground Pin for the RF Digital Circuitry 13 CLKOUT The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be used to drive the clock input of a microcontroller. To reduce spurious components in the output spectrum, the sharp edges can be reduced with a series RC. For 4.8 MHz output clock, a series 50 W into 10 pF will reduce spurs to < –50 dBc. Defaults on power-up to divide by 16. 14 OSC2 Oscillator Pin. If a single-ended reference is used (such as a TCXO), it should be applied to this pin. When using an external signal generator, a 51 W resistor should be tied from this pin to ground. The XOE bit in the R Register should set high when using an external reference. REV. 0 –5– ADF7010 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Function 15 OSC1 Oscillator Pin. For use with crystal reference only. This is three-stated when an external reference oscillator is used. 16 VCOGND Voltage Controlled Oscillator Ground 17 TEST Input to the RF fractional-N divider. This pin allows the user to connect an external VCO to the part. Disabling the internal VCO activates this pin. If the internal VCO is used, this pin should be grounded. 18 DVDD Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 19 RFGND Ground for Output Stage of Transmitter 20 RFOUT The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output should be impedance matched to the desired load using suitable components. See the Output RF Stage section. 21 AGND Ground Pin for the RF Analog Circuitry 22 VCOIN The tuning voltage on this pin determines the output frequency of the Voltage Controlled Oscillator (VCO). The higher the tuning voltage the higher the output frequency. 23 CVCO A 0.22 mF capacitor should be added to reduce noise on VCO bias lines. Tied to CREG pin. 24 CREG A 2.2 mF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor will improve regulator power-on time but may cause higher spurious components. –6– REV. 0 Typical Performance Characteristics–ADF7010 RL = 10.0dBm 935.000MHz 918.000MHz VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz RBW = 1kHz SPAN 5.000MHz 915.7MHz 901.000MHz –20.00s TPC 1. FSK Modulated Signal, FDEVIATION = 58 kHz, Data Rate = 19.2 kbps/s, 10 dBm RL = 10.0dBm 2dBm 5.00s 5.00s/DIV 30.00s TPC 4. PLL Settling Time, 902 MHz to 928 MHz, 23 s (± 400 kHz) +10dBm VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 1MHz RBW = 3kHz VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz RBW = 100kHz –36dBm @ 200kHz +19.2MHz –61dBc 915.7MHz SPAN 500kHz RBW 100kHz TPC 2. OOK Modulated Signal, Data Rate = 4.8 kbps/s, 4 dBm 915.7MHz SPAN 50.00MHz TPC 5. PFD Spurious/Fractional Spurious +10dBm +10dBm SECOND HARMONIC –22dBc THIRD HARMONIC –34dBc VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz RBW = 30Hz PN @ 4kHz 80dBc/Hz START 800MHz RBW 1.0MHz STOP 7.750GHz 915.7MHz TPC 3. Harmonic Levels at 10 dBm Output Power. See Figure 15. REV. 0 SPAN 10.00kHz TPC 6. In-Band Phase Noise –7– ADF7010 110 VDD = 3V TA = 25C C1 FREQ 1.6MHz C1 RISE 144.8ns C1 FALL 145.6ns C1 +DUTY 49.385 100 GAIN – MHz/V 90 80 70 60 50 Ch1 500mV M 200ns 40 885 895 TPC 7. 1.6 MHz CLOCKOUT Waveform 905 915 FREQUENCY 935 925 945 TPC 10. Typical VCO Gain 20 +10dBm 15 VDD = 3V PFD FREQUENCY = 19.2MHz LOOP BW = 100kHz RBW = 10Hz 10 VDD = 2.2V VDD = 3.0V VDD = 3.6V LEVEL – dBm 5 +1.6MHz –53dBc LOW RANGE MID RANGE 0 HIGH RANGE –5 –10 –15 –20 –25 915.7MHz –30 SPAN 5.00MHz 40 60 80 100 PA SETTING – MODULATION REGISTER 120 TPC 11. PA Output Programmability, TA = 25∞C TPC 8. Spurious Signal Generated by CLOCKOUT 0 44 42 CURRENT – mA SENSITIVITY – dBm –5 –10 –15 40 38 36 34 –20 32 –25 0.8 0.9 1.0 1.1 1.2 FREQUENCY – GHz 1.3 30 2.2 1.4 TPC 9. N-Divider Input Sensitivity 2.4 2.6 3.2 2.8 3.0 SUPPLY VOLTAGE – V 3.4 3.6 TPC 12. IDD vs. VDD @ 10 dBm –8– REV. 0 ADF7010 REGISTER MAPS XOE RF R REGISTER CLKOUT RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 R2 R1 CL4 CL3 CL2 CL1 X1 R4 R3 R2 CONTROL BITS 11-BIT FREQUENCY ERROR CORRECTION 4-BIT R-VALUE R1 F11 F10 F9 F8 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F7 F6 F5 F4 F3 F2 F1 DB1 DB0 C2 (0) C1 (0) VCO BAND LD PRECISION RF N REGISTER 8-BIT INTEGER-N DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 LDP V1 N8 N7 N6 N5 N4 CONTROL BITS 12-BIT FRACTIONAL-N N3 N2 N1 M12 M11 M10 M9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M8 M7 M6 M5 M4 M3 M2 M1 C2 (0) C1 (1) PRESCALER MODULATION REGISTER INDEX COUNTER GFSK MOD CONTROL MODULATION DEVIATION DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P1 IC2 IC1 MC3 MC2 MC1 D7 D6 D5 D4 D3 MODULATION SCHEME POWER AMPLIFIER D2 D1 P7 P6 DB8 DB7 DB6 DB5 DB4 DB3 DB2 P5 P4 P3 P2 P1 S2 S1 CONTROL BITS DB1 DB0 C2 (1) C1 (0) REV. 0 T6 T5 T4 T3 T2 T1 M4 M3 M2 M1 –9– VP1 PLL ENABLE T7 PA ENABLE T8 DB8 DB7 DB6 DB5 DB4 DB3 DB2 CP3 CP2 CP1 I1 PD3 PD2 PD1 FAST LOCK DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 T9 CLKOUT ENABLE MUXOUT DATA INVERT TEST MODES VCO DISABLE FUNCTION REGISTER CP4 CHARGE PUMP CONTROL BITS DB1 DB0 C2 (1) C1 (1) ADF7010 XOE RF R REGISTER CLKOUT RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 R2 R1 CL4 CL3 CL2 CL1 X1 R4 R3 R2 CONTROL BITS 11-BIT FREQUENCY ERROR CORRECTION 4-BIT R-VALUE R1 X1 XOE 0 1 XTAL OSCILLATOR ON XTAL OSCILLATOR OFF F11 F10 F9 F8 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F7 F6 F5 F4 F3 F2 F1 F11 0 0 0 0 0 ........... ........... ........... ........... ........... DB1 DB0 C2 (0) C1 (0) F3 F2 F1 1 1 . 0 0 1 1 . 0 0 1 0 . 1 0 F-COUNTER OFFSET 1023 1022 . 1 0 ......................................................................................................................................................... 1 1 ........... ........... ........... ........... ........... 1 1 1 1 . 0 0 1 1 . 0 0 1 0 . 1 0 1 2 . 1023 1024 15 e.g., F-COUNTER OFFSET = 1, FRACTIONAL OFFSET = 1/2 CL4 CL3 CL2 CL1 CLKOUT DIVIDE RATIO 0 0 0 0 . . . 1 0 0 0 1 . . . 1 0 1 1 0 . . . 0 1 0 1 0 . . . 0 2 4 6 8 . . . 24 1 1 0 1 26 1 1 1 0 28 1 1 1 1 30 RF R COUNTER DIVIDE RATIO R4 R3 R2 R1 0 0 0 0 . . . 1 0 0 0 1 . . . 1 0 1 1 0 . . . 0 1 0 1 0 . . . 0 1 2 3 4 . . . 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 –10– REV. 0 ADF7010 VCO BAND LD PRECISION RF N REGISTER CONTROL BITS 12-BIT FRACTIONAL-N 8-BIT INTEGER-N DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 LDP M8 M7 M6 M5 M4 M3 V1 N8 N7 N6 N5 N4 N3 N2 N1 M12 M11 M10 M9 DB3 DB2 M2 M1 DB1 e.g., SETTING F = 0 IN FSK MODE TURNS ON THE SIGMA-DELTA WHILE THE PLL IS AN INTEGER VALUE M3 M2 M1 MODULUS DIVIDE RATIO .......... .......... .......... .......... .......... .......... .......... 1 1 1 . . . 1 0 0 1 . . . 0 0 1 0 . . . 0 4 5 6 . . . 4092 1 .......... 1 0 1 4093 1 .......... 1 1 0 4094 1 .......... 1 1 1 4095 M12 M11 M10 0 0 0 . . . 1 0 0 0 . . . 1 0 0 0 . . . 1 1 1 1 1 1 1 e.g., MODULUS DIVIDE RATIO = 2048 –> FRACTION 1/2 REV. 0 V1 VCO BAND MHZ 0 1 902–928 451–464 LDP LOCK DETECT PRECISION 0 1 3 CYCLES <15ns 5 CYCLES <15ns N8 N7 N6 N5 N4 N3 N2 N1 N COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 1 1 1 . . . 1 1 0 0 0 . . . 1 1 0 0 0 . . . 1 1 0 0 0 . . . 1 1 0 0 1 . . . 0 1 0 1 0 . . . 1 31 32 33 34 . . . 253 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255 THE N-VALUE CHOSEN IS A MINIMUM OF P2 + 3P + 3. FOR PRESCALER = 8/9 THIS MEANS A MINIMUM N DIVIDE OF 91. –11– DB0 C2 (0) C1 (1) ADF7010 PRESCALER MODULATION REGISTER INDEX COUNTER GFSK MOD CONTROL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P1 IC2 IC1 MC3 MC2 MC1 D7 D6 D5 D4 D3 D2 D1 P7 P6 DB8 DB7 DB6 DB5 DB4 DB3 DB2 P5 P4 P3 P2 P1 S2 S1 P1 RF PRESCALER 0 1 4/5 8/9 D6 . D2 D1 0 0 0 . 0 1 1 . 1 1 1 1 1 0 1 1 . 1 0 0 . 0 1 1 1 1 . . . . . . . . . . . . . X 0 0 . 1 0 0 . 1 0 0 . 1 X 0 1 . 1 0 1 . 1 0 1 . 1 PA OFF 16.0dBm 161(10/32) . 1631(10/32) 6dBm 61(10/32) . 61(10/32) 2dBm 21(10/32) . 12dBm D2 D1 F DEVIATION 0. 0. 0. 0. . 1. 0 0 0 0 . 1 0 0 1 1 . 1 0 PLL MODE 11 FSTEP 02 FSTEP 13 FSTEP ............... 127 FSTEP . . . . . . . . DB0 S2 S1 MODULATION SCHEME 0 0 1 1 0 1 0 1 FSK GFSK ASK OOK P6 . P2 P1 0 0 0 . 0 1 1 . 1 1 1 1 1 0 1 1 . 1 0 0 . 0 1 1 1 1 . . . . . . . . . . . . . X 0 0 . 1 0 0 . 1 0 0 . 1 X 0 1 . 1 0 1 . 1 0 1 . 1 PA OFF 16.0dBm 161(10/32) . 1631(10/32) 6dBm 61(10/32) . 61(10/32) 2dBm 21(10/32) . 12dBm 12 D3 . . . . DB1 C2 (1) C1 (0) P7 IF FREQUENCY SHIFT KEYING SELECTED D7. . . . . . . . CONTROL BITS POWER AMPLIFIER OUTPUT LEVEL IF AMPLITUDE SHIFT KEYING SELECTED, TxDATA = 0 D7 MODULATION SCHEME POWER AMPLIFIER MODULATION DEVIATION FSTEP = FPFD/2 IF GAUSSIAN FREQUENCY SHIFT KEYING SELECTED IC2 IC1 D7 0 0 0 0 . 1 INDEX COUNTER 0 0 1 1 0 1 0 1 16 32 64 128 MC3 MC2 MC1 0 0 . 1 0 0 . 1 0 1 . 1 D3 0 0 0 0 . 1 D2 0 0 1 1 . 1 D1 0 1 0 1 . 1 DIVIDER FACTOR 0 1 2 3 ...... 127 GFSK MOD CONTROL 0 1 . 7 –12– REV. 0 ADF7010 T6 T5 T4 T3 T2 T1 M4 M3 M2 M1 VP1 VCO DISABLE 0 VCO ON 1 VCO OFF CP4 PLL ENABLE T7 PA ENABLE T8 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CP4 CP3 C2 C1 I1 PD3 PD2 PD1 C2 (1) C1 (1) CHARGE PUMP FAST LOCK DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 T9 CLKOUT ENABLE MUXOUT DATA INVERT TEST MODES VCO DISABLE FUNCTION REGISTER VP1 I1 DATA INVERT 0 DATA 1 DATA CP FLOCK DOWN PD1 PLL ENABLE 0 BLEED OFF 0 PLL OFF 1 BLEED ON 1 PLL ON CP2 0 0 1 1 CP3 CP FLOCK UP 0 BLEED OFF 1 BLEED ON CP1 RSET 0 1 0 1 PD2 M4 M3 M2 M1 MUXOUT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LOGIC LOW LOGIC HIGH THREE-STATE REGULATOR READY (DEFAULT) DIGITAL LOCK DETECT ANALOG LOCK DETECT R DIVIDER / 2 OUTPUT N DIVIDER / 2 OUTPUT RF R DIVIDER OUTPUT RF N DIVIDER OUTPUT DATA RATE LOGIC LOW LOGIC LOW LOGIC LOW NORMAL TEST MODES SIGMA-DELTA TEST MODES –13– PA ENABLE 0 PA OFF 1 PA ON ICP (mA) 2.7k 4.7k 10k 0.50 1.50 2.51 3.51 0.29 0.87 1.44 2.02 0.14 0.41 0.68 0.95 PD3 REV. 0 CONTROL BITS CLKOUT 0 CLKOUT OFF 1 CLKOUT ON ADF7010 DEFAULT VALUES FOR REGISTERS RESERVED XOE R REGISTER CLKOUT DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 0 1 0 0 0 0 0 0 0 CONTROL BITS 11-BIT FREQUENCY ERROR CORRECTION 4-BIT R-VALUE 1 0 0 0 0 DB8 DB7 DB6 DB5 DB4 DB3 DB2 0 0 0 0 0 0 0 0 DB1 DB0 C2 (0) C1 (0) VCO BAND LD PRECISION N REGISTER 8-BIT INTEGER-N DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 0 1 0 0 0 CONTROL BITS 12-BIT FRACTIONAL-N 0 0 0 0 1 0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 C2 (0) C1 (1) 0 PRESCALER MODULATION REGISTER INDEX COUNTER GFSK MOD CONTROL DB23 DB22 DB21 DB20 1 0 0 MODULATION DEVIATION DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 0 0 0 0 0 0 0 0 MODULATION SCHEME POWER AMPLIFIER 0 0 1 DB8 DB7 DB6 DB5 DB4 DB3 DB2 0 0 0 0 0 0 0 1 CONTROL BITS DB1 DB0 C2 (1) C1 (0) 0 0 0 0 0 0 0 0 0 0 1 1 –14– 0 PLL ENABLE 0 PA ENABLE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 CLKOUT ENABLE MUXOUT DATA INVERT TEST MODES VCO DISABLE FUNCTION REGISTER DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 0 0 1 1 0 1 0 0 FAST LOCK CHARGE PUMP CONTROL BITS DB1 DB0 C2 (1) C1 (1) REV. 0 ADF7010 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION PRESCALER, PHASE FREQUENCY DETECTOR (PFD), AND CHARGE PUMP The on-board crystal oscillator circuitry (Figure 2), allows the use of an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting XOE low. It is enabled by default on power-up and is disabled by bringing CE low. Two parallel resonant capacitors are required for oscillation at the correct frequency; the value of these is dependent on the crystal specification. Errors in the crystal can be corrected using the Error Correction register within the R Register. A singleended reference (TCXO, CXO) may be used. The CMOS levels should be applied to OSC2, with XOE set high. The dual-modulus prescaler (P/P + 1) divides the RF signal from the VCO to a lower frequency that is manageable by the CMOS counters. The PFD takes inputs from the R Counter and the N Counter (N = Int + Fraction) and produces an output proportional to the phase and frequency difference between them. Figure 4 is a simplified schematic. VP HI OSC2 10pF D1 Q1 U1 R DIVIDER 100k OSC1 CLR1 100k NC 500k DELAY ELEMENT 10pF BUFFER SW1 XTAL OSCILLATOR DISABLED CLR2 HI Q2 DOWN N DIVIDER The CLKOUT circuit takes the reference clock signal from the oscillator section above and supplies a divided down 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide is set by the 4 MSBs in the R register. On power-up, the CLKOUT defaults to divide by 16. CPGND R DIVIDER DVDD N DIVIDER CLKOUT ENABLE BIT DIVIDE BY 2 CP OUTPUT Figure 4. PFD Stage CLKOUT The PFD includes a delay element that sets the width of the antibacklash pulse. The typical value for this in the ADF7010 is 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Figure 3. CLKOUT Stage The output buffer to CLKOUT is enabled by setting Bit DB4 in the function register high. On power-up, this bit is set high. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 W) can be used to slow the clock edges to reduce these spurs at FCLK. R COUNTER The 4-bit R Counter divides the reference input frequency by an integer from 1 to 15. The divided down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in the R register. Maximizing the PFD frequency reduces the N-value. This reduces the noise multiplied at a rate of 20 log(N) to the output, as well as reducing occurrences of spurious components. The R register defaults to R = 1 on power-up. REV. 0 D2 U2 CLKOUT DIVIDER AND BUFFER DIVIDER 1 TO 15 CP U3 TO R COUNTER, AND CLOCK OUT DIVIDE Figure 2. Oscillator Circuit on the ADF7010 OSC1 CHARGE PUMP UP MUXOUT AND LOCK DETECT The MUXOUT pin allows the user to access various internal points in the ADF7010. The state of MUXOUT is controlled by Bits M1 to M4 in the function register. REGULATOR READY This is the default setting on MUXOUT after the transmitter has been powered up. The power-up time of the regulator is typically 50 ms. Since the serial interface is powered from the regulator, it is necessary for the regulator to be at its nominal voltage before the ADF7010 can be programmed. The status of the regulator can be monitored at MUXOUT. Once the REGULATOR READY signal on MUXOUT is high, programming of the ADF7010 may begin. –15– ADF7010 DVDD REGULATOR READY DIGITAL LOCK DETECT ANALOG LOCK DETECT MUX CONTROL MUXOUT R COUNTER/2 OUTPUT N COUNTER/2 OUTPUT R COUNTER OUTPUT N COUNTER OUTPUT DGND Figure 5. MUXOUT Stage Digital Lock Detect Digital lock detect is active high. The lock detect circuit is contained at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until 25 ns phase error is detected at the PFD. Since no external components are needed for digital lock detect, it is more widely used than analog lock detect. CHARGE PUMP OUT VCO Analog Lock Detect Figure 6. Typical Loop Filter Configuration–– Third Order Integrator This N-channel open-drain lock detect should be operated with an external pull-up resistor of 10 kW nominal. When lock has been detected, this output will be high with narrow low going pulses. VOLTAGE REGULATOR The ADF7010 requires a stable voltage source for the VCO and modulation blocks. The on-board regulator provides 2.2 V using a band gap reference. A 2.2 mF capacitor from CREG to ground is used to improve stability of the regulator over a supply from 2.3 V to 3.6 V. The regulator consumes less than 400 mA and can only be powered down using the chip enable (CE) pin. Bringing the chip enable pin low disables the regulator and also erases all values held in the registers. The serial interface operates off the regulator supply; therefore, to write to the part, the user must have CE high. Regulator status can be monitored using the Regulator Ready signal from MUXOUT. LOOP FILTER The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop filter design is shown in Figure 6. In FSK, the loop should be designed so that the loop bandwidth (LBW) is approximately 5 times the data rate. Widening the LBW excessively reduces the time spent jumping between frequencies but may cause insufficient spurious attenuation. For ASK systems, the wider the loop BW the better. The sudden large transition between two power levels will result in VCO pulling and can cause a wider output spectrum than is desired. By widening the loop BW to >10 times the data rate, the amount of the VCO pulling is reduced, since the loop will settle quickly back to the correct frequency. The wider LBW may restrict the output power and data rate of ASK based systems, compared with FSK based systems. Narrow loop bandwidths may result in the loop taking long periods of time to attain lock. Careful design of the loop filter is critical in obtaining accurate FSK/GFSK modulation. For GFSK, it is recommended that an LBW of 2.0 to 2.5 times the data rate be used to ensure sufficient samples are taken of the input data while filtering system noise. –16– REV. 0 ADF7010 VOLTAGE CONTROLLED OSCILLATOR (VCO) LOW An on-chip VCO is included on the transmitter. The VCO converts the control voltage generated by the loop filter into an output frequency that is sent to the antenna via the power amplifier (PA). The VCO has a typical gain of 80 MHz/V and operates from 900 MHz–940 MHz. The PD1 bit in the function register is the active high bit that turns on the VCO. A frequency divide by 2 is included to allow operation in the lower 450 MHz band. To enable operation in the lower band, the V1 bit in the N Register should be set to 1. MED HIGH The VCO needs an external 220 nF between the VCO and the regulator to reduce internal noise. P5 P1 P7, P6 Figure 8. Output Stage VCO CONTROL BIT SERIAL INTERFACE The serial interface allows the user to program the four 24-bit registers using a 3-wire interface. (CLK, Data, and Load Enable). MUX VCO LOOP FILTER TO PA AND N DIVIDER The serial interface consists of a level shifter, 24-bit shift register, and four latches. Signals should be CMOS compatible. The serial interface is powered by the regulator, and therefore is inactive when CE is low. DIVIDE BY 2 220nF Table I. C2, C1 Truth Table CREG PIN VCO SELECT BIT Figure 7. Voltage Controlled Oscillator RF OUTPUT STAGE The RF output stage consists of a DAC with a number of current sources to adjust the output power level. To set up the power level: FSK GFSK: The output power is set using the modulation register by entering a 7-bit number into the bits P1–P7. The two MSBs set the range of the output stage, while the five LSBs set the output power in the selected range. C2 C1 Data Latch 0 0 1 1 0 1 0 1 R Register N Register Modulation Register Function Register Data is clocked into the shift register, MSB first, on the rising edge of each clock (CLK). Data is transferred to one of four latches on the rising edge of LE. The destination latch is determined by the value of the two control bits (C2 and C1). These are the two LSBs, DB1 and DB0, as shown in the timing diagram of Figure 1. ASK: The output power as set up for FSK is the output power for a TxDATA of 1. The output power for a zero data bit is set up the same way but using the bits D1–D7. VDD L1 PA The output stage is powered down by setting bit PD2 in the Function register to zero. RFOUT L2 C1 50 Figure 9. Output Stage Matching REV. 0 –17– ADF7010 M12 M11 M10 0.20 0.00 0.0 0.50 1.00 M9 M7 M6 M5 M4 M3 M2 M1 F6 F5 F4 F3 F2 F1 N3 N2 N1 N0 12-BIT N VALUE L(SERIES) = 6.8nH F10 F9 F8 F7 5.00 0.20 10-BIT ( SIGN) ERROR CORRECTION L(SHUNT) = 12nH 30 150 16 – j33 140 130 1.00 110 100 90 80 N14 N13 N12 N11 N10 40 2.00 0.50 120 50 N6 N5 N4 Changing the Output Frequency The prescaler can be 4/5 or 8/9. The spurious performance is better with a 4/5 prescaler, and the N-value can be lower since NMIN is P 2 + 3P + 3. The fractional part of the N Register changes the output frequency by: ( FPFD )( N -Register Value ) 212 The frequency error correction contained in the R Register changes the output frequency by: ( FPFD )( Frequency Error Correction Value ) 215 The output frequency of the PLL is: Int + (23 ¥ Fractional ) + Error 215 REFERENCE IN VCO N By default, this will be set to 0. The user can calibrate the system and set this by writing a twos complement number to Bits F1–F11 in the R Register. This can be used to compensate for initial error, temperature drift, and aging effects in the crystal reference. Integer N Register The integer part of the N-Counter contains the prescaler and A and B counters. It is eight bits wide and offers a divide of P 2 + 3P + 3 to 255. The combination of the integer (255) and the fractional (31767/ 31768) give a maximum N Divider of 256. The minimum PFD usable is: THIRD ORDER - MODULATOR FRACTIONAL N N7 The resolution of each register is the smallest amount that the output frequency can be changed by changing the LSB of the register. The ADF7010 consists of a 15-bit sigma-delta fractional N divider. The N Counter divides the output frequency to the output stage back to the PFD frequency. It consists of a prescaler, integer, and fractional part. PFD/ CHARGE PUMP N8 Figure 12. Fractional Components 70 FRACTIONAL-N N COUNTER AND ERROR CORRECTION PFD Frequency ¥ N9 15-BIT FRACTIONAL N REGISTER 60 Figure 10. Output Impedance on Smith Chart R M8 5.00 2.00 FPFD (min) = INTEGER N Figure 11. Fractional-N PLL Fractional-N Registers The fractional part is made up of a 15-bit divide, made up of a 12-bit N value in the N Register summed with a 10-bit (plus sign bit) in the R-Register that is used for error correction, as shown in Figure 12. Maximum Output Frequency Required (255 + 1) For use in the U.S. 902 MHz–928 MHz band, there is a restriction to using a minimum PFD of 3.625 MHz to allow the user to have a center frequency of 928 MHz. PFD Frequency The PFD frequency is the number of times a comparison is made between the reference frequency and the feedback signal from the output. The higher the PFD frequency, the more often a comparison is made at the PFD. This also allows a wider loop bandwidth without compromising stability. This means that the frequency lock time will be reduced when jumping from one frequency to another by increasing the PFD. –18– REV. 0 ADF7010 The N divide in the integer part is also reduced. This results in less noise being multiplied from the PFD to the output, resulting in better phase noise for higher PFDs. Setting up the ADF7010 for GFSK To set up the frequency deviation, set the PFD and the mod control Bits MC1 to MC3: Increasing the PFD reduces your resolution at the output. GFSK DEVIATION ( Hz ) = MODULATION SCHEMES Frequency Shift Keying (FSK) where m is mod control. Frequency shift keying is implemented by setting the N value for the center frequency and then toggling this with the TxDATA line. The deviation from the center frequency is set using Bits D1–D7 in the Modulation register. The deviation from the center frequency in Hz is: FDEVIATION ( Hz ) = Modulation Number ¥ FPFD 212 R INTERNAL VCO USING SPIRAL INDUCTORS GAIN 70 MHz/V – 90 MHz/V PA STAGE PFD/ CHARGE PUMP VCO TxDATA FRACTIONAL N Gaussian Frequency Shift Keying (GFSK) Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the TxDATA. A TxCLK output line is provided from the ADF7010 for synchronization of TxDATA from the microcontroller. The TxCLK line may be connected to the clock input of an external shift register that clocks data to the transmitter at the exact data rate. SHIFT REGISTER ANTENNA TxDATA ADF7010 TxCLK Figure 14. TxCLK Pin Synchronizing Data for GFSK REV. 0 For further information, refer to the Using GFSK on the ADF7010 application note. On-Off Keying (OOK) CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE INTEGER N Figure 13. FSK Implementation DATA FROM MICROCONTROLLER FPFD Divider Factor ¥ Index Counter On-off keying is implemented by switching the output stage to a certain power level for a high TxDATA bit and switching the output stage off for a zero. Due to feedthrough effects, a maximum modulation depth of 33 dB is specified. For OOK, the transmitted power for a high input is programmed using Bits P1–P7 in the Modulation register. OOK is selected by setting Bits S1 and S2 to 1 in the modulation register. THIRD ORDER - MODULATOR +FDEV Data Rate(bits s ) = Amplitude shift keying is implemented by switching the output stage between two discrete power levels. This is implemented by toggling the DAC, which controls the output level between two 7-bit values set up in the Modulation register. A zero TxDATA bit sends Bits D1–D7 to the DAC. A high TxDATA bit sends Bits P1–P7 to the DAC. A maximum modulation depth of 30 dB is possible. ASK is selected by setting Bit S2 = 1 and Bit S1 = 0. FSK DEVIATION FREQUENCY –FDEV To set up the GFSK data rate: Amplitude Shift Keying (ASK) The modulation number is a number from 1 to 127. FSK is selected by setting Bits S1 and S2 to zero in the modulation register. CHEAP AT CRYSTAL 2m ¥ FPFD 212 The fractional-N PLL allows the selection of any channel within 902 MHz to 928 MHz to a resolution of < 100 Hz, as well as facilitating frequency hopping systems. The use of the ADF7010 in accordance with FCC Part 15.247, allows for improved range by allowing power levels up to 1 W, and greater interference avoidance by changing the RF channel on a regular basis. Careful selection of the RF transmit channels must be made to achieve best spurious performance. The architecture of Fractional-N results in some level of the nearest integer channel moving through the loop to the RF output. These “beat-note” spurs are not attenuated by the loop if the desired RF channel and the nearest integer channel are separated by a frequency of less than the loop BW. The occurrence of beat-note spurs is rare, as the integer frequencies are at multiples of the reference, which is typically > 10 MHz. The beat-note spurs can be significantly reduced in amplitude by avoiding very small or very large values in the fractional register. By having a channel 1 MHz away from an integer frequency, a 100 kHz loop filter will reduce the level to < –45 dBc. When using an external VCO, the Fast Lock (bleed) function will reduce the spurs to < –60 dBc for the same conditions above. –19– ADF7010 2.2F 220nF DVDD CPVDD CVCO CREG RSET 12nH 6.8nH 100pF 6.8nH ANTENNA RFOUT VCOIN CPOUT C03143–0–11/02(0) 4.7k 6.2pF VCOIN 6.2pF ADF7010 TxDATA LE CLK OSC2 DATA 19.2MHz OSC1 CE 10pF MUXOUT CLKOUT TEST 10pF GND LOCK DETECT 50 DECOUPLING CAPACITORS HAVE BEEN OMITTED FOR CLARITY. 4.8MHZ CLOCK Figure 15. Application Diagram OUTLINE DIMENSIONS 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 PRINTED IN U.S.A. PIN 1 1.20 MAX SEATING PLANE 0.20 0.09 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AD –20– REV. 0