Configurable, High g, iMEMS Accelerometer ADXL180 FEATURES GENERAL DESCRIPTION Wide sensor range: 50 g to 500 g Adjustable filter bandwidth: 100 Hz to 800 Hz Configurable communication protocol 2-wire, current mode bus interface Selectable sensor data resolution: 8 bit or 10 bit Continuous auto-zero Fully differential sensor and interface circuitry High resistance to EMI/RFI Sensor self-test 5.0 V to 14.5 V operation 8 bits of user-defined OTP memory 32-bit electronic serial number Dual device per bus option The ADXL180 iMEMS® accelerometer is a configurable, single axis, integrated satellite sensor that enables low cost solutions for front and side impact airbag applications. Acceleration data is sent to the control module via a digital 2-wire current loop interface bus. The communication protocol is programmable for compatibility with various automotive interface bus standards. The sensor g range is configurable to provide full-scale ranges from ±50 g to ±500 g. The sensor signal third-order, low-pass Bessel filter bandwidth is configurable at 100 Hz, 200 Hz, 400 Hz, and 800 Hz. The 10-bit analog-to-digital converter (ADC) allows either 8-bit or 10-bit acceleration data to be transmitted to the control module. Each part has a unique electronic serial number. The device is rated for operation from −40°C to +125°C and is available in a 5 mm × 5 mm LFCSP package. APPLICATIONS Crash sensing FUNCTIONAL BLOCK DIAGRAM ADXL180 VSCI SERIAL NUMBER OSCILLATOR/ TIMING GENERATOR V/Q OTP FUSE ROM SERIAL PORT VBP COMM INTERFACE TRIMS VBC VBN SYNC DETECT CONFIGURATION DATA PROGRAM INTERFACE MOD DIFF SENSOR DEMOD AMP 3-POLE BESSEL FILTER 10BIT ADC AUTOZERO STATE MACHINE VOLTAGE REGULATOR VDD SUPPLY MONITOR VCM REF 07544-001 VCM SELFTEST VSCO Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADXL180 TABLE OF CONTENTS Features .............................................................................................. 1 Phase 3: Self-Test Diagnostic .................................................... 35 Applications ....................................................................................... 1 Phase 4: Auto-Zero Initialization ............................................. 38 General Description ......................................................................... 1 Phase 5: Normal Operation ...................................................... 38 Functional Block Diagram .............................................................. 1 Signal Range and Filtering ............................................................ 39 Revision History ............................................................................... 3 Transfer Function Overview ..................................................... 39 Specifications..................................................................................... 4 Range............................................................................................ 39 Absolute Maximum Ratings............................................................ 7 Three-Pole Bessel Filter ............................................................. 39 ESD Caution .................................................................................. 7 Auto-Zero Operation ................................................................. 39 Pin Configuration and Function Descriptions ............................. 8 Error Detection ............................................................................... 41 Terminology ...................................................................................... 9 Overview ..................................................................................... 41 Theory of Operation ...................................................................... 10 Overview...................................................................................... 10 Parity Error Due to Communications Protocol Configuration Bit Error ....................................................................................... 41 Acceleration Sensor .................................................................... 10 Self-Test Error ............................................................................. 42 Signal Processing ........................................................................ 11 Offset Error/Offset Drift Monitoring ...................................... 42 Digital Communications State Machine ................................. 11 Voltage Regulator Monitor Reset Operation .......................... 42 2-Wire Current Modulated Interface....................................... 11 Test and Diagnostic Tools ............................................................. 43 Synchronous Operation and Dual Device Bus ....................... 11 VSCI Signal Chain Input Test Pin .............................................. 43 Programmed Memory and Configurability............................ 11 VSCO Analog Signal Chain Output Test Pin ............................ 43 Physical Interface ............................................................................ 13 Configuration Specification .......................................................... 44 Application Circuit ..................................................................... 13 Overview ..................................................................................... 44 Current Modulation ................................................................... 13 Configuration Mode Transmit Communications Protocol.. 45 Manchester Data Encoding ....................................................... 14 Configuration Mode Command (Receive) Communications Protocol........................................................................................ 46 Operation at Low VBP or Low VDD............................................ 14 Operation at High VDD ............................................................... 14 Communications Timing and Bus Topologies ........................... 15 Asynchronous Communication ............................................... 15 Configuration Mode Communications Handshaking .......... 47 Configuration and User Data Registers .................................. 48 Configuration Mode Exit .......................................................... 48 Synchronous Communication .................................................. 15 Serial Number and Manufacturer Identification Data Registers ....................................................................................... 48 Synchronous Communication Mode—Dual Device ............. 17 Programming the Configuration and User Data Registers .. 48 Data Frame Definition ................................................................... 21 OTP Programming Conditions and Considerations ............ 49 Data Frame Transmission Format............................................ 21 Configuration/User Register OTP Parity ................................ 49 Data Frame Configuration Options ......................................... 21 Configuration Mode Error Reporting ..................................... 49 Acceleration Data Coding ......................................................... 23 Configuration Register Reference ................................................ 50 State Vector Coding ................................................................... 24 UD[7:0] User Data Bits.............................................................. 51 State Vector Descriptions .......................................................... 24 UD8 Configuration Bit .............................................................. 51 Transmission Error Detection Options ................................... 25 BDE .............................................................................................. 51 Application Layer: Communication Protocol State Machine... 26 SCOE ............................................................................................ 51 ADXL180 State Machine ........................................................... 26 FDLY ............................................................................................ 51 Phase 1: Power-on-Reset Initialization .................................... 26 ADME .......................................................................................... 51 Phase 2: Device Data Transmission ......................................... 26 STI ................................................................................................ 51 Phase 2: Mode Description ....................................................... 28 FC[1:0] ......................................................................................... 51 Rev. 0 | Page 2 of 56 ADXL180 RG[2:0] .........................................................................................51 SVD ............................................................................................... 53 MD[1:0] ........................................................................................52 CUPAR and CUPRG .................................................................. 53 SYEN .............................................................................................53 Axis of Sensitivity ............................................................................ 54 AZE ...............................................................................................53 Branding ........................................................................................... 55 ERC ...............................................................................................53 Outline Dimensions ........................................................................ 56 DAT ...............................................................................................53 Ordering Guide ........................................................................... 56 REVISION HISTORY 8/08—Revision 0: Initial Version Rev. 0 | Page 3 of 56 ADXL180 SPECIFICATIONS TA = −40°C to +125°C, VBP − VBN = 5.0 V to 14.5 V, fLP = 400 Hz, acceleration = 0 g, unless otherwise noted. Table 1. Parameter 1 SENSOR Scale Factor 50 g Range 8-Bit Data 10-Bit Data 100 g Range 8-Bit Data 10-Bit Data 150 g Range 8-Bit Data 10-Bit Data 200 g Range 8-Bit Data 10-Bit Data 250 g Range 8-Bit Data 10-Bit Data 350 g Range 8-bit Data 10-bit Data 500 g Range 8-Bit Data 10-Bit Data Offset 8-Bit Data 10-Bit Data Noise (Peak-to-Peak) 8-Bit Data 10-Bit Data Self Test Amplitude Internal Self-Test Limit Nonlinearity Cross-Axis Sensitivity Resonant Frequency Q LOW-PASS FILTER Frequency Response Symbol Pass Band −3 dB Frequency −3 dB Frequency −3 dB Frequency −3 dB Frequency AUTO-ZERO Update Rate Slow Mode Fast Mode fLP Min Typ Max Unit Test Conditions/Comments Measurement frequency: 100 Hz See Table 37 0.465 0.116 0.50 0.1250 0.535 0.134 g/LSB g/LSB 0.930 0.233 1.00 0.2500 1.070 0.268 g/LSB g/LSB 1.395 0.349 1.50 0.3750 1.605 0.401 g/LSB g/LSB 1.860 0.465 2.00 0.5000 2.140 0.535 g/LSB g/LSB 2.325 0.581 2.50 0.625 2.675 0.669 g/LSB g/LSB 3.255 0.830 3.50 0.8925 3.745 0.955 g/LSB g/LSB 4.650 1.163 5.00 1.2500 5.350 1.338 g/LSB g/LSB +11 +47 LSB LSB 2 3 LSB LSB 30 30 2 +5 g g % % kHz 880 440 220 110 Hz Hz Hz Hz All ranges, auto-zero disabled −12 −48 2 20 20 25 0.2 −5 12.8 1.5 50 g range 10 Hz to 400 Hz 10 Hz to 400 Hz STI enabled, see Table 35 Of full-scale range Third-order Bessel Programmable, see Table 38 670 335 167.5 83.75 800 400 200 100 5.0 0.5 sec/LSB sec/LSB Rev. 0 | Page 4 of 56 10-bit LSB 10-bit LSB ADXL180 Parameter 1 REGULATOR VOLTAGE MONITOR Regulator Operating Voltage Power-Up Reset Voltage Overvoltage Level Reset Hysteresis Voltage COMMUNICATIONS INTERFACE Quiescent (Idle) Current Modulation Current Signal Current Autodelay Detect Current Data Bit Period 2 Data Bit Duty Cycle Data Bit Rise/Fall Fall Time Rise Time Encoding ADC Conversion Time2 Error Checking (Selectable) Number of CRC Bits Number of Parity Bits Synchronization Pulse Detect No Detect Limit Detect Threshold Threshold Hysteresis Synchronization Pulse Detect Time Synchronization Pulse Discharge (Pull-Down) Time Synchronization Mode Transmission Delay Configuration Mode Receive Communications Interface Detect Threshold Threshold Hysteresis Interbit Time Data 0 Pulse Width Data 1 Pulse Width Configuration Mode Response Time Configuration Mode Write Delay Time VBP During Fuse Programming VBP Current During Fuse Programming Symbol Min Typ Max Unit Test Conditions/Comments VDD VPUR VOV VHYST 3.77 4.7 4.20 4.0 4.95 0.12 4.23 5.3 V V V V See Figure 31 See Figure 31 ILDLE IMOD ISIG IDET tB DDC 5 23 28 18 45 tR tF 400 350 6 25 31 22 8 50 7.7 30 37.7 26 53 mA mA mA mA μs % 1000 1000 ns ns Manchester 35 tADC μs See Figure 8 See Figure 10 x³ + x¹+ x0 Even 3 1 VSPND VSPT ISIG = IIDLE + IMOD Total including IIDLE tB = 8 × tCLK DDC = tA/tB, see Figure 7 See Figure 7 3.0 tSPD 0.1 8 V V V tCLK See Figure 12 tSPP 40 tCLK See Figure 12 tSTD 63 tCLK See Figure 12 3.5 VBP − VBN + VSPT ≤ 14.5 V; see Figure 12 All @ 25°C only; VBP − VBN + VCT ≤ 12.25 V VCT 5.25 See Figure 33 24 V V tCLK tCLK tCLK μs 50 μs See Figure 33 V Compliant up to the maximum operating voltage Maximum drawn by the part 0.1 tIB tPG0 tPG1 tTM1 250 40 80 tTM2 VBPF IFP 55 7.5 15 Rev. 0 | Page 5 of 56 mA See Figure 33 See Figure 33 See Figure 33 See Figure 33 ADXL180 Parameter 1 ASYNCHRONOUS MODE TIMING2 Message Transmission Period Phase 2, Mode 0 All Other Phases and Modes Initialization State (Phase 1) Device Data State (Phase 2) Mode 0 Mode 1 Mode 2 Mode 3 Self-Test State (Phase 3) Self-Test Time 3 Self-Test Interval Self-Test Cycle Auto-Zero Initialization State (Phase 4) SYNCHRONOUS MODE TIMING 4 Message Transmission Period Initialization State1 (Phase 1) Device Data State (Phase 2) Mode 0 Mode 1 Mode 2 Mode 3 Self-Test State (Phase 3) Self-Test Time3 Self-Test Interval Self-Test Cycle Auto-Zero Initialization State (Phase 4) CLOCK Period2 PSRR 5 POWER SUPPLY HOLDUP TIME THERMAL RESISTANCE, JUNCTION TO CASE Symbol Min Typ Max Unit Test Conditions/Comments ADIFX compatible See Figure 26 See Figure 26 See Figure 26 tPM0 tP tI 456 228 100 tDD0 tDD1 tDD2 tDD3 4.10 109 109 117 μs μs ms ms ms ms ms ms tST tSTI tSTC tAZ 394 21.9 65.7 14.94 ms ms ms sec tPS N/A tI 100 tDD0s tDD1s tDD2s tDD3s 9 × tPS 480 × tPS 480 × tPS 512 × tPS ms ms ms ms ms ms tSTS tSTIS tSTCS tAZs 1728 × tPS 96 × tPS 288 × tPS 65,535 × tPS ms ms ms sec tCLK θJC 1.05 1.0 <1 Determined by sync pulse, See Figure 12, minimum tPS = tSPD + tSTD + tM + tB 0.95 500 30 μs LSB ns °C/W 1 fCLK = 1/tCLK 8-bit LSB; test conditions: VBP − VBN = 7.00 V, VAC = 500 mV p-p, 100 kHz to 1.1 MHz @ IBUS = ISIG All parameters are specified using the application circuit shown in Figure 6. CB = 10 nF, CVDD = 100 nF. All timing is driven from the on-chip master clock. 3 tST and tSTS are the times for six self-test cycles. This is the maximum number of cycles in the internal self-test mode. 4 Transmission timing is defined by the internal system clock in asynchronous mode and by the synchronization pulse period in synchronous mode. 2 Rev. 0 | Page 6 of 56 ADXL180 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Parameter Supply Voltage (VBP − VBN) Voltage at Any Pin with Respect to VBN Except VBP Storage Temperature Range Soldering Temperature Operating Temperature Range ESD All Pins Latch-Up Current Mechanical Shock Unpowered Powered Drop Test (onto Concrete)1 Thermal Gradient 1 Rating −0.3 V to +21 V −0.3 V to VDD + 0.3 V −55°C to +150°C 255°C −40°C to +125°C 1.5 kV HBM 100 mA ESD CAUTION ±4000 g (0.5 ms, half sine) ±2000 g (0.5 ms, half sine); −0.3 V to +7.0 V 1.2 m ±20°C/minute Soldered to FR4 coupon printed circuit board (PCB) at the dimensions of 25.4 mm × 25 mm. During test, the PCB is fastened to a support with 46 g mass, equivalent to a typical satellite module PCB. tP tP CRITICAL ZONE tL TO tP TEMPERATURE RAMP-UP tL tL TSMAX TSMIN RAMP-DOWN tS 07544-004 PREHEAT TA = 25°C t = 25°C TO PEAK TIME Figure 2. ADXL180 Pb-Free Solder Profile Table 3. ADXL Solder Profile Parameters Profile Feature Average Ramp-Up Rate (TL to TP) Preheat Temperature Min (TS min) to Temperature Max (TS max) Time (min to max) (tS) TS max to TL Ramp-Up Rate Time Maintained Above Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5°C of Actual Peak Temperature (tP) Ramp-Down Rate Time 25°C to Peak Temperature Small Body Pb-Free Assemblies 3°C/second maximum 150°C to 200°C 60 sec to 180 sec 3°C/second maximum 217°C 60 sec to 150 sec 260°C +5/−5°C 20 sec to 40 sec 6°C/sec maximum 8 minutes maximum Rev. 0 | Page 7 of 56 ADXL180 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCM 16 VSCI NC NC 15 14 13 NC 1 12 VBP VCM DAP1 VCM 2 11 VCM ADXL180 TOP VIEW (Not to Scale) VBN 3 10 VBN VBN DAP2 5 VDD 6 NC 7 VSCO NC = NO CONNECT 9 VBC 8 VBN 07544-002 NC 4 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DAP1 DAP2 Mnemonic NC VCM VBN NC VDD NC VSCO VBN VBC VBN VCM VBP NC NC VSCI VCM VCM VBN Description Reserved for Analog Devices Use Only. VBN or do not connect. Reserved for Analog Devices, Inc., Use Only. Do not connect. Negative Bus Voltage. Reserved for Analog Devices Use Only. VBN or do not connect. Voltage Regulator Bypass Capacitor. Reserved for ADI Use Only. VBN or do not connect. Reserved for ADI Use Only. Do not connect. Negative Bus Voltage. Daisy-Chain Connection. Daisy-chain connection to VBP of the second device or do not connect. Negative Bus Voltage. Reserved for ADI Use Only. Do not connect. Positive Bus Voltage. Reserved for ADI Use Only. VBN or do not connect. Reserved for ADI Use Only. VBN or no connect Analog Signal Chain Input. VBN when not in use. Reserved for ADI Use Only. Do not connect. Exposed Pad: Reserved for ADI Use Only. Do not connect. Exposed Pad: Negative Bus Voltage. Rev. 0 | Page 8 of 56 ADXL180 TERMINOLOGY Full-Scale Range (FSR) The full-scale range of a device, also referred to as the dynamic range, is the maximum and minimum g level that reports on the output following the internal filtering. As a reference, there is usually a trade-off in increased sensitivity and resolution for decreased full-scale range, and vice versa. Noise Device noise is the noise content between 10 Hz and 400 Hz, as noted in the Specifications Table 1. Device noise can be measured by performing an FFT on the digital output and measuring the noise content between the specified frequency limits. Sensitivity The sensitivity of a device is the amount of output change per input change. In this device, it is most usually referred to in units of LSB/g. Scale Factor The scale factor is the amount of input change per output change. In this device, it is most usually referred to in units of g/LSB. Offset Offset is the low frequency component of the output signal that is not due to changes in input acceleration. Slow moving effects, such as temperature changes and self-heating during start up, may affect offset, but the time scale for these effects is beyond that of a typical shock or crash event. Auto-Zero Auto-zero is an offset compensation technique intended to reduce the long term offset drift effects of temperature and aging. This technique is designed to limit interaction with true acceleration signals. For more information, see Figure 30. Rise/Fall Times The device rise time is defined as the amount of time necessary for the Manchester encoded signal (IMOD) to transition from 10% to 90% of its final value (ISIG). Device fall time is the amount of time required for the IMOD signal to fall from 90% of ISIG to within 10% of IIDLE. Idle Current Idle current is the current of the device when at rest, waiting for a synchronization pulse, or in between current modulation. Modulation Current Modulation current is the amount of current that the ADXL180 device pulls from the bus when communicating. For more information, see Figure 7. Phase A phase is a stage in the ADXL180 state machine. For more information, see Figure 20. Mode Mode refers to the selection of the Phase 2 method of device data communication. The ADXL180 is configurable into four unique operating modes. CRC A cyclic redundancy check (CRC) is calculated from a set of data and then transmitted alongside that data. If the calculation technique is defined and known to the receiving device, the receiver can then check whether the CRC bits match the data. If they do not match, a transmission error has occurred. Parity Parity is defined by the count of 1s in a binary string of data. If this count is even, then the data is determined to have even parity. Often a bit is used, such as the CUPAR, in a configuration register that is defined in such a way as to establish a particular parity in the register to detect single bit changes during the life of the device. This is possible because a single bit change changes parity and a monitor circuit can detect this. Similarly, a parity bit can be added in a data transmission to detect single bit errors if the parity of communication is preestablished for the transmit and receive systems. Rev. 0 | Page 9 of 56 ADXL180 THEORY OF OPERATION OVERVIEW The ADXL180 is a complete satellite system, including acceleration sensor, data filtering, digital protocol functionality, and a 2-wire, high-voltage, current-modulated bus interface communications port. ACCELERATION SENSOR The ADXL180 provides a fully differential sensor structure and circuit path. This device uses electrical feedback with zero force feedback. Figure 4 is a simplified view of one of the differential sensor elements. Each sensor includes several differential capacitor unit cells. Each cell is composed of fixed plates attached to the substrate and movable plates attached to the frame. Displacement of the frame changes the differential capacitance, which the onchip circuitry measures. Complementary signals drive the fixed capacitor plates. The relative phasing between the two halves of the differential sensor is such that the displacement signal is differential between the two measurement channels. Using the fully differential sensor and an antiphase clocking scheme helps reject electrical environmental noise (see Figure 5). The ADXL180 acceleration sensor uses two electrically isolated, mechanically coupled sensors to measure acceleration as shown in Figure 5. The clock phasing of the readout is such that the electrical signal due to acceleration is differential between the channels and environmental disturbances couple in as a commonmode signal. The following differential amplifier can then extract the acceleration signal while suppressing the environmental noise. Electrical feedback adjusts the amplitudes of the fixed capacitor plates’ drive signals such that the ac signal on the moving plates is zero. The feedback signal is linearly proportional to the applied acceleration. This feedback technique ensures that there is no net electrostatic force applied to the sensor. ANCHOR MOVABLE FRAME UNIT SENSING CELL UNIT SELF-TEST FORCING CELL MOVING PLATE MOTION FIXED PLATES 07544-024 ACCELERATION PLATE CAPACITORS ANCHOR Figure 4. Simplified View of ADXL180 Sensor Under Acceleration ACCELERATION SENSING AXIS +X-AXIS SENSOR SPRING + EMI DISTURBANCE RESPONSE COMMON TO BOTH CHANNELS 0 + AMP VOUT – ISOLATED MECHANICAL COUPLINGS ACCELERATION RESPONSE DIFFERENTIAL BETWEEN CHANNELS –X-AXIS SENSOR – Figure 5. Differential Acceleration Sensing Rev. 0 | Page 10 of 56 07544-025 0 ADXL180 SIGNAL PROCESSING The ADXL180 contains an on-board set of signal processing blocks both prior to and after ADC conversion. The first stage is a fully differential, switched capacitor, low-pass, three-pole Bessel filter. Range scaling is also handled in one of the filter blocks, enabling 50 g to 500 g range capability. At this point, an analog output test signal (VSCO) is available to the user in a diagnostic mode. The signal then converts by a 10-bit rail-to-rail SAR ADC. In the digital section, an auto-zero routine is available to the user as part of the state machine in addition to error detection features such as offset drift detection. DIGITAL COMMUNICATIONS STATE MACHINE The ADXL180 digital state machine is based on a Core 5 phase state machine implemented in high density CMOS. This state machine handles the sequential states of SYNCHRONOUS OPERATION AND DUAL DEVICE BUS In a point-to-point bus topology, the ADXL180 supports asynchronous transmission of data to the receive device every 228 μs, controlled by the on-board state machine. A synchronous option is also available, allowing two devices to be on the same bus using time division multiplexing where each device transmits its data during a known time slot. Synchronization is achieved by voltage modulated synchronization pulses, configuring the ADXL180 device into a synchronous mode, and establishing data frame time slots. The high voltage communication port registers valid synchronization pulses and enables message-by-message advancement of the state machine rather than asynchronous timed regular data transmission. PROGRAMMED MEMORY AND CONFIGURABILITY Phase 1. Initialization. Phase 2. Device data transmission, including individual serial number and user-programmed data. Phase 3. Self-diagnostic, including automatic full electromechanical self-test with internal error detection available. Phase 4. Auto-zero initialization, if selected. During this phase, acceleration data is already available. Phase 5. Normal acceleration data transmission. Factory-Programmed Serial Number and Manufacturer Information 2-WIRE CURRENT MODULATED INTERFACE User-Programmable Data Register The data that is generated during these five phases is transmitted using a 2-wire high voltage communication port. This allows the device to be powered by a fixed supply voltage, and communicate back to the system or ECU electronics by modulating current. Current modulated messages are encoded using Manchester encoding. The ADXL180 gives the user an 8-bit register of user-programmable data, which is transmitted during Phase 2 of the state machine. In addition, the UD8 bit, a ninth user-available bit, is transmitted separately during Phase 2 and can be used for various purposes, such as orientation definition or module type. The ADXL180 includes a 32-bit factory-programmed serial number, as shown in Table 5. This serial number transmits during Phase 2 of startup for all devices to enable robust quality tracking of individual devices, and it is field readable. In addition, this data includes revision information and manufacturer identification in case multiple devices used within a single application are from different manufacturers or generations of parts. Table 5. Factory Programmed and User-Programmed Memory Configuration Mode Programmed By Register Address User 0000b 0001b 0010b 0011b Factory 1011b 1100b 1101b 1110b 1111b Configuration Mode Register Name UREG CREG0 CREG1 CREG2 SN0 SN1 SN2 SN3 MFGID MSB D7 UD7 UD8 STI CUPRG SNB7 SNB15 SNB23 SNB31 SNPRG D6 UD6 BDE AZE CUPAR SNB6 SNB14 SNB22 SNB30 SNPAR Rev. 0 | Page 11 of 56 D5 UD5 MD1 SYEN SCOE SNB5 SNB13 SNB21 SNB29 REV2 D4 UD4 MD0 ADME FC1 SNB4 SNB12 SNB20 SNB28 REV1 D3 UD3 FDLY ERC FC0 SNB3 SNB11 SNB19 SNB27 REV0 D2 UD2 DLY2 SVD RG2 SNB2 SNB10 SNB18 SNB26 MFGID2 D1 UD1 DLY1 DAT RG1 SNB1 SNB9 SNB17 SNB25 MFGID1 LSB D0 UD0 DLY0 MAN RG0 SNB0 SNB8 SNB16 SNB24 MFGID0 ADXL180 User-Programmed Configuration Application Layer (ISO Layer 7) At each of these previously described points in the system, the ADXL180 is highly configurable for different applications. The organization and configurable items are briefly described in this section but are covered in depth in the remainder of this data sheet. The serial number and configuration data transmission mode and self-test (internal self-test pass/fail discrimination or external self-test data evaluation). Physical Layer (ISO Layer 1) The bus interface hardware definition including the phase of Manchester encoding and synchronization pulse enable/disable. Data Link Layer (ISO Layer 2) The specifics of the data frame format including the data width (8-bit or 10-bit data), state vector (enable/disable), and error detection (parity or CRC). Other signal processing related aspects of the function of the ADXL180 can also be configured as follows: • • • • Rev. 0 | Page 12 of 56 Sensor scale factor (range) Signal chain low-pass filter bandwidth Auto-zero: enable/disable User-defined data in the user data register ADXL180 PHYSICAL INTERFACE APPLICATION CIRCUIT CURRENT MODULATION A typical application circuit is shown in Figure 6. The two capacitors shown in Figure 6 are typically ceramic, X7R, multilayer SMT capacitors. Maximum recommended values of ESR and ESL are 250 mΩ and 2 nH, respectively. Capacitor tolerances of ±10% are recommended. When the ADXL180 device is powered on, it uses current modulation to transmit data. Normally, the device pulls IIDLE current. When modulating, an additional current of IMOD is pulled from the sensor bus. See Figure 7. ADXL180 VBP VBP VDD CB 10nF SUPPLY AND CONFIGURATION BUS CVDD VBN VBN 07544-026 100nF Figure 6. Application Circuit tB tA 90% IMOD 50% 10% TIME tRF Figure 7. Communication Current Modulation Timing Rev. 0 | Page 13 of 56 07544-027 IIDLE ADXL180 Table 6. MAN Options MANCHESTER DATA ENCODING To encode data within the current modulation, the ADXL180 uses Manchester encoding. Manchester encoding works on the principle of transitions representing binary 1s and 0s, as shown in Figure 8. Manchester encoding uses a set of predefined start bits to transmit the clocking within each message, see Figure 9. The pattern of the start bits allows the receiver to synchronize itself to the bit stream. These start bits are user selectable. START BITS LOGIC 1 LOGIC 0 LOGIC 0 LOGIC 1 ISIG 07544-028 BUS CURRENT IIDLE Figure 8. Manchester-1, Start Bits and Phase START BITS LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 1 IIDLE Figure 9. Manchester-2, Bit Coding 1 Manchester Coding Manchester-1 (Default) Manchester-2 Start Bits 1, 0 Logic 0 Falling edge Logic 1 Rising edge 0, 0 Rising edge Falling edge The phase of the Manchester encoded data can be selected via a bit in the configuration registers. See Figure 8 and Figure 9 for details. The configuration bit that sets the phase of the Manchester encoder also sets the value of the two start bits. The start bits are 1, 0 for Manchester-1 and 0, 0 for Manchester-2. For phase and start bit information, see Table 6. OPERATION AT LOW VBP OR LOW VDD The ADXL180 monitors its internal regulator voltage to ensure proper operation. If the bus voltage drops, or the internal regulator voltage drops below the VPUR reset threshold, the device resets. See the Voltage Regulator Monitor Reset Operation section. OPERATION AT HIGH VDD ISIG 07544-029 BUS CURRENT MAN 0 If the regulator pin detects a high voltage, such as from a short or leakage condition, the ADXL180 detects an error. See the Voltage Regulator Monitor Reset Operation section for more details. Rev. 0 | Page 14 of 56 ADXL180 COMMUNICATIONS TIMING AND BUS TOPOLOGIES ASYNCHRONOUS COMMUNICATION tP * ADC SAMPLE tADC tP* IMOD tM** DATA FRAME DATA FRAME 07544-030 LOOP CURRENT tM** IIDLE TIME * tP = tDD DURING PHASE 2, MODE 0 ** tM = tCLK TIMES THE NUMBER OF BITS TRANSMITTED Figure 10. Asynchronous Mode Data Transmission Timing The ADXL180 data transmissions in their default mode run asynchronous to the control module. In this mode, the ADXL180 timing is entirely based on the internal clock of the device. After the initialization phases are complete, the ADXL180 begins to transmit sensor data every 228 μs. The device transmits sensor data until the supply voltage falls below the required minimum operating level. If an internal error is detected, the device transmits the appropriate error code until the supply voltage falls below the required minimum operating level. Configuring the ADXL180 for Synchronous Operation Table 7. Sync Enable (SYEN) Options SYEN 0 1 Asynchronous Single Device Point-to-Point Topology A single device is wired in the point-to-point configuration as shown in Figure 11. This configuration must be used in asynchronous mode. Do not use two asynchronous devices on one bus because communications errors are very likely to occur. CENTER MODULE Definition Synchronization pulse disabled. The device transmits data every 228 μs based on the internal clock of the device. Data is transmitted according to an internal state machine sequence when powered on (default). Synchronization pulse enabled. The device requires a synchronization pulse to sample and transmit data. Data transmission is in accordance with the internal state machine of the device. The user-defined SYEN bit determines whether the device is used in synchronous operation or remains asynchronous. SYEN, as shown in Table 7, must be set to SYEN = 1 to enable synchronous operation. VBP VBN NC VBN VBC DEVICE 1 07544-031 Synchronization Pulse Detection NC Figure 11. Asynchronous Point-To-Point Topology SYNCHRONOUS COMMUNICATION The ADXL180 data transmission can be synchronized to the control module. This synchronization is accomplished by the control module generating a synchronization pulse to the ADXL180. The synchronization pulse is a voltage pulse that is superimposed on the supply voltage by the center module. Figure 12 shows the synchronization pulse timing. Upon detecting a synchronization pulse, the ADXL180 transmits its data. The ADXL180 uses a digital integration method to validate the synchronization pulse. The ADXL180 detects the supply voltage (VBP) rising above the level of VSPT. The state of the level detection circuit controls the count direction of an up-down counter. The counter is clocked every 1 μs. The counter is incremented if the ADXL180 detects a level exceeding VSPT. The counter is decremented if the ADXL180 detects a level below VSPND. Operation is not defined between these thresholds. If the synchronization pulse is fully below VSPND, the pulse is rejected and not detected. The counter saturates at zero. The synchronization pulse is considered valid on the next clock after the counter is incremented to seven counts. The counter is gated off (blanked) after a valid synchronization pulse is detected. Once the sync pulse has been recognized as valid, a command is issued to start the acceleration data analog-to-digital conversion. The ADC does not run continuously in synchronous mode, ensuring that only the acceleration data present at the time of the sync pulse is output from the device. Rev. 0 | Page 15 of 56 ADXL180 The synchronization pulse detector is reenabled after tB, which is an idle bit transmission following the last data frame bit (see the Data Frame Definition section). At this point, the device is ready to receive the next sync pulse. If the application requires or uses a pulse of nonuniform shape, such as, for example, rising above VSPT and subsequently toggling such that it falls below VSPT one or more times before tSPD, consult Analog Devices, Inc., applications support for further information on application specific pulse recognition. Note, this counter means that when an invalid length sync pulse of less than seven counts is followed less than seven counts later by a subsequent sync pulse, detection may occur when the counter is incremented further by less than seven counts by the second pulse. NO DETECT CASE DETECT CASE Bus Discharge Enable Table 8. Bus Discharge Enable BDE 0 1 Definition Bus discharge disabled (default). Bus discharge enabled. Only active when SYEN = 1. The bus discharge enable (BDE) bit in the configuration registers can be set to aid in the discharge of the bus voltage after a synchronization pulse is detected. If the BDE bit is set, the ADXL180 changes the bus current (IBUS) level from IIDLE to ISIG once a valid synchronization pulse has been detected. The control module then sets the voltage on the bus to the nominal operating level. The bus capacitance is discharged by the ADXL180 device. The current level of ISIG acts as an active pull-down current to return the VBP voltage to the nominal supply voltage. The pull-down current pulse can also be used as a handshake with the control module acting as an acknowledgement of the synchronization pulse. tPS VSPT VSPND BUS VOLTAGE SYNCH DETECT/ BLANKING VSPT VSPND VSP tB tSPD … tADC ADC BUSY … ADXL180 RETURN CURRENT tSTD tSPP tM DATA FRAME TIME Figure 12. Synchronization Pulse Timing (Single Device) Rev. 0 | Page 16 of 56 … 07544-012 BUS DISCHARGE CURRENT (IF BDE = 1) ADXL180 Synchronous Single Device Point-to-Point Topology A single device is wired in the point-to-point configuration as shown in Figure 13. The standard use of this configuration is with no delay devices. It is possible to use this topology with fixed delay devices as well, such as if line noise reduction after a sync pulse transmission is desired. VBP VBN NC NC VBN VBC DEVICE 1 07544-031 CENTER MODULE Figure 13. Single Device—Synchronous Communication SYNCHRONOUS COMMUNICATION MODE—DUAL DEVICE ADXL180 devices to share a single pair of wires from the control module for power and communications. This is accomplished using time division multiplexing where each device transmits its data during a known time slot. The time slot used by each device is determined by the delay time from detection of a synchronization pulse to the beginning of data transmission. The data transmission delay time is selectable in the configuration registers. The following discussion uses the convention that the first time slot is named Time Slot A and the second time slot is named Time Slot B (see Figure 14). The two ADXL180 devices can be wired in either a parallel or series mode as described in the following sections. If a synchronization pulse is not detected, no data is sent. This is true for all initialization phases and normal run-time operation. Note that the minimum synchronization pulse period is The ADXL180 can be used in a dual device synchronous communication mode. This mode allows a maximum of two Rev. 0 | Page 17 of 56 tSPD + tDLY + tM + tB ADXL180 VSPT VBP BUS VOLTAGE tB tSPD SYNC DETECT/ BLANKING DEVICE 1 tSTD BUS DISCHARGE CURRENT tSPP tM ADXL180 RETURN CURRENT DEVICE 1 DEVICE 1 DATA FRAME tADC ADC BUSY DEVICE 1 tB SYNC DETECT/ BLANKING DEVICE 2 tDLY tM ADXL180 RETURN CURRENT DEVICE 2 DEVICE 2 DATA FRAME tADC ADC BUSY DEVICE 2 BUS CURRENT TIME SLOT A TIME SLOT B DEVICE 1 DEVICE 2 DATA FRAME DATA FRAME TIME Figure 14. Synchronization Pulse Timing (Dual Device) Rev. 0 | Page 18 of 56 07544-033 tSPP ADXL180 As shown in Table 9, the user can select the data timing of the second device to establish the predefined data slots. This allows for the fastest possible sampling, if required, and Table 9 shows the number of data frame bits the first device may transmit to ensure no overlap. To further reduce device interference from line or system circuit effects, use higher FDLY amounts than the minimum. Table 9. Data Transmission Delay Codes DLY2 0 0 0 0 1 1 1 1 DLY1 0 0 1 1 0 0 1 1 DLY0 0 1 0 1 0 1 0 1 Delay Time (tDLY) 205 μs 213 μs 221 μs 229 μs 237 μs 245 μs 253 μs 261 μs Maximum First Data Frame Bits 11 12 13 14 15 16 17 18 Fixed Delay Mode Fixed delay mode establishes which device transmits in the second time slot. FDLY requires that either (but not both) of the two devices on the bus have the FDLY bit programmed to enable the data frame transmission delay time. The device with the FDLY bit set is named Device 2. Device 2 delays its data transmission by the amount of time programmed into the configuration register via Bit DLY2, Bit DLY1, and Bit DLY0. After receiving a valid synchronization pulse, only Device 1, without the FDLY bit set, sinks ISIG as an active bus pull-down current (if the BDE bit is set) to return the VBP voltage to the nominal supply voltage. Table 10. Fixed Delay Mode FDLY 0 1 Definition Fixed delay mode disabled (default). Fixed delay mode enabled. Device transmits data in the time slot delayed by tDLY as defined by DLY2 to DLY0. Caution: do not set Device 2 using Time Slot B as BDE = 1. Only Device 1 should draw ISIG as an active pull-down when the BDE bit is set. It is good practice to never have BDE = 1 and FDLY = 1 in the same device. The autodelay mode allows two identically configured devices to be wired in a series configuration. The two devices automatically configure the two node network upon power up. The configuration bit (ADME) must be set to enable the autodelay mode. A device with the ADME bit set sinks a bus current of IDET for 6 ms upon power up. The first device in the series configuration (Device 2) detects the presence of the other device in the series (Device 1) by sensing the IDET current passing though itself from Pin VBP to Pin VBC during the first 6 ms of the power-up initialization Phase 1. If the current draw of Device 1 is present, Device 2 delays its data transmission by the amount of time programmed into the configuration register via Bit DLY2, Bit DLY1, and Bit DLY0. Therefore, Device 2 transmits its data during Time Slot B. The data transmission delay time of Device 2 is usually selected based on the number of bits in the data frame. After receiving a valid synchronization pulse, only Device 1 sinks ISIG as an active pull-down current (if the BDE bit is set) to return the VBP voltage to the nominal supply voltage. Device 2 (using Time Slot B) never sinks ISIG as an active pull-down even if the BDE bit is set. In a single device network, the unit that would be called Device 1 is not present. Therefore, the single device detects no current draw through the VBC pin during the power-on initialization. In this case, the single device transmits data during Time Slot A. This allows a device programmed with a nonminimum delay time to be used as either Device 1 or Device 2 in a series configuration or as a single device. The autodelay mode detect function samples the state of the autodelay detect sense circuit every 500 μs during the first 6 ms of Phase 1. A total of four consecutive samples must be valid to place the device in the autodelay mode. Caution: do not send an additional valid sync pulse during the blanking period, tSTD or tB, for either device, because it incurs the risk of the signal being misinterpreted and a change in message response timing. Dual Device Synchronous Parallel Topology The two devices are wired in a parallel configuration as shown in Figure 15. This configuration must be run in the fixed delay mode. Autodelay Mode 1 VBP VBN NC NC VBN VBC DEVICE 1 Table 11. Autodelay Mode Enable (ADME) Options ADME 0 CENTER MODULE Definition Autodelay mode is disabled. The part does not check for a second device on the line and does not pull any extra current during startup (default). Autodelay mode detection is enabled. Pull down IDET for 6 ms at power up. Rev. 0 | Page 19 of 56 VBP VBN NC NC VBN VBC DEVICE 2 Figure 15. Dual Device—Parallel Configuration 07544-034 Configuring Synchronous Operation Delay Selection ADXL180 The two devices are wired in a series configuration as shown in Figure 16. The series configuration can be configured to run in either of two modes: fixed delay or autodelay. These modes are configured using the FDLY and ADME bits in the configuration registers. Rev. 0 | Page 20 of 56 CENTER MODULE VBP VBN VBN DEVICE 1 VBC VBP VBN NC NC VBN VBC DEVICE 2 Figure 16. Dual Device—Series Configuration 07544-035 Dual Device Synchronous Series Topology ADXL180 DATA FRAME DEFINITION DATA FRAME TRANSMISSION FORMAT tM DATA BITS START START BIT 0 BIT 1 LOOP CURRENT 0 IMOD IIDLE tB LOGIC SIGNAL AT CONTROL MODULE DECODER DATA BITS START START BIT 0 BIT 1 ‘1’ ‘0’ 0 07544-036 TIME Figure 17. Data Message Timing (Manchester-1, Bit Coding) A data frame starts with two start bits. The value of these two bits is determined by the Manchester encoding mode select bit. See the Manchester Data Encoding section. Figure 17 shows the basic format and timing of the data frame. A 1-bit idle time is an implicit stop bit at the end of a data frame. • • • DATA FRAME CONFIGURATION OPTIONS Figure 18 diagrams the protocol data frame construction options. The data frame can be broken into four specific fields as follows: • Start bits—two start bits are always transmitted at the start of the data frame. These bits are used to synchronize the center module decoder with the Manchester encoded signal. Error checking—a single parity bit or a 3-bit CRC code can be selected. State vector—identifies the type of data in the data field. It can be disabled. When it is disabled, it is not transmitted. Data—the device data and sensor data can be transmitted in either 8-bit or 10-bit mode. Depending on the settings of the configuration register bits (ERC, SVD, and DAT), the data frame can be from 11 bits to 18 bits in length. Figure 18 shows the formats of the available data frames. Note that the error checking field is transmitted first when the CRC is selected but transmitted last when parity is selected. See Figure 18 for specific examples of full protocol configurations. Rev. 0 | Page 21 of 56 ADXL180 CREG BIT NAME SVD TRANSMITTED FIRST DAT START BITS 0 0 0 0 1 0 START BITS 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 0 0 1 0 0 1 0 1 1 1 0 0 1 2 1 1 0 1 0 1 1 0 1 0 1 1 2 3 0 1 2 1 2 0 1 2 3 4 1 6 7 7 8 9 4 5 6 5 6 7 8 9 5 6 7 8-BIT DATA 2 0 1 2 3 2 2 4 10-BIT DATA 0 1 2 3 4 5 P 6 2 2 7 8-BIT DATA 0 1 2 3 4 3 4 5 3 4 6 6 Figure 18. Data Frame Formats Rev. 0 | Page 22 of 56 9 0 P 5 7 8 P 5 8 6 7 0 P 8-BIT DATA 0 5 3 10-BIT DATA 0 4 8-BIT DATA 2 STATE VECTOR 0 1 10-BIT DATA START BITS 1 2 STATE VECTOR START BITS 1 1 STATE VECTOR START BITS 1 0 CRC START BITS 1 2 10-BIT DATA CRC START BITS 0 1 CRC START BITS 0 STATE VECTOR CRC 7 0 9 0 07544-037 ERC ADXL180 ACCELERATION DATA CODING Table 14. 8-Bit Full Sensor Data Range Coding 01 1111 1111 01 1111 1110 SENSOR CODE 01 1111 1101 01 1111 1100 00 0000 0001 00 0000 0000 11 1111 1111 11 1111 1110 10 0000 0010 10 0000 0000 –FS 0 07544-038 10 0000 0001 +FS ACCELERATION INPUT Decimal +127 Hex 0x7F Binary (Twos Complement) 0111 1111 +126 +125 … +1 0 −1 … −126 −127 −128 0x7E 0x7D … 0x01 0x00 0xFF … 0x82 0x81 0x80 0111 1110 0111 1101 … 0000 0001 0000 0000 1111 1111 … 1000 0010 1000 0001 1000 0000 Table 15. 10-Bit Full Sensor Data Range Coding Decimal +511 Hex 0x1FF Binary (Twos Complement) 01 1111 1111 +510 +509 … +1 0 −1 … −510 −511 −512 0x1FE 0x1FD … 0x01 0x00 0x3FF … 0x202 0x201 0x200 01 1111 1110 01 1111 1101 … 00 0000 0001 00 0000 0000 11 1111 1111 … 10 0000 0010 10 0000 0001 10 0000 0000 Figure 19. 10-Bit ADC Transfer Characteristic Table 12. DAT Data Bit Options DAT 0 1 Definition 10-bit data sensor data transmitted. 8-bit Phase 2 configuration data left justified in 10-bit data frame (default). 8-bit sensor data transmitted. The sensor data coding is dependent on the configuration register bit settings. Either 8-bit or 10-bit sensor data can be transmitted. This 8-bit or 10-bit data range is either full range or reduced range. Whether the data range is full or reduced depends on the setting of the state vector disable and auto-zero enable configuration register bits. For more information, see Table 13. Table 13. Full and Reduced Sensor and Device Data Ranges SVD1 0 0 1 1 1 AZE2 0 1 0 1 Data Range Full Reduced Reduced3 Reduced3 SVD is the state vector disable configuration bit. AZE is the auto-zero enable configuration bit. 3 A configuration error is reported if Phase 2 Mode 0 is selected with the state vector disabled (SVD = 1). The ADXL180 transmits a configuration error code during run time and no sensor data is transmitted. Description Most positive (+FS) acceleration value … … … … Zero (0) acceleration value … … … … Most negative (−FS) acceleration value Description Most positive (+FS) acceleration value … … … … Zero (0) acceleration value … … … … Most negative (−FS) acceleration value Table 16. 8-Bit Reduced Sensor Data Range Coding Decimal +116 Hex 0x74 Binary (Twos Complement) 0111 0100 … 0 … 0x00 … 0000 0000 … −116 … 0x8C … 1000 1100 2 Description Most positive (+FS) acceleration value … Zero (0) acceleration value … Most negative (−FS) acceleration value Table 17. 10-Bit Reduced Sensor Data Range Coding Decimal +464 Hex 0x1D0 Binary (Twos Complement) 01 1101 0000 … 0 … −464 … 0x000 … 0x230 … 00 0000 0000 … 10 0011 0000 Rev. 0 | Page 23 of 56 Description Most positive (+FS) acceleration value … Zero (0) acceleration value … Most negative (−FS) acceleration value ADXL180 STATE VECTOR CODING Table 18. SVD Data Bit Options SVD 0 1 Definition State vector is enabled (default). State vector is disabled, a reduced data range is used. The 3-bit state vector field contains a code that defines the meaning of the data contained in the 8- or 10-bit data field. These definitions are listed in Table 19. When selected, the 3-bit state vector is appended to the 8- or 10-bit data field and transmitted as part of the data frame. STATE VECTOR DESCRIPTIONS Table 19. State Vector Table SV2 0 SV1 0 SV0 0 State Normal operation Phase 1 5 Data In Frame Sensor data 0 0 1 Device data 2 Serial number/manufacturer ID/range/user and configuration register data 0 1 0 Self Test 0 3 0 1 1 Self Test 1 3 1 0 0 4 1 0 1 Auto-zero initialization OTP memory data Sensor data with the self-test signal unasserted Sensor data with the self-test signal asserted Sensor data NA OTP memory data (configuration mode data) 1 1 0 Status/error NA Status/error data (see Table 39) 1 1 1 Reserved NA Reserved 1 NA is not applicable. Rev. 0 | Page 24 of 56 Description This is the running state of the ADXL180. During this state, an analog-to-digital conversion is performed, and the resulting sensor data is transmitted every 228 μs in asynchronous mode or every 250 μs in synchronous mode. The data field contains serial number and/or configuration data. See the ADXL180 State Machine section for the device data transmission specifics for each MD1 to MD0 selection. The ADXL180 is in sensor self-test mode. The internal sensor self-test signal is unasserted. The ADXL180 is in sensor self-test mode. The internal sensor self-test signal is asserted. The ADXL180 is in Phase 4. The auto-zero function is running in the fast initialization mode. This state vector indicates that the data sent is from the OTP memory of the ADXL180. This data type is only sent when the device is in configuration mode. This state is set when an internal error is detected by the ADXL180. The data field contains the error type. See the Error Detection section for details. ADXL180 There are two error checking methods available: a 3-bit CRC and a 1-bit parity check. These are determined by the userselected Bit ERC. calculation is performed from MSB to LSB on the entire data frame. The CRC state registers are initialized to zero. Therefore, when checking the result of the transmission, the final CRC check state should be zero. The three CRC bits are always the three least significant bits in the transmission. Table 20. Error Check (ERC) Bit Options Parity Encoding TRANSMISSION ERROR DETECTION OPTIONS ERC 0 1 Definition A 3-bit CRC is included in the message. CRC is calculated using the polynomial x3 + x1 + x0. (Default.) One parity bit is included in the message. CRC is not used. It is a bit that is set such that even parity is achieved in the transmitted message. The ADXL180 can be programmed so that the LSB of each data transmission contains a 1-bit parity check bit. The 1-bit parity check is even parity. The parity algorithm sets the parity bit to be either a one or a zero; thus, the resulting number of ones transmitted in the data frame is always an even number. CRC Encoding The ADXL180 can be programmed to utilize a 3-bit CRC. The polynomial used for the encoding is x3 + x1 + x0. The CRC Rev. 0 | Page 25 of 56 ADXL180 APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE Table 21. ADXL180 Start-Up Sequence Summary Name Function Data Type Transmitted Phase 1 Initialization Power-on reset None Phase 2 Device Data None Serial number, configuration and range Phase 3 Self-Test Sequence self-test pattern Sensor, range, device OK or delimiter Phase 4 Auto-Zero Initialization Fast auto-zero Sensor Phase 5 Run Time Slow autozero Sensor ADXL180 STATE MACHINE PHASE 1: POWER-ON-RESET INITIALIZATION After power is applied and stabilized, the ADXL180 follows a five-phase start-up sequence. The basic function of each phase is fixed as shown in Figure 20. The five phases and the function modes available in each phase are detailed in the following sections. The power-on-reset initialization period is typically 100 ms long. It is the period of time from when the internal reset signal is deasserted until the beginning of Phase 2. This time allows for circuit stabilization and entry into configuration mode. No data is transmitted during Phase 1. No errors are reported during Phase 1. Additionally, until phase 1 is exited, the device does not respond to a transmitted sync pulse (see Table 21). RESET PHASE 2: DEVICE DATA TRANSMISSION VDD > VPUR RESET RESET Overview PHASE 1 INITIALIZATION The device data consists of the serial number and configuration data. Device data is transmitted during Phase 2. This data can be transmitted in one of four configurable modes (see Table 22). These modes are described in detail in the following sections. The parity of all OTP memory blocks is continuously monitored (provided that the block has been programmed) beginning at the end of Phase 2. See the Parity Encoding section for more details. PHASE 2 DEVICE DATA ERROR RESET PHASE 3 SELF-TEST Table 22. MD Phase 2 Device Data Mode Select Codes ERROR RESET PHASE 4 AUTO-ZERO INITIALIZATION ERROR ERROR ERROR STATE TRANSMIT ERROR CODE Name Mode 0 Mode 1 1 1 0 1 Mode 2 Mode 3 Definition ADIFX mode device data (default) Range data only (range selection limited) 8-bit coded device data 10-bit coded device data During Phase 2, if Mode 0, Mode 1, or Mode 2 is selected, the device data is 8-bit data. If the 10-bit data mode is selected in combination with Phase 2 Mode 0, Mode 1, or Mode 2, the 8-bit device data is left justified in the 10-bit data field. The two LSBs are held at zero (see Table 24). PHASE 5 NORMAL OPERATION RESET MD0 0 1 07544-039 RESET MD1 0 0 Figure 20. ADXL180 Start-Up Sequence Rev. 0 | Page 26 of 56 ADXL180 Influence of MD On Data Range Table 23. MD Settings and Device Data Ranges Mode (Device Data) 0: ADIFX3 (All Configuration Data, Serial Number, and Manufacturer ID) 1: Range Data Only3 (Limited Range Selection) 2: 8-Bit Coded Device Data3 (UD[7:0], Serial Number, and Range) 3: 10-Bit Coded Device Data4 (UD[7:0], Serial Number, and Range) MD1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SVD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MD0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AZE2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Range Full Reduced Configuration error Configuration error Full Reduced Reduced Reduced Full Reduced Reduced Reduced Full Reduced Reduced Reduced 1 SVD is the state vector disable configuration bit. AZE is the auto-zero enable configuration bit If Phase 2 Mode 0, Mode 1, or Mode 2 is selected, the device data is 8-bit data. If the 10-bit data mode is selected in combination with Phase 2 Mode 0, Mode 1, or Mode 2, the 8-bit device data is left justified in the 10-bit data field. The two LSBs are held at zero (see Table 24). 4 The 10-bit device data mode (Phase 2 Mode 3) is incompatible with the 8-bit data mode (the DAT bit is set to 1). The device transmits a configuration error code if Phase 2 Mode 3 is selected and the DAT bit is set to 1. No sensor data is transmitted. 2 3 Device Data Mapping in Phase 2 Table 24. Phase 2 Device Data Bit Mapping in 10-Bit Sensor Data Mode DB9 Device Data MSB DB8 Device Data DB7 Device Data DB6 Device Data DB5 Device Data DB4 Device Data DB3 Device Data DB2 Device Data LSB DB1 0 DB0 0 Table 25. Phase 2 Device Data Bit Mapping in 8-Bit Sensor Data Mode DB7 Device Data MSB DB6 Device Data DB5 Device Data DB4 Device Data DB3 Device Data Rev. 0 | Page 27 of 56 DB2 Device Data DB1 Device Data DB0 Device Data LSB ADXL180 PHASE 2: MODE DESCRIPTION Asynchronous Mode Mode 0 The device data is transmitted at a time interval of 456 μs based on the internal clock of the ADXL180. The 456 μs period is twice the normal transmission time interval of 228 μs. The Mode 0 option for Phase 2 transmits the entire contents of the configuration registers, the serial number and the manufacturer ID byte. The total number of messages transmitted during Phase 2, Mode 0 is 9. Synchronous Mode In synchronous mode, the device data is transmitted in response to the synchronization pulse generated by the control module. See the Synchronization Pulse Detection section. PHASE 1 TRANSMIT SN0 BYTE tP TRANSMIT SN1 BYTE tP TRANSMIT SN2 BYTE tP TRANSMIT SN3 BYTE PHASE 2 MODE 0 tP 9 × tP TRANSMIT MANUFACTURER ID BYTE tP TRANSMIT UREG BYTE tP TRANSMIT CREG0 BYTE tP TRANSMIT CREG1 BYTE tP 07544-040 TRANSMIT CREG2 BYTE tP PHASE 3 Figure 21. Phase 2 Mode 0 State Machine Table 26. Mode 0 Serial Number and Configuration Data Byte Sequence Byte 8 CREG2 Byte 7 CREG1 Byte 6 CREG0 Byte 5 UREG Byte 4 Manufacturer ID Byte 3 SN3 Byte 2 SN2 Byte 1 SN1 Table 27. Mode 0 Manufacturer ID Byte MSB SNPRG SNPAR REV2 REV1 REV0 MFGID2 Rev. 0 | Page 28 of 56 MFGID1 LSB MFGID0 Byte 0 SN0 ADXL180 Table 28. Mode 0 Manufacturer ID Byte Codes Manufacturer ID Byte Field MFGID2|MFGID2|MGFID0 Code (Binary) 101b REV2|REV1|REV0 000b Comments Analog Devices identification code Die revision code Mode 1 When Phase 2 Mode 1 is selected, only the range data is transmitted during Phase 2. The total number of messages transmitted during Phase 2 Mode 1 is 480. PHASE 1 480 × tP TRANSMIT RANGE BYTE PHASE 2 MODE 1 07544-041 479 A configuration error is flagged when Phase 2 Mode 1 is selected with a range code selection that sets a range other than one of the ranges listed in Table 29. In this case, the error state is entered immediately instead of entering Phase 1. See Table 39 for the error coding. When both Phase 2 Mode 1 and the 10-bit data mode are selected, all range data is transmitted with two zero value LSBs appended (that is, left-justified data), as shown in Table 24. Note that, when Mode 1 is selected with the state vector enabled and auto-zero is not enabled, the full range sensor data coding is used (see the Data Frame Transmission Format section). Therefore, the positive and negative full-scale ends of the sensor data range overlap with the range and error codes. The state vector distinguishes between the types of transmitted data. The state vector identifies the range data as device data (state vector = 001b) and error codes as status/error data (state vector = 110b). Normal operation sensor data has a state vector of 000b (see Table 19 for details). PHASE 3 Figure 22. Phase 2 Mode 1 State Machine Table 29. Phase 2 Mode 1 Range Data Coding 8-Bit Data Decimal Hex −122 0x86 −125 0x83 −128 0x80 10-Bit Data Decimal Hex −488 0x218 −500 0x20C −512 0x200 State Vector Code 001b 001b 001b Rev. 0 | Page 29 of 56 Description ±250 g measurement range ±50 g measurement range ±100 g measurement range ADXL180 Mode 2 Device Data When Mode 2 is selected, the device data that is transmitted consists of the UREG byte, four configuration register bytes (see Figure 24), and the 4-byte serial number. The data is transmitted one bit per message. Each message represents either a Logic 0 or a Logic 1. The code, 0x7A (+122d), represents a Logic 0 and the code, 0x79 (+121d), represents a Logic 1 in 8-bit data mode. See Table 30 for both 8-bit and 10-bit data coding. The delimiter code depends on the range setting in the configuration registers. The delimiter byte used for each range setting is listed in Table 31. The data is transmitted in the following sequence and as shown in Figure 23. The total number of messages transmitted during Mode 2 Phase 2 is 480. 3. 4. 5. Transmit delimiter code 64 times. Transmit 32 messages of serial number data (32 bits of information, one bit per message). Transmit 12 messages of user bits (12 bits of information, one bit per message). See Table 32. Transmit delimiter code eight times. Repeat Step 2 through Step 4 seven times. PHASE 1 PHASE 2 MODE 2 TRANSMIT DELIMITER CODE 63 TRANSMIT SN DATA BIT CODE 31 480 × tP TRANSMIT USER DATA BIT CODE User Bits and User Register (UREG) 11 The user bits (U11 to U0) information transmitted during Phase 2 Mode 2 maps into the user and configuration register data stored in the OTP memory of the ADXL180. This includes the 8-bits in the UREG. The mapping is shown in Table 32. See the Configuration Specification section for information about the definition and function of the user and configuration registers data bits. TRANSMIT DELIMITER CODE 7 7 PHASE 3 10-Bit Data and Mode 2 Figure 23. Phase 2 Mode 2 State Machine During Phase 2 when both Mode 2 and the 10-bit data mode are selected, all device data messages are transmitted with two zero-value LSBs appended (that is, left-justified data). Note that, when Mode 2 is selected with the state vector enabled and the auto-zero is not enabled, the full range sensor data coding is Rev. 0 | Page 30 of 56 07544-044 1. 2. used (see the Data Frame Transmission Format section). Therefore, the positive and negative full-scale ends of the sensor data range overlap with the device data and status/error codes. The state vector distinguishes between the types of transmitted data. The state vector identifies the device data (state vector = 001b) and the status/error codes (state vector = 110b). Normal operation sensor data has a state vector of 000b. See Table 19 and Table 16. ADXL180 PHASE 1 SERIAL NUMBER/ USER DATA SERIAL NUMBER/ USER DATA SERIAL NUMBER/ USER DATA SERIAL NUMBER/ USER DATA PHASE 3 SERIAL NUMBER/ USER DATA SERIAL NUMBER/ USER DATA SERIAL NUMBER/ USER DATA DELIMITER SERIAL NUMBER/ USER DATA PHASE 2 ST DATA/ STATUS SN00 SN01 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DELIM DELIM DELIM DELIM DELIM DELIM DELIM 45 46 47 48 49 50 51 52 Figure 24. Phase 2 Mode 2 Device Data Transmission Table 30. Phase 2 Mode 2 Sensor and Device Data Coding 8-Bit Data Decimal Hex +127 0x7F +126 0x7E +125 0x7D +124 0x7C +123 0x7B +122 0x7A +121 0x79 +120 0x78 +119 0x77 +118 0x76 +117 0x75 +116 0x74 +115 0x73 … … 0 0x00 … … −115 0x8D −116 0x8C −117 0x8B −118 0x8A −119 0x89 −120 0x88 −121 0x87 −122 0x86 −123 0x85 −124 0x84 −125 0x83 10-Bit Data Decimal Hex +508 0x1FC +504 0x1F8 +500 0x1F4 +496 0x1F0 +492 0x1EC +488 0x1E8 +484 0x1E4 +480 0x1E0 +476 0x1DC +472 0x1D8 +468 0x1D4 +464 0x1D0 +460 0x1CC … … 0 0x 000 … … −460 0x234 −464 0x230 −468 0x22C −472 0x228 −476 0x224 −480 0x220 −484 0x21C −488 0x218 −492 0x214 −496 0x210 −500 0x20C Data Type Undefined Undefined Error code Undefined Undefined Logic 0 Logic 1 Undefined Undefined Undefined Undefined Acceleration data Acceleration data … Acceleration data … Acceleration data Acceleration data Undefined Undefined Undefined Undefined Undefined Status code Undefined Undefined Status code Rev. 0 | Page 31 of 56 Description Unused Unused Device error Unused Device OK Device data : Logic 0 Device data : Logic 1 Unused Unused Unused Unused Most positive (+FS) acceleration value Zero (0) acceleration value Most negative (−FS) acceleration value Unused Unused Unused Unused Unused ±250 g measurement range Unused Unused ±50 g measurement range 07544-045 33 34 35 36 37 38 39 40 41 42 43 44 DELIM U00 U01 U02 DELIMITER U03 U04 SN02 8 U05 SN03 7 U06 SN04 6 U07 SN05 5 U08 SN06 4 U09 SN07 3 U10 SN08 2 U11 SN09 1 USER BITS SN10 SN11 SN12 SN13 SN14 SN23 SN15 SN24 SN16 SN25 SN17 SN26 SN18 SN27 SN19 SN28 SN20 SN29 SN21 SN30 SN22 SN31 SERIAL NUMBER ADXL180 8-Bit Data Decimal Hex −126 0x82 −127 0x81 −128 0x80 10-Bit Data Decimal Hex −504 0x208 −508 0x204 −512 0x200 Data Type Undefined Undefined Status code Description Unused Unused ±100 g measurement range Table 31. Phase 2 Mode 2 Delimiter Coding Range 50 g 100 g 150 g 200 g 250 g 350 g 500 g State Vector Code 001b 001b 001b 001b 001b 001b 001b Decimal −125 −128 −125 −125 −122 −125 −125 8-Bit Data Hex 0x83 0x80 0x83 0x83 0x86 0x83 0x83 Rev. 0 | Page 32 of 56 Decimal −500 −512 −500 −500 −488 −500 −500 10-Bit Data Hex 0x20C 0x200 0x20C 0x20C 0x218 0x20C 0x20C ADXL180 32 times for each nybble number. The specific meaning of each data nybble is defined in Table 33. The total number of messages transmitted during Phase 2 in Mode 3 is (32 × 16) = 512. Table 32. Phase 2 Mode 2 User Bit Mapping Device Data Bit Name SYEN RG2 RG1 RG0 UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 User Register (UREG) The User Register UREG[7:0], in Mode 3 transmit during Nybble 7 (UREG[7:4]) and Nybble 8 (UREG[3:0]). Use with State Vector Enabled When Mode 3 is selected with the state vector enabled and the auto-zero not enabled, the full range sensor data coding is used (see the Data Frame Transmission Format section). Therefore, the positive and negative full-scale ends of the sensor data range overlap with the device data and status data codes. The state vector distinguishes between the types of transmitted data. The state vector identifies the device data (state vector = 001b) and status codes as status/error data (state vector = 110b). Normal operation sensor data has a state vector of 000b (see Table 19). Mode 3 Device Data In Phase 2 Mode 3, the 10-bit data codes, −512 (0x200) to −481 (0x21F), are used to transmit the device data. The data coding is shown in Table 34 and in Figure 25. One 4-bit nybble of the device data (encoded as one of 16 nybble codes) is transmitted in each 10-bit message. The number of the data nybble is identified by the preceding nybble number (NN) code as detailed in Table 33. This allows a total of (16 × 4) = 64 unique bits of device data to be transmitted during Phase 2. Each message is repeated PHASE 1 NN1 DATA1 Illegal Configuration: Mode 3 and 8-Bit Data A configuration error is flagged if Phase 2 Mode 3 is selected and the configuration register is programmed to select the 8-bit data mode. In this case, the error state is entered immediately instead of Phase 1. See the Error Detection section for more information. PHASE 2 NN1 DATA1 NN2 DATA2 PHASE 3 NN2 DATA2 NN16 NN16 DATA 16 32 MESSAGES 32 MESSAGES 32 MESSAGES DATA 16 07544-046 User Bit U11 U10 U09 U08 U07 U06 U05 U04 U03 U02 U01 U00 Figure 25. Mode 3 Device Data Transmission Table 33. Phase 2 Mode 3 Device Data Mapping Device Data Nybble No. 11 2 3 4 5 Protocol ID Number of nybbles sent Manufacturer Sensor type Sensor range2 Definition 6 BDE and RS 7 8 9 10 User data (UD Bits[7:4]) User data (UD Bits[3:0]) Serial number (Bits[31:28]) Serial number (Bits[27:24]) 16 Analog Devices Accelerometer 100 g 50 g 200 g Other RS = 0, BDE = 0 RS = 0, BDE = 1 RS = 1, BDE = 0 RS = 1, BDE = 1 0 to 255 0 to 255 Rev. 0 | Page 33 of 56 Binary Code 001 10000 101 00001 0000 0001 0010 0011 0000 0001 0010 0011 XXXX3 XXXX XXXX XXXX Nybble Sent 0011 0000 1010 0001 0000 0001 0010 0011 0000 0001 0010 0011 XXXX XXXX XXXX XXXX ADXL180 Device Data Nybble No. 11 12 13 14 15 16 Definition Serial number (Bits[23:20]) Serial number (Bits[19:16]) Serial number (Bits[15:12]) Serial number (Bits[11:8]) Serial number (Bits[7:4]) Serial number (Bits[3:0]) Binary Code XXXX XXXX XXXX XXXX XXXX XXXX 1 Nybble Sent XXXX XXXX XXXX XXXX XXXX XXXX Data Nybble 1 is transmitted first. If the configuration register settings have configured the ADXL180 for a range other than 50 g, 100 g, or 200 g, the other code (0011b) is sent. In these cases, the UD bits can be used to indicate the actual range. 3 X indicates that the data is device dependent. 2 Table 34. Phase 2 Mode 3 Sensor and Device Data Coding Decimal 511 … 501 500 499 … 488 487 486 … 465 464 … 0 … −464 −465 … −480 −481 −482 −483 −484 −485 −486 −487 −488 −489 −490 −491 −492 −493 −494 −495 −496 Hex 0x1FF … 0x1F5 0x1F4 0x1F3 … 0x1E8 0x1E7 0x1E6 … 0x1D1 0x1D0 … 0x000 … 0x230 0x22F … 0x220 0x21F 0x21E 0x21D 0x21C 0x21B 0x21A 0x219 0x218 0x217 0x216 0x215 0x214 0x213 0x212 0x211 0x210 Data Type Undefined Undefined Undefined Status Undefined Undefined Undefined Status Undefined Undefined Undefined Acceleration Data Acceleration Data Acceleration Data Acceleration Data Acceleration Data Undefined Undefined Undefined Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Data Nybble Description Unused Unused Unused Device Error Unused Unused Unused Device OK Unused Unused Unused Most positive (+FS) acceleration value … Zero (0) acceleration value … Most negative (−FS) acceleration value Unused Unused Unused Device Data 1111 Device Data 1110 Device Data 1101 Device Data 1100 Device Data 1011 Device Data 1010 Device Data 1001 Device Data 1000 Device Data 0111 Device Data 0110 Device Data 0101 Device Data 0100 Device Data 0011 Device Data 0010 Device Data 0001 Device Data 0000 Rev. 0 | Page 34 of 56 ADXL180 Decimal −497 −498 −499 −500 −501 −502 −503 −504 −505 −506 −507 −508 −509 −510 −511 −512 Hex 0x20F 0x20E 0x20D 0x20C 0x20B 0x20A 0x209 0x208 0x207 0x206 0x205 0x204 0x203 0x202 0x201 0x00 Data Type Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Nybble Number Description Device Data Nybble 16 Device Data Nybble 15 Device Data Nybble 14 Device Data Nybble 13 Device Data Nybble 12 Device Data Nybble 11 Device Data Nybble 10 Device Data Nybble 9 Device Data Nybble 8 Device Data Nybble 7 Device Data Nybble 6 Device Data Nybble 5 Device Data Nybble 4 Device Data Nybble 3 Device Data Nybble 2 Device Data Nybble 1 PHASE 3: SELF-TEST DIAGNOSTIC The ADXL180 has two self-test modes, internal and external. In both modes the ADXL180 applies an internally generated electrostatic force to the sensor, simulating an acceleration force. This force causes the sensor proof-mass to displace. This displacement is transduced by the sensor interface electronics and passed through the signal chain to the ADC. When in external self-test mode, the ADXL180 transmits sensor data while activating the self-test signal several times. When in internal self-test mode, the ADXL180 transmits data dependent on the setting of the Phase 2 Mode select bits. While doing so, the ADXL180 activates the self-test signal several times. It then examines the results and either continues the start-up initialization sequence or reports an error. The detailed operation of the two self-test modes is described in the following sections. Concept of Self-Test The fixed plates in the forcing cells are normally kept at the same potential as that of the movable frame. When self-test is activated, the voltage between the fixed plates and the moving plates in the forcing cells is changed. This creates an attractive electrostatic force, which causes the frame to move toward one set of fixed plates. The entire signal channel is active; therefore, the sensor displacement causes a signal change at the output of the ADC. Internal and External Self-Test Option There are two selectable modes of operation for self-test. The self-test modes are internal and external. The self-test mode is toggled by selecting or deselecting the STI configuration bit, as shown in Table 35. Table 35. Self Test Internal (STI) Options STI 0 1 Definition External self-test. User must monitor self-test data to verify proper operation. Device does not monitor its own response to the self-test stimulus. (Default.) Internal self-test. The device internally monitors self-test data to determine proper operation. External Self-Test The external self-test mode applies an electrostatic force to the sensor (simulating an acceleration force) and transmits the sensor data to the control module. This allows the control module to measure the subsequent change in the sensor output value. The signal path low-pass filter of the ADXL180 has a slower response time than the rise time of the internal self-test control (STC) signal. Therefore, the sensor data transmitted during the external self-test sequence follows the rise and fall times of the low pass filter in response to the internal STC signal. The state vector (if enabled) provides the relative timing information indicating when the internal STC signal is applied to the sensor. The STC signal activates six times during the self-test state of the ADXL180 (see Figure 26). During external self-test, an average of the zero self-test value is computed and subsequently used to provide an initial offset correction value for the autozero function. See the Phase 4: Auto-Zero Initialization section for more information. Rev. 0 | Page 35 of 56 ADXL180 PHASE 3 PHASE 4 tST LOOP I MOD CURRENT IIDLE tSTC tSTI tSTI tSTI tSTI 07544-047 STC TIME Figure 26. External Self-Test Control Timing c. Internal Self-Test The internal mode self-test applies an electrostatic force to the sensor (simulating an acceleration force) and measures the change in the sensor output value. A self-test cycle (tSTC) constitutes one activation and deactivation of the self-test force. A self-test cycle is considered passed if the change in the sensor output value falls within the expected minimum and maximum self-test response levels. The internal self-test (Phase 3) is exited and Phase 4 is entered upon completing the second of any two successful self-test cycles. A self-test cycle is considered failed if the change in the sensor output value is not within the expected levels. The self-test cycle is then repeated. The self-test cycle is run a maximum of six times. The internal self-test (Phase 3) is exited and the error state entered if fewer than two of the six self-test cycles pass. Once the error state is entered, the self-test error code is transmitted until the device is reset. The internal self-test sequence is as follows: 1. Wait 32 consecutive ADC samples. 2. Average 64 consecutive ADC samples (VSTZ1). 3. Enable self-test voltage. 4. Wait 32 consecutive ADC samples. 5. Average 64 consecutive ADC samples (VSTP). 6. Disable self-test voltage. 7. Wait 32 consecutive ADC samples. 8. Average 64 consecutive ADC samples (VSTZ2). 9. Compare measured values. a. Compare (VSTZ1) to specified minimum and maximum offset tolerance. b. Compare (VSTZ2) to specified minimum and maximum offset tolerance. Calculate difference (VSTP) − (VSTZ1) and compare to specified minimum and maximum difference. d. Calculate the absolute difference (VSTZ1) − (VSTZ2) and compare to the maximum value. e. If delta is less than or equal to four counts (10 bits), then the self-test is a pass. f. If delta is greater than or equal to five counts (10 bits), then the self-test is a fail. 10. If any measurements in Step 9 fail to achieve the defined limits, then repeat Step 1 through Step 9. Repeat a maximum of five times. 11. If fewer than two out of the six self-test cycles pass, an internal self-test error flag is set. The error state is then entered. The self-test error code is sent until the device is reset. 12. Phase 4 is entered upon completing the second of any two successful self-test cycles. Influence of MD Selections On Transmitted Self-Test Data Table 36. Phase 3 Data Transmitted During Internal Self-Test MD1 0 0 1 1 MD0 0 1 0 1 Data Device OK Range Delimiter Device OK When the internal self-test mode is selected, the type of data transmitted during Phase 3 is dependent on the setting of the Phase 2 mode select bits (MD1 and MD0). See Table 36 and Table 39 for the Device OK code. See the Phase 2: Device Data Transmission section for specifics of the delimiter and range codes. Rev. 0 | Page 36 of 56 ADXL180 ENTER SELF-TEST CYCLE WAIT 32 SAMPLES CALCULATE STD = VSTP – VSTZ1 AVERAGE 64 SAMPLES VSTZ1 STDMIN < STD < STDMAX NO YES ASSERT SELF-TEST SIGNAL CALCULATE STZ = |VSTZ1 – VSTZ2 | WAIT 32 SAMPLES NO STZ ≤ 4 LSB* AVERAGE 64 SAMPLES VSTP *10-BIT LSB YES INCREMENT PASS COUNT DEASSERT SELF-TEST SIGNAL INCREMENT CYCLE COUNT WAIT 32 SAMPLES PASS COUNT = 2 YES ENTER PHASE 4 AVERAGE 64 SAMPLES VSTZ2 NO OFFSETMIN < VSTZ1 < OFFSETMAX NO CYCLE COUNT = 6 NO ENTER SELF-TEST CYCLE YES YES SET SELF-TEST FAIL CODE YES Figure 28. Internal Self-Test State Machine Figure 27. First Half Is Joined to Second Half of ST Chain Rev. 0 | Page 37 of 56 07544-049 ENTER ERROR STATE 07544-048 OFFSETMIN< VSTZ2 < OFFSETMAX NO ADXL180 specifics. No acceleration data is transmitted when the ADXL180 is in the error state. PHASE 4: AUTO-ZERO INITIALIZATION If auto-zero is not enabled, upon entering Phase 4, the ADXL180 immediately passes from Phase 4 to Phase 5. PHASE 5: NORMAL OPERATION Fast Auto-Zero Mode If auto-zero is enabled, the fast auto-zero routine begins upon entering Phase 4. The last offset average measurement (VSTZ2) of Phase 3 is used as a starting value for the fast auto-zero routine. This occurs whether internal or external self-test has been selected. See the External Self-Test section. The auto-zero function is described in the Auto-Zero Operation section. The ADXL180 transmits the offset corrected sensor data every 228 μs in asynchronous mode during Phase 4. When in synchronous mode, the ADXL180 transmits the offset corrected sensor data after receiving a valid synchronization pulse during Phase 4. The number of sensor values sent during Phase 4 is 65,535. Therefore, in asynchronous mode, the Phase 4 time period is nominally 15 seconds long, during which time the device fully responds to acceleration input. Error Reporting If an error is detected during Phase 4, (for example, offset out of range, OTP parity error, and so forth), the appropriate error code is set and the error state is entered. The error code is transmitted until the device is reset. See Table 39 for error code If auto-zero is not enabled, upon entering Phase 5, the ADXL180 transmits the measured (raw) acceleration signal every 228 μs (in asynchronous mode) until power down. In synchronous mode, raw data is transmitted in response to every synchronization pulse until power down. Slow Auto-Zero If auto-zero is enabled, the slow auto-zero routine begins upon entering Phase 5. The ADXL180 transmits the offset corrected acceleration signal every 228 μs (in asynchronous mode) until power down. In synchronous mode, offset corrected data is transmitted in response to every synchronization pulse until power down. The auto-zero function is described in the AutoZero Operation section. Error Reporting Although the auto-zero routine continually corrects for offset drift, if an error is detected during Phase 5, (for example, offset out of range, OTP parity error, and so forth), the appropriate error code is set and the error state is entered. The error code is transmitted until the device is reset. See Table 39 for error code specifics. No acceleration data is transmitted when the ADXL180 is in the error state. Rev. 0 | Page 38 of 56 ADXL180 SIGNAL RANGE AND FILTERING TRANSFER FUNCTION OVERVIEW THREE-POLE BESSEL FILTER The three-pole, low-pass Bessel filter has a selectable −3 dB corner (fLP). The corner can be set to 100 Hz, 200 Hz, 400 Hz, or 800 Hz by programming the filter corner (FC) bits in the configuration registers. In the pass band between fHP and fLP, the response of the ADXL180 is flat with the nominal scale factor defined by the settings of the range (RG) bits in the configuration registers (see Figure 29). The auto-zero function creates a first-order high-pass filter with a −3 dB corner at fLP. Note that the output of this filter is slew rate limited. The autozero function can be disabled by setting the appropriate bit in the configuration registers. See the Specifications section for more information. Table 38. FC Low-Pass Filter Bandwidth Frequency Select Codes –3dB NOMINAL SENSITIVITY FC0 0 1 0 1 −3 dB LP Frequency 400 Hz 200 Hz 100 Hz 800 Hz By configuring the FC1 and FC0 bits as shown in Table 38, the output filter on the ADXL 180 can be set. This adjusts the −3 dB frequency of the output filter to the desired bandwidth. The ADXL180 low-pass filter is a third-order, low-pass Bessel filter with a −60 dB per decade roll-off. See the Specifications table for more information on the tolerances of the low-pass filter bandwidth. AUTO-ZERO OPERATION +20dB/DECADE AUTO-ZERO FILTER fHP FREQUENCY The auto-zero function is enabled by setting the appropriate bit in the configuration registers, see Table 44. This function helps reduce slow offset drifts due to aging, temperature, and so forth. The acceleration signal offset is determined by passing the acceleration signal through a one-pole digital low-pass filter. The output of this filter is then slew rate limited. The slew rate limited offset value is then subtracted from the acceleration data. This forms a slew rate limited high-pass filter as shown in Figure 30. –60dB/DECADE BESSEL FILTER fLP 07544-050 LSB/g Figure 29. Bode Plot of ADXL180 Transfer Function RANGE Table 37. RG[2:0] Sensor Range Select Codes RG2 0 0 0 0 1 1 1 1 FC1 0 0 1 1 RG1 0 0 1 1 0 0 1 1 RG0 0 1 0 1 0 1 0 1 If auto-zero mode is enabled, a fast offset compensation is performed during start up of Phase 4 (fast auto-zero mode). The filter output is set to the last zero reading average performed by the self-test (Phase 3). The −3 dB frequency of the digital low-pass filter is approximately 0.08 Hz, and the slew rate limiter output (and therefore the offset correction) is updated every 0.5 seconds. The fast update mode (Phase 4) is 15 seconds long in asynchronous mode and 65,535 × tPS in synchronous mode (see the Phase 4: Auto-Zero Initialization section). Range ±50 g ±100 g ±250 g ±150 g ±200 g ±350 g ±500 g Not used The ADXL180 is configurable into the g-ranges shown in Table 37. Adjusting the device g-range alters the g/LSB scale factor. Selecting the 50 g range offers increased data resolution of 0.125 g/LSB; however, input signals above 50 g appear clipped on the output of the device. Selecting a higher g-rating decreases the resolution of data; however, it allows for a wider full-scale range of observable signals. If auto-zero mode is enabled, an offset compensation is performed during normal operation (Phase 5). This offset compensation is performed at a slower rate than during the auto-zero initialization (Phase 4). The −3 dB frequency of the digital low-pass filter is approximately 0.01 Hz and the slew rate limiter output (and therefore the offset correction) is updated every five seconds. The slow update mode persists until power down. See the Phase 5: Normal Operation section. The range of the offset corrected output is reduced compared to when the auto-zero is disabled. This is the function of the limiter block in Figure 30. This range reduction is shown in Table 16 and Table 17. Rev. 0 | Page 39 of 56 ADXL180 Offset Drift Monitoring Cumulative offset drift is monitored during the normal operation of the ADXL180. Offset drift monitoring occurs at the same rate as auto-zero but runs independent of whether auto-zero is enabled or disabled. An offset error is flagged if the offset correction exceeds the maximum specified value. The appropriate error code is sent in the next data frame transmitted to the control module (see the Offset Error/Offset Drift Monitoring section). This message is sent continuously until power to the ADXL180 is removed. The error status clears on the next power-on-reset. AUTO-ZERO DISABLE BESSEL LP FILTER TRANSMISSION PERIOD M U X 10-BIT ADC DIGITAL LP FILTER SLEW RATE LIMITER LIMITER OFFSET OVERRANGE DETECT LIMITER ENABLE FAST/SLOW Figure 30. Auto-Zero Signal Path Rev. 0 | Page 40 of 56 TO SERIAL PORT 07544-052 gSENSOR ADXL180 ERROR DETECTION OVERVIEW The ADXL180 monitors its internal operation and reports errors. The error reporting codes differ depending on whether the state vector has been enabled. Table 39 describes the errors and the specific codes transmitted in various configurations. The state vector allows the ADXL180 to report specific errors if enabled. If the state vector is not enabled, a single error code is sent regardless of the type of error. The error code is transmitted every 228 μs in asynchronous mode until power down. The error code is transmitted in response to every synchronization pulse in synchronous mode until power down. PARITY ERROR DUE TO COMMUNICATIONS PROTOCOL CONFIGURATION BIT ERROR As shown in Table 39, an error code is generated if the parity of the ADXL180 device OTP memory is incorrect. However, if this error is due to a parity error in one of the ERC, SVD, DAT, or MAN bits that govern the format of the transmitted message, the error code is transmitted in an alternate data format. Receive system designs that recognize repeated message transmissions, wrong data lengths, and incorrect Manchester encoding help to detect more easily that an error code is being set. Table 39. Status/Error Coding Error Configuration Error Offset Error Self-Test Error OTP Parity Error Device OK Device Not OK (NOK) 1 State Vector Enabled 10-Bit 8-Bit Data Mode Data Mode 0x7F 127d 0x1F9 505d 0x7E 126d 0x1F8 504d 0x7D 125d 0x1F7 503d 0x7C 124d 0x1F6 502d 0x7B 123d 0x1E7 487d 0x7A 122d 0x1F4 500d State Vector Disabled 10-Bit 8-Bit Data Mode Data Mode 0x7D 125d 0x1F4 500d 0x7D 125d 0x1F4 500d 0x7D 125d 0x1F4 500d 0x7D 125d 0x1F4 500d 0x7B 123d 0x1E7 487d 0x7D 125d 0x1F4 500d A self-test error reported during Phase 5 indicates a failure of the internal self-test circuit, not a sensor self-test error. Rev. 0 | Page 41 of 56 Error Reporting Active in Phases 2 5 4, 51 4, 5 3 3, 4, 5 ADXL180 SELF-TEST ERROR In the ADXL180, self-test is automatically run during Phase 3. If the internal self-test mode is selected, then the device enters into the self-test routine as detailed in Figure 27 and Figure 28. The device reports a failure during Phase 3 if it does not detect two successful self-test pulses. When external self-test is enabled, the device enters into the self- test routine as detailed in Figure 27 and Figure 28; however, it reports all six self-test pulses to the control module. The control module is responsible for designation of a device failure. OFFSET ERROR/OFFSET DRIFT MONITORING VOV VDD (NOMINAL) VPUR VOLTAGE REGULATOR MONITOR RESET OPERATION The control module can reset the ADXL180 by lowering the bus supply voltage to cause a power-fail reset. Figure 31 shows that, for both the undervoltage and overvoltage trip thresholds, there is a nominal 120 mV hysteresis before the voltage regulator returns to within specification. No data transmission occurs while the ADXL180 is in the reset state. The bus current is held at the idle level during reset. VHYST VHYST POWER OK RESET TIME Figure 31. Voltage Regulator Monitor Reset Functionality Rev. 0 | Page 42 of 56 07544-053 VOLTAGE REGULATOR OUTPUT (VDD) During Phase 3, an offset calculation is performed by averaging the offset value with self-test deasserted (see Figure 27 for more details). If this value is outside of the datasheet specifications, then an error is reported at the start of Phase 5. Additionally, the ADXL180 continuously monitors long term offset drift. If the long-term offset correction exceeds the maximum specified value, then an offset error is reported. This error is reported independent of whether or not the auto-zero functionality has been enabled. ADXL180 TEST AND DIAGNOSTIC TOOLS VSCI SIGNAL CHAIN INPUT TEST PIN VSCO ANALOG SIGNAL CHAIN OUTPUT TEST PIN The VSCI signal chain input test pin allows the excitation of the signal chain from the input of the sensor interface circuitry (sensor amplifier) through to the output of the current mode serial port. The function of this pin becomes active after the pin input voltage exceeds the level of about 0.8 V. Below this level, the ADXL180 does not respond to the voltage applied to the VSCI pin. Above the threshold limit of 0.8 V, the voltage signal at the VSCI pin is applied to the sensor interface circuitry in parallel with the sensor signal. The VSCO analog signal chain output test pin provides access to the sensor signal chain analog output voltage at the output of the Bessel filter. This signal is filtered and ranged as defined by the configuration register settings. It is before the digital autozero function in the signal chain. Therefore, it is not autozeroed. The configuration register SCOE bit must be set to 1 to enable this output. The signal output resistance is typically 50 Ω. Connect this output to a high impedance input only. The applied signal is zero when the input signal is equal to the common-mode potential of the sensor interface circuitry (~VDD/2 V), see Figure 32. The VSCI input scaling for all ranges is typically about 640 μV/g. The scaling of the VSCI input voltage to the ADC code output is dependent on the range setting of the part. Table 40. SCOE VSCO Signal Chain Output Enable SCOE 0 1 Definition VSCO output disabled. (Default.) VSCO output enabled. Analog output prior to ADC conversion is present on VSCO pin. Connect VSCO to high impedance input, or data or sensor data may be adversely affected. +600g g-Range 50 g 100 g 150 g 200 g 250 g 350 g 500 g 0g 07544-054 g EQUIVALENT Table 41. Typical VSCO Sensitivity Per g-Range –600g ~0.8 VDD/2 ~3.2 VSCI TEST PIN VOLTAGE Figure 32. VSCI Signal Chain Input Test Pin Transfer Function Rev. 0 | Page 43 of 56 Sensitivity 32.8 mV/g 16.4 mV/g 10.8 mV/g 8.2 mV/g 6.56 mV/g 4.69 mV/g 3.28 mV/g ADXL180 CONFIGURATION SPECIFICATION the ADXL180 via voltage modulation of the VBP pin with respect to the VBN pin. This signal uses pulse duration modulation to combine the clock and digital data. The clock and data are encoded as shown in Figure 33. OVERVIEW The ADXL180 configuration mode allows access to the userprogrammable nonvolatile configuration registers used to define the function of the device. The configuration mode is entered by writing a 16-bit configuration mode enable key code to the VBP pin during Phase 1 of the ADXL180 start-up sequence, which begins immediately after power is applied to the ADXL180. The 16-bit configuration mode enable key code is 0x5A5A with no start or parity bits (see Figure 34). The configuration mode key is sent LSB first. Note that the configuration mode key code is 16 bits long and the configuration mode read/write command data frames are 14 bits long. This helps avoid misinterpretation of either by the ADXL180. The ADXL180 acknowledges entering the configuration mode by transmitting the contents of the CREG2 register. This register contains the configuration/user data programming bit (CUPRG) status. This allows the user’s configuration/test system to determine whether the ADXL180 configuration OTP fuse memory has been programmed without further communication. If the configuration mode is not entered within the Phase 1 initialization time period, the ADXL180 treats the pulses on the VBP pin as synchronization pulses (in synchronous mode) or ignores them in asynchronous mode. All configuration mode data sent to the ADXL180, including the configuration mode enable key code is communicated to tIB tIB tIB tIB tPGO tPG1 tPG1 tIB tPG0 VCT VBP DATA 0 1 0 1 07544-055 CLOCK TIME Figure 33. Configuration Mode Receive Pulse Width Data and Clock Encoding TRANSMITTED FIRST CONFIGURATION MODE KEY 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 07544-056 CONFIGURATION MODE ENABLE KEY DATA FRAME (16 BITS) Figure 34. Configuration Mode Enable Key Code Data Frame ttm1 16-BIT CONFIG MODE KEY CODE ttm2 VBP IBUS TIME Figure 35. Configuration Mode Entry Key Code Sequence Rev. 0 | Page 44 of 56 07544-057 18-BIT TRANSMIT DATA: CREG2 ADXL180 TRANSMITTED FIRST START BITS 1 0 STATE VECTOR 0 1 2 DATA 0 1 2 3 4 ADDRESS 5 6 7 0 1 2 P 3 0 07544-058 DATA FRAME (18 BITS) Figure 36. Configuration Mode Transmit Data Frame CONFIGURATION MODE TRANSMIT COMMUNICATIONS PROTOCOL In configuration mode, the ADXL180 transmits the configuration mode register data through the current mode Manchester encoded serial port. The configuration mode protocol is fixed regardless of the actual settings of the configuration registers (RAM or OTP). The transmit communication protocol used by the ADXL180 in configuration mode is • • • • • • • • • Manchester-1 data encoding Two start bits (10b) 4-bit configuration mode register address field 8-bit configuration mode register data field 3-bit state vector field (101b) One parity bit (even) Synchronization pulse disabled Auto-zero disabled Data is transmitted LSB first This is an 18-bit protocol (including the two start bits). Although similar to the ADIFX protocol, it is different in that parity, and not CRC, is used as the error checking code. This distinguishes configuration mode messages from normal operation messages. Figure 36 shows the configuration mode data frame format. Table 42 shows the configuration mode transmit data bit mapping. Excluding the two start bits, the word is 16 bits long. Data Bit DB15 (transmitted last) is the parity bit. The configuration mode transmit parity is even. The parity bit is set to either 1 or 0 to make the total number of 1s in the 16-bit word an even number. Data Bits[DB14:DB11] are the four configuration mode register address bits. The following eight data bits, DB10 through DB3, are the eight configuration mode register data bits. The next three bits, DB2 through DB0, are the state vector bits. In the configuration mode, the state vector is 101b. This data frame format is different from the ADIFX format. Rev. 0 | Page 45 of 56 ADXL180 operation and a 1 indicates a read operation. The parity bit is set for even parity. The parity bit should be set to 0 or 1 to make the total number of 1s in the data frame even. The data is transmitted LSB first as shown in Table 42. CONFIGURATION MODE COMMAND (RECEIVE) COMMUNICATIONS PROTOCOL The 8-bit configuration register data is passed to the ADXL180 with a read/write command bit, a 4-bit configuration register address, and a parity bit as shown in Figure 37. The read/write bit is set to indicate the desired action. A 0 indicates a write TRANSMITTED FIRST DATA 0 1 2 3 4 ADDRESS 5 6 7 0 1 2 3 R/W P 0 0 07544-059 RECEIVE DATA FRAME (14 BITS) Figure 37. Configuration Mode Command (Receive) Data Frame Table 42. Configuration Mode Transmit Data Bit Mapping DB15 Parity DB14 Addr 3 DB13 Addr 2 DB12 Addr 1 DB11 Addr 0 DB10 Data Bit 7 (MSB) DB9 Data Bit 6 DB8 Data Bit 5 DB7 Data Bit 4 DB6 Data Bit 3 Rev. 0 | Page 46 of 56 DB5 Data Bit 2 DB4 Data Bit 1 DB3 Data Bit 0 (LSB) DB2 State Vector 2 DB1 State Vector 1 DB0 State Vector 0 ADXL180 written to RAM, read back from the RAM, and transmitted to the user’s test/configuration system as a handshake. This provides a data integrity check for data write commands. If there is an attempt to write data to a RAM register after the CUPRG bit is set, the data is ignored by the ADXL180 (that is, it has no affect on the device). The data returned by the ADXL180 is the contents of the addressed OTP fuse register. This is the same result as if a data read command had been issued. CONFIGURATION MODE COMMUNICATIONS HANDSHAKING Configuration mode communications uses a handshaking protocol. Following the completion of a data write or data read command being written to the ADXL180, a data frame is transmitted from the ADXL180 through the current mode serial port. This forms a handshake acknowledgment with the test system (see Figure 38). The source of the data (RAM or OTP) transmitted in the handshake data frame is dependent on whether the OTP memory has been programmed. When the test/configuration system sends a data read command, the data contained in the data frame is ignored and the data that is contained in the addressed configuration mode register is sent to the test/configuration system in response. The data sent is always read from the RAM registers. If the CUPRG bit has not been set (that is, the OTP fuses are not programmed), the RAM contains the last data written to it by the configuration/ test system. When the CUPRG bit is set (that is, the OTP fuses are programmed) the fuse data is loaded into the RAM registers (see Figure 40). Upon receiving a configuration mode data frame, if a parity error is detected, the ADXL180 returns a handshake data frame with the state vector code set to the status/error state vector code (110b). The 8-bit data field and the 4-bit address field are both set to all 0s. When the test system sends a data write command, the data that was written to the addressed configuration mode register is then DATA READ SEQUENCE DATA WRITE SEQUENCE ttm1 ttm2 HANDSHAKE HANDSHAKE IBUS ttm1 DATA READ TRANSMIT DATA TRANSMIT DATA TIME Figure 38. Configuration Mode Write Data and Read Data Sequences Rev. 0 | Page 47 of 56 07544-060 VBP ttm2 DATA WRITE ADXL180 The ADXL180 can be configured to send this data as part of the device data transmitted during Phase 2 of the power-up initialization sequence. CONFIGURATION AND USER DATA REGISTERS The configuration and user data registers are the user register, UREG, and the three configuration registers, CREG0, CREG1, and CREG2 (see Table 44). The ADXL180 can be programmed to provide a variety of signal chain characteristics and device operating modes via Configuration Register CREG0, Configuration Register CREG1, and Configuration Register CREG2. The configuration register and user register data can be programmed into nonvolatile OTP memory. PROGRAMMING THE CONFIGURATION AND USER DATA REGISTERS When the desired configuration and user data has been written to the UREG and CREG registers, writing a 1 to the configuration/user data program command bit (CUPRG) causes the four bytes of configuration/user data to be permanently written to the configuration/user data OTP fuse memory. The OTP fuses are programmed sequentially by the ADXL180 without further user intervention. This takes about 12 ms (tCUP in Figure 39). The ADXL180 ignores all test system read and write commands while it is programming the fuses. In general, the CREG registers hold data that alters the function of the ADXL180. The data contained in the UREG has no affect on the operation of the ADXL180. The UREG bits are typically used to indicate information such as module housing type and sensing axis. The ADXL180 can be programmed to transmit the UREG bits as part of the device data during power-up Phase 2, depending on the Phase 2 mode that is selected. The ADXL180 acknowledges the completion of the programming sequence of the configuration/user data OTP memory by sending the contents of the CREG2 register as described in the Configuration Mode Transmit Communications Protocol section. The CREG2 register contains the configuration/user data programming bit (CUPRG). This allows the test/configuration system to verify that the configuration/user data programming bit has been programmed without further communication. The contents of all of the configuration and user registers should then be read to confirm that they have been programmed to the desired settings. Figure 39 illustrates a sample sequence of commands to write and then program the configuration and user registers. CONFIGURATION MODE EXIT The configuration mode is exited by writing 0x80 to Address 1010b. A communication handshake is transmitted by the ADXL180 after the configuration mode exit address is written. The ADXL180 reenters its start-up sequence at the beginning of the initialization phase (Phase 1) immediately upon exiting the configuration mode. This method does not generate a device reset. Alternatively, the configuration mode can be exited by lowering the bus supply voltage to cause a power-on-reset to occur. This method generates a device reset. Once programmed, the OTP fuse memory settings are loaded into the RAM registers during the Phase 1 initialization of the ADXL180 start-up sequence. Figure 40 shows the basic structure of the configuration and user RAM/OTP memory structure. SERIAL NUMBER AND MANUFACTURER IDENTIFICATION DATA REGISTERS The serial number and manufacturer identification data registers can be read in configuration mode. The manufacturer identification register is fixed at the mask level. The serial number is programmed during the final manufacturing stages. CONFIGURATION MODE KEY SEQUENCE DATA WRITE SEQ DATA WRITE SEQ DATA WRITE SEQ UREG CREG0 CREG1 DATA WRITE SEQ INTERNAL CONFIGURATION REGISTER OTP PROGRAMMING SEQUENCE DATA WRITE CM CREG2 VBP EXIT CREG2 HANDSHAKE IBUS tCUP 07544-061 VDD TIME Figure 39. Example Configuration Register OTP Programming Sequence Rev. 0 | Page 48 of 56 ADXL180 FROM RECEIVE SERIAL PORT A RAM MUX OTP FUSE OTP DATA B CUPRG SEL 07544-062 OTP PROGRAM TO TRANSMIT SERIAL PORT AND CONFIGURATION CONTROL LOGIC Figure 40. Configuration Mode RAM and OTP Register Structure The CUPRG bit is automatically programmed to the locked state (1) at the end of the configuration/user data OTP fuse programming sequence. This prevents any further writes to the UREG and CREG RAM registers as well as disables the configuration/user data OTP fuse programming circuitry. The read value of this bit indicates whether the configuration/user data OTP memory has been programmed (that is, locked). A 1 indicates that the OTP memory block has been programmed and further test system writes to either the RAM or OTP configuration/user data registers are ignored. OTP PROGRAMMING CONDITIONS AND CONSIDERATIONS Note that all configuration/user OTP registers are programmed when the CUPRG bit is set regardless of whether the registers have been written to. The OTP registers can be programmed one time only. During normal operation and in configuration mode, the internal voltage regulator is operating at 4.2 V nominal. This internal voltage changes to a nominal value of 6.5 V during the time that the ADXL180 is programming the configuration and user OTP fuses (tCUP). The VBP supply voltage must be held at or above the minimum fuse programming value specified in the specification table for proper fuse programming. The VBP supply current is increased during fuse programming as shown in Figure 39. The configuration/test system must supply at least the value IFP as specified. The configuration and user registers are production tested for user programming at 25°C. If the minimum programming voltage is not achieved, the ADXL180 does not respond to subsequent communications requests because it waits for the required programming voltage. The device does not attempt to program unless the required voltage level is achieved. The user’s test system should include a timeout check if the device does not respond due to this situation. When properly programmed, the ADXL180 issues a handshake back to the command module. Do not attempt to write to the configuration registers or attempt another OTP programming step until this handshake has been received. CONFIGURATION/USER REGISTER OTP PARITY The configuration/user data OTP CU parity bit (CUPAR) must be programmed to provide even parity for the configuration/ user data OTP memory. The CUPAR bit should be set to either a 1 or a 0 to make the total number of 1s in the configuration/ user data OTP memory (including the value of the OTP CU parity bit) an even number. The configuration/user data OTP memory is defined as CREG0, CREG1, CREG2, and UREG. The parity calculation must include the state of all register bits including all of the UD and NU bits. The CUPRG bit must also be included. During normal operation, once the configuration/ user data programming bit is set, the ADXL180 monitors the parity of the configuration/user data OTP memory and compares it against the programmed value of the CU parity bit in CREG2. An OTP parity error is flagged if the monitored parity and the programmed parity differ. See the Error Detection section. CONFIGURATION MODE ERROR REPORTING The receive communication parity error and the OTP programming voltage error are the two errors reported by the ADXL180 when in configuration mode. The OTP parity, configuration and other normal mode (run-time) errors are suppressed in configuration mode. The state vector code is set to a state vector of 5 (101b). The 8-bit error data code is shown in Table 43. The 4-bit address field is set to 8 (1000b). Table 43. Configuration Mode Error Codes Error Data Code 0000 0000b Rev. 0 | Page 49 of 56 Error Description Configuration mode receive parity error ADXL180 CONFIGURATION REGISTER REFERENCE The following tables define the codes for each programmable field in the three configuration registers (CREG0, CREG1, and CREG2). The default setting (unprogrammed state) of all bits in all configuration registers is zero. As a result, the default configuration of the ADXL180 is compatible with the ADIFX operation mode and communication protocol as implemented in the ADXS101 satellite transmitter. Table 44. Configuration and User Data Bit Map Configuration Mode Register Address 0000b 0001b 0010b 0011b 0100b…1001b 1010b 1011b 1100b 1101b 1110b 1111b 1 2 Configuration Mode Register Name UREG CREG0 CREG1 CREG2 NU CMEXIT SN0 SN1 SN2 SN3 MFGID MSB D7 UD7 UD8 STI CUPRG X 1 SNB7 SNB15 SNB23 SNB31 SNPRG D6 UD6 BDE AZE CUPAR X 0 SNB6 SNB14 SNB22 SNB30 SNPAR D5 UD5 MD1 SYEN SCOE X 0 SNB5 SNB13 SNB21 SNB29 REV2 X = don’t care. NU = not used. Rev. 0 | Page 50 of 56 D4 UD4 MD0 ADME FC1 X 0 SNB4 SNB12 SNB20 SNB28 REV1 D3 UD3 FDLY ERC FC0 X 0 SNB3 SNB11 SNB19 SNB27 REV0 D2 UD2 DLY2 SVD RG2 X 0 SNB2 SNB10 SNB18 SNB26 MFGID2 D1 UD1 DLY1 DAT RG1 X 0 SNB1 SNB9 SNB17 SNB25 MFGID1 LSB D0 UD0 DLY0 MAN RG0 X 0 SNB0 SNB8 SNB16 SNB24 MFGID0 ADXL180 UD[7:0] USER DATA BITS FDLY The user register is for arbitrary user data. It does not have any influence on sensor operation. This data is transmitted during Phase 2 of the state machine. For more information on transmission format and timing, in particular depending on the setting of MD bits, see the ADXL180 State Machine section. Table 49. Fixed Delay Mode FDLY 0 1 Table 45. User Data Bit Definitions ADME Bit Names UD0 UD1 UD2 UD3 UD4 UD5 UD6 UD7 Table 50. Autodelay Mode Enable (ADME ) Options Definition User Data Bit 0. No function, data only. User Data Bit 1. No function, data only. User Data Bit 2. No function, data only. User Data Bit 3. No function, data only. User Data Bit 4. No function, data only. User Data Bit 5. No function, data only. User Data Bit 6. No function, data only. User Data Bit 7. No function, data only. ADME 0 STI Table 51. Self Test Internal (STI) Options STI 0 Table 46. UD8 Configuration Bit Definition Reserved, don’t care (default) Reserved, don’t care 1 The value of the RS bit may be transmitted during Phase 2, independent of UD[7:0], depending on the selection of the MD bits. BDE Table 47. Bus Discharge Enable BDE 0 1 Definition Autodelay mode disabled. The part does not check for a second device on the line and does not pull any extra current during startup. (Default.) Autodelay mode detection enabled. IDET pull-down for 6 ms at power-up. 1 UD8 CONFIGURATION BIT UD8 0 1 Definition Fixed delay mode disabled (default). Fixed delay mode enabled. Device transmits data in the time slot delayed by tDLY as defined by DLY[2:0]. Definition Bus discharge disabled (default). Bus discharge enabled. Only active when SYEN = 1. Definition External self-test. User must monitor self-test data to verify proper operation. Device does not monitor its own response to the self-test stimulus. (Default.) Internal self-test. The device monitors its own self-test data to determine proper operation. Table 52. Phase 3 Data Transmitted When STI = 1 MD1 0 0 1 1 MD0 0 1 0 1 Data Device OK Range Delimiter Device OK FC[1:0] The bus discharge enable (BDE) bit enables a discharge of the bus voltage after a synchronization pulse is detected. If the BDE bit is set, the ADXL180 changes the bus current (IBUS) level from IIDLE to ISIG when a valid synchronization pulse has been detected. See the Synchronous Communication section for more details and timing information. Table 53. FC Low-Pass Filter Bandwidth Frequency Select Codes SCOE RG[2:0] FC1 0 0 1 1 FC0 0 1 0 1 −3 dB LP Frequency 400 Hz 200 Hz 100 Hz 800 Hz Table 48. SCOE VSCO Signal Chain Output Enable Table 54. RG[2:0] Sensor Range Select Codes SCOE 0 1 RG2 0 0 0 0 1 1 1 1 Definition VSCO output disabled. (Default.) VSCO output enabled. Analog output prior to ADC conversion is present on VSCO pin. Connect VSCO to high impedance input or data or sensor data may be adversely affected. Rev. 0 | Page 51 of 56 RG1 0 0 1 1 0 0 1 1 RG0 0 1 0 1 0 1 0 1 Range ±50 g ±100 g ±250 g ±150 g ±200 g ±350 g ±500 g Not used ADXL180 MD[1:0] Table 55. Phase 2 (Device Data) Transmission Mode Select Codes Table 56. Phase 2 (Device Data) Transmission Mode Select Codes MD1 0 0 MD0 0 1 Name Mode 0 Mode 1 1 1 0 1 Mode 2 Mode 3 MD1 0 0 1 1 Definition ADIFX mode device data Range data only (range selection limited) 8-bit coded device data 10-bit coded device data MD0 0 1 0 1 Data Device OK Range Delimiter Device OK Table 57. MD Settings and Device Data Ranges with SVD and AZE Settings (Replication of Table 23) Mode (Device Data) 0: ADIFX 3 (All Configuration Data, Serial Number And Manufacturer ID) 1: Range Data Only3 (Limited Range Selection) 2: 8-Bit Coded Device Data3 (UD[7:0], Serial Number And Range) 3: 10-Bit Coded Device Data 4 (UD[7:0], Serial Number And Range) MD1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 MD0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SVD 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D AZE 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Range Full Reduced Configuration error Configuration error Full Reduced Reduced Reduced Full Reduced Reduced Reduced Full Reduced Reduced Reduced SVD is the state vector disable configuration bit. AZE is the auto-zero enable configuration bit. If Phase 2 Mode 0, Mode 1, or Mode 2 is selected, the device data is 8-bit data. If the 10-bit data mode is selected in combination with Phase 2 Mode 0, Mode 1, or Mode 2, the 8-bit device data is left justified in the 10-bit data field. The two LSBs are held at zero (see Table 24). 4 The 10-bit device data mode (Phase 2 Mode 3) is incompatible with the 8-bit data mode (the DAT bit is set to 1). The device transmits a configuration error code if Phase 2 Mode 3 is selected and the DAT bit is set to 1. No sensor data is transmitted. 2 3 Rev. 0 | Page 52 of 56 ADXL180 SYEN DAT Table 58. Sync Enable (SYEN) Options Table 61. DAT Data Bit Options SYEN 0 DAT 0 1 Definition Synchronization pulse disabled. Device transmits data according to state machine based on internal clock every 228 μs when powered (default). Synchronization pulse enabled. The device requires a synchronization pulse to sample and transmit data according to state machine. AZE 1 Definition Auto-zero function is disabled. Phase 4 has no messages. Device immediately moves to normal data (Phase 5) after self-test (Phase 3). (Default.) Auto-zero function enabled. See Auto-Zero Operation section for details. ERC 1 SVD 0 1 Definition State vector enabled (default). State vector disabled, reduced data range used. CUPAR AND CUPRG Table 63. Device Configuration Bit Definitions Name CUPAR CUPRG Table 60. Error Check (ERC) Bit Options ERC 0 SVD Table 62. SVD Data Bit Options Table 59. AZE Auto Zero Enable AZE 0 1 Definition 10-bit data sensor data transmitted. 8-bit Phase 2 configuration data left-justified in 10-bit data frame (default). 8-bit sensor data transmitted. Definition 3-bit CRC is included in message. Calculate CRC using the polynomial x3 + x1 + x0. (Default.) One parity bit is included in the message. CRC is not used. It is a bit that is set such that even parity is achieved in the transmitted message. Rev. 0 | Page 53 of 56 Setting 0 1 0 1 Definition Data dependent setting Data dependent setting Configuration OTP memory not programmed Configuration OTP memory programmed ADXL180 AXIS OF SENSITIVITY XOUT = 0g ADXL180 XXXX XXXX XOUT = +1g ADXL180 XXXX XXXX XOUT = 0g XOUT = 0g EARTH’S SURFACE Figure 41. Output Response vs. Orientation Rev. 0 | Page 54 of 56 07544-003 XOUT = –1g ADXL180 XXXX XXXX ADXL180 XXXX XXXX ADXL180 BRANDING XL 180Z # P Y W W CL CL CL CL CL 07544-006 Y Figure 42. ADXL180 Laser Brand Table 64. ADXL180 Branding Key Line 1 2 3 3 4 4 Text XL 180Z YY WW CL P Description Accelerometer ADXL180Z Year code Week code Lot code Country of origin (Philippines) Rev. 0 | Page 55 of 56 ADXL180 OUTLINE DIMENSIONS 0.15 MAX 5.10 5.00 SQ 4.90 0.20 MIN 0.50 0.40 0.30 PIN 1 INDICATOR 1.83 1.73 1.63 (BOTTOM VIEW) 3.31 3.21 3.11 0.05 MAX 0.02 NOM 1.35 1.25 1.15 0.25 BSC EXPOSED PADS TOP VIEW 1.50 1.45 1.40 SEATING PLANE 0.50 BSC 0.30 0.25 0.18 1.62 1.52 1.42 3.70 3.60 3.50 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 080408-A PIN 1 INDICATOR Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP_LQ] 5 mm × 5 mm Body, Thick Quad (CP-16-8) Dimensions shown in millimeters ORDERING GUIDE Model ADXL180WCPZ-RL 1 1 Temperature Range −40°C to +125°C Package Description 16-Lead LFCSP_LQ Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07544-0-8/08(0) Rev. 0 | Page 56 of 56 Package Option CP-16-8