Cypress CY62146EV30 4-mbit (256k x 16) static ram Datasheet

CY62146EV30 MoBL®
4-Mbit (256K x 16) Static RAM
Features
■
Very High Speed: 45 ns
■
Temperature Ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
■
Wide Voltage Range: 2.20V–3.60V
■
Pin Compatible with CY62146DV30
■
Ultra Low Standby Power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA
current. Ultra low active current is ideal for providing More
Battery Life™ (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when: the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE ) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
■
Ultra Low Active Power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy Memory Expansion with CE and OE Features
■
Automatic Power Down when Deselected
■
CMOS for Optimum Speed and Power
■
Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II
Packages
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
advanced circuit design designed to provide an ultra low active
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K x 16
RAM Array
IO0–IO7
IO8–IO15
•
BHE
WE
CE
OE
BLE
A17
A15
A16
A13
A14
A11
Cypress Semiconductor Corporation
Document Number: 38-05567 Rev. *D
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 23, 2009
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CY62146EV30 MoBL®
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [1, 2]
Figure 2. 44-Pin TSOP II [1]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
IO10
A5
A6
I/O1
I/O2
C
VSS I/O11
A17
A7
VCC
D
VCC
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Product Portfolio
Power Dissipation
Product
Range
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62146EV30LL
Ind’l/Auto-A
Min
Typ [3]
Max
2.2
3.0
3.6
45 ns
f = fmax
Standby ISB2 (μA)
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
2
2.5
15
20
1
7
Notes
1. NC pins are not connected on the die.
2. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document Number: 38-05567 Rev. *D
Page 2 of 13
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CY62146EV30 MoBL®
DC Input Voltage [4, 5] ........... –0.3V to 3.9V (VCC max + 0.3V)
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................ –65°C to + 150°C
Latch-up Current...................................................... >200 mA
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Operating Range
Supply Voltage to Ground
Potential .............................–0.3V to + 3.9V (VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State [4, 5]................ –0.3V to 3.9V (VCCmax + 0.3V)
Ambient
Temperature
Device
Range
CY62146EV30
Industrial/
Auto-A
VCC [6]
–40°C to +85°C 2.2V to 3.6V
Electrical Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
Parameter
VOH
VOL
VIH
VIL
Description
Test Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Min
Typ [3]
Max
Unit
IOH = –0.1 mA
2.0
V
IOH = –1.0 mA, VCC > 2.70V
2.4
V
IOL = 0.1 mA
0.4
V
IOL = 2.1 mA, VCC > 2.70V
0.4
V
VCC = 2.2V to 2.7V
1.8
VCC + 0.3
V
VCC= 2.7V to 3.6V
2.2
VCC + 0.3
V
VCC = 2.2V to 2.7V
–0.3
0.6
V
VCC= 2.7V to 3.6V
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
μA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
+1
μA
ICC
VCC Operating Supply Current
f = fmax = 1/tRC
15
20
mA
2
2.5
f = 1 MHz
VCC = VCC(max),
IOUT = 0 mA
CMOS levels
ISB1
Automatic CE Power down
Current — CMOS Inputs
CE > VCC−0.2V,
VIN > VCC–0.2V or VIN < 0.2V
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE), VCC = 3.60V
1
7
μA
ISB2 [7]
Automatic CE Power down
Current — CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
1
7
μA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to Vcc(min) and 200 μs wait time after Vcc stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 38-05567 Rev. *D
Page 3 of 13
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CY62146EV30 MoBL®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
VFBGA
TSOP II
Unit
75
77
°C/W
10
13
°C/W
Figure 3. AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
90%
90%
10%
VCC
OUTPUT
30 pF
10%
GND
Rise Time = 1 V/ns
R2
INCLUDING
JIG AND
SCOPE
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
Parameters
RTH
V
2.50V
3.0V
Unit
R1
16667
1103
Ω
R2
15385
1554
Ω
RTH
8000
645
Ω
VTH
1.20
1.75
V
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Conditions
Min
VCC for Data Retention
[7]
Data Retention Current
tCDR [8]
Chip Deselect to Data
Retention Time
tR [9]
Operation Recovery Time
Typ [3]
Max
1.5
VCC = 1.5V, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Industrial/Auto-A
Unit
V
0.8
7
μA
0
ns
tRC
ns
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
VDR > 1.5V
tCDR
VCC(min)
tR
CE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
Document Number: 38-05567 Rev. *D
Page 4 of 13
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CY62146EV30 MoBL®
Switching Characteristics
Over the Operating Range [10, 11]
45 ns (Industrial/Auto-A)
Parameter
Description
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
45
ns
45
ns
ns
10
ns
tACE
CE LOW to Data Valid
45
tDOE
OE LOW to Data Valid
22
ns
tLZOE
OE LOW to Low-Z [12]
18
ns
OE HIGH to High-Z
tLZCE
CE LOW to Low-Z [12]
tHZCE
CE HIGH to High-Z
5
[12, 13]
tHZOE
10
[12, 13]
ns
18
0
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Down
tDBE
BLE / BHE LOW to Data Valid
[12]
tLZBE
BLE / BHE LOW to Low-Z
tHZBE
BLE / BHE HIGH to High-Z [12, 13]
Write Cycle
ns
ns
ns
45
ns
22
ns
5
ns
18
ns
[14]
tWC
Write Cycle Time
45
ns
tSCE
CE LOW to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BLE / BHE LOW to Write End
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
[12, 13]
tHZWE
WE LOW to High-Z
tLZWE
WE HIGH to Low-Z [12]
ns
18
10
ns
ns
Notes
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
14. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document Number: 38-05567 Rev. *D
Page 5 of 13
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CY62146EV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled) [15, 16]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [16, 17]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
15. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 38-05567 Rev. *D
Page 6 of 13
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CY62146EV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [14, 18, 19]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA IO
tSD
NOTE 20
tHD
DATAIN
tHZOE
Figure 8. Write Cycle No. 2 (CE Controlled) [14, 18, 19]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
DATAIN
NOTE 20
tHZOE
Notes:
18. Data IO is high impedance if OE = VIH.
19. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
20. During this period, the IOs are in output state and input signals must not be applied.
Document Number: 38-05567 Rev. *D
Page 7 of 13
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CY62146EV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [19]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA IO
NOTE 20
tHD
DATAIN
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [19]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA IO
NOTE 20
tSD
tHD
DATAIN
tLZWE
Document Number: 38-05567 Rev. *D
Page 8 of 13
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CY62146EV30 MoBL®
Truth Table
CE
WE
OE
BHE
BLE
H
X
X
X
X
Inputs/Outputs
High-Z
Mode
Deselect/Power down
Power
Standby (ISB)
L
X
X
H
H
High-Z
Output Disabled
Active (ICC)
L
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
L
H
High-Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
45
Ordering Code
CY62146EV30LL-45BVXI
Package
Diagram
Package Type
51-85150 48-Ball VFBGA (Pb-free)
CY62146EV30LL-45ZSXI
51-85087 44-Pin TSOP II (Pb-free)
CY62146EV30LL-45ZSXA
51-85087 44-Pin TSOP II (Pb-free)
Operating
Range
Industrial
Automotive-A
Please contact your local Cypress sales representative for availability of other parts
Document Number: 38-05567 Rev. *D
Page 9 of 13
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CY62146EV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
0.15(4X)
Document Number: 38-05567 Rev. *D
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85150-*D
Page 10 of 13
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CY62146EV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP II, 51-85087
51-85087-*A
Document Number: 38-05567 Rev. *D
Page 11 of 13
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CY62146EV30 MoBL®
Document History Page
Document Title: CY62146EV30 MoBL®, 4-Mbit (256K x 16) Static RAM
Document Number: 38-05567
Orig. of
Submission
REV. ECN NO. Change
Description of Change
Date
**
223225
AJU
See ECN
New Data Sheet
*A
247373
SYT
See ECN
Changed Advance Information to Preliminary
Moved Product Portfolio to Page 2
Changed VCC stabilization time in footnote #8 from 100 μs to 200 μs
Removed Footnote #14(tLZBE) from Previous revision
Changed ICCDR from 2.0 μA to 2.5 μA
Changed typo in Data Retention Characteristics(tR) from 100 μs to tRC ns
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18
ns for 45 ns Speed Bin
Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for
45 ns Speed Bin
Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
Speed Bin
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed tDBE from 15 to 18 ns for 35 ns Speed Bin
Changed Ordering Information to include Pb-Free Packages
*B
414807
ZSD
See ECN
Changed from Preliminary information to Final
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62146EV30
Changed ball E3 from DNU to NC
Removed the redundant foot note on DNU.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ values from 0.7 μA to 1 μA and Max values from 2.5
μA to 7 μA.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed ICCDR from 2.5 μA to 7 μA.
Added ICCDR typical value.
Changed tLZOE from 3 ns to 5 ns
Changed tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tHZCE from 22 ns to 18 ns
Changed tPWE from 30 ns to 35 ns.
Changed tSD from 22 ns to 25 ns.
Updated the package diagram 48-ball VFBGA from *B to *D
Updated the ordering information table and replaced the Package Name column
with Package Diagram.
*C
925501
VKN
See ECN
Added footnote #8 related to ISB2 and ICCDR
Added footnote #12 related AC timing parameters
*D
2678796 VKN/PYRS
03/25/2009
Added Automotive-A information
Document Number: 38-05567 Rev. *D
Page 12 of 13
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CY62146EV30 MoBL®
Sales, Solutions, and Legal Information
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05567 Rev. *D
Revised March 23, 2009
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MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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