Cypress CY62137CV33 2m (128k x 16) static ram Datasheet

CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
2M (128K x 16) Static RAM
Features
Life™ (MoBL®) in portable applications such as cellular telephones. The devices also has an automatic power-down feature that significantly reduces power consumption by 80%
when addresses are not toggling. The device can also be put
into standby mode reducing power consumption by more than
99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW, and WE LOW).
• Very high speed: 55 ns and 70 ns
• Voltage range:
— CY62137CV25: 2.2V–2.7V
— CY62137CV30: 2.7V–3.3V
— CY62137CV33: 3.0V–3.6V
— CY62137CV: 2.7V–3.6V
• Pin-compatible with the CY62137V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
•
•
•
•
•
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
— Typical active current: 5.5 mA @ f = fmax (70-ns
speed)
Low and ultra-low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball FBGA
Functional Description[1]
The CY62137CV25/30/33 and CY62137CV are high-performance CMOS static RAMs organized as 128K words by 16
bits. These devices feature advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SENSE AMPS
ROW DECODER
10
128K x 16
RAM Array
2048 x 1024
I/O0 – I/O7
I/O8 – I/O15
BHE
WE
CE
OE
BLE
A12
A13
A14
A15
A16
A11
COLUMN DECODER
CE
Power -down
Circuit
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05201 Rev. *D
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 20, 2002
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Pin Configuration[2, 3]
FBGA (Top View)
4
5
3
6
A1
A2
NC
A
A3
A4
CE
I/O0
B
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
NC
A7
I/O3
VCC
D
VCC
I/O12 DNU
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
1
2
BLE
OE
A0
I/O8
BHE
I/O9
NC
H
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current ................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Device
Ambient
Temperature TA
Range
Supply Voltage to Ground Potential –0.5V to VCCMAX + 0.5V
CY62137CV25
DC Voltage Applied to Outputs
in High-Z State[4] ....................................–0.5V to VCC + 0.3V
CY62137CV30
2.7V to 3.3V
CY62137CV33
3.0V to 3.6V
CY62137CV
2.7V to 3.6V
DC Input Voltage[4] .................................... −0.5V to VCC + 0.3V
Industrial –40°C to +85°C
VCC
2.2V to 2.7V
Output Current into Outputs (LOW) .............................20 mA
Product Portfolio
Power Dissipation
Operating, ICC (mA)
VCC Range (V)
Product
VCC(min.) VCC(typ.)
[5]
f = 1 MHz
VCC(max.)
Speed
(ns)
Typ.[5]
55
f = fmax
Standby, ISB2 (µA)
Max.
Typ.[5]
Max.
Typ.[5]
Max.
1.5
3
7
15
2
10
70
1.5
3
5.5
12
55
1.5
3
7
15
2
10
70
1.5
3
5.5
12
55
1.5
3
7
15
5
15
CY62137CV25LL
2.2
2.5
2.7
CY62137CV30LL
2.7
3.0
3.3
CY62137CV33LL
3.0
3.3
3.6
70
1.5
3
5.5
12
CY62137CVLL
2.7V
3.3
3.6
70
1.5
3
5.5
12
5
15
CY62137CVSL
2.7V
3.3
3.6
70
1.5
3
5.5
12
1
5
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or VSS to ensure proper application.
4. VIL(min.) = –2.0V for pulse durations less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05201 Rev. *D
Page 2 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Electrical Characteristics Over the Operating Range
CY62137CV25-55
Parameter
Description
Test Conditions
Min.
CY62137CV25-70
Typ.[5] Max.
VOH
Output HIGH Voltage
IOH = –0.1 mA
VCC = 2.2V
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = 2.2V
VIH
Input HIGH Voltage
1.8
VCC +
0.3V
VIL
Input LOW Voltage
–0.3
IIX
Input Leakage Current GND < VI < VCC
–1
IOZ
Output Leakage
Current
–1
ICC
VCC Operating Supply f = fMAX = 1/tRC
Current
f = 1 MHz
GND < VO < VCC, Output Disabled
2.0
Automatic CE
CE > VCC – 0.2V
Power-down Current— VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs
f = fmax (Address and Data Only),
f=0 (OE, WE, BHE, and BLE)
ISB2
Automatic CE
CE > VCC – 0.2V
Power-down Current— VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 2.7V
CMOS Inputs
2.0
0.4
V
1.8
VCC +
0.3V
V
0.6
–0.3
0.6
V
+1
–1
+1
µA
+1
–1
+1
µA
mA
7
15
5.5
12
1.5
3
1.5
3
2
10
2
10
CY62137CV30-55
Parameter
Description
Test Conditions
Min.
Output HIGH Voltage
IOH = –1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
VIH
Input HIGH Voltage
2.2
VCC +
0.3V
VIL
Input LOW Voltage
–0.3
IIX
Input Leakage Current GND < VI < VCC
–1
IOZ
Output Leakage
Current
–1
ICC
VCC Operating Supply f = fMAX = 1/tRC
Current
f = 1 MHz
ISB1
Automatic CE
CE > VCC – 0.2V
Power-down Current— VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs
f = fmax (Address and Data Only),
f=0 (OE, WE, BHE, and BLE)
ISB2
Automatic CE
CE > VCC – 0.2V
Power-down Current— VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs
f = 0, VCC = 3.3V
Min.
2.4
Typ.[5] Max.
2.4
Unit
V
0.4
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
µA
CY62137CV30-70
Typ.[5] Max.
VOH
GND < VO < VCC, Output Disabled
Unit
V
0.4
VCC = 2.7V
IOUT = 0 mA
CMOS Levels
ISB1
Typ.[5] Max.
Min.
0.4
V
2.2
VCC +
0.3V
V
0.8
–0.3
0.8
V
+1
–1
+1
µA
+1
–1
+1
µA
mA
7
15
5.5
12
1.5
3
1.5
3
2
10
2
10
µA
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –1.0 mA
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 3.0V
CY62137CV33-55
CY62137CV33-70
CY62137CV-70
Min. Typ.[5] Max.
Min. Typ.[5] Max. Unit
2.4
2.4
VCC = 2.7V
VCC = 3.0V
VCC = 2.7V
Document #: 38-05201 Rev. *D
V
2.4
0.4
V
0.4
V
0.4
V
Page 3 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
CY62137CV33-55
CY62137CV33-70
CY62137CV-70
Min. Typ.[5] Max.
Min. Typ.[5] Max. Unit
VIH
Input HIGH Voltage
2.2
VCC +
0.3V
2.2
VCC +
0.3V
V
VIL
Input LOW Voltage
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
+1
–1
+1
µA
ICC
VCC Operating Supply Current f = fMAX = 1/tRC
mA
f = 1 MHz
VCC = 3.6V
IOUT = 0 mA
CMOS
Levels
7
15
5.5
12
1.5
3
1.5
3
ISB1
Automatic CE
CE > VCC – 0.2V
Power-down Current —CMOS VIN > VCC – 0.2V or VIN < 0.2V,
Inputs
f = fmax (Address and Data Only),
f=0 (OE, WE, BHE, and BLE)
5
15
5
15
ISB2
Automatic CE
CE > VCC – 0.2V
LL
Power-down Current —CMOS VIN > VCC – 0.2V or VIN < SL
Inputs
0.2V,
f = 0, VCC = 3.6V
5
15
5
15
1
5
µA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
6
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)[6]
ΘJC
Thermal Resistance
(Junction to Case)[6]
Test Conditions
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
BGA
Unit
55
°C/W
16
°C/W
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC Typ
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
Rise TIme: 1 V/ns
Equivalent to:
Fall Time: 1 V/ns
THÉVENIN EQUIVALENT
RTH
OUTPUT
Parameters
R1
R2
RTH
VTH
2.5V
16600
15400
8000
1.20
3.0V
1105
1550
645
1.75
VTH
3.3V
1216
1374
645
1.75
Unit
Ω
Ω
Ω
V
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05201 Rev. *D
Page 4 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Conditions
Min.
Typ.[5]
1.5
VCC= 1.5V
LL
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V SL
tCDR[6]
Chip Deselect to Data Retention Time
tR[7]
Operation Recovery Time
1
Max.
Unit
Vccmax
V
6
4
µA
0
ns
tRC
ns
Data Retention Waveform[8]
DATA RETENTION MODE
VCC(min.)
VCC
VCC(min.)
VDR > 1.5 V
tR
tCDR
CE or
BHE.BLE
Switching Characteristics Over the Operating Range[9]
55 ns
Parameter
Description
Min
70 ns
Max
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to
tHZOE
55
Low-Z[10]
OE HIGH to High-Z
tLZCE
CE LOW to Low-Z
tHZCE
CE HIGH to High-Z[10, 12]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
tDBE
BHE/BLE LOW to Data Valid
tLZBE[11]
BHE/BLE LOW to Low-Z[10]
tHZBE
Write
BHE/BLE HIGH to
55
10
70
10
ns
25
10
20
0
0
55
5
ns
ns
70
ns
70
ns
5
20
ns
ns
25
55
ns
ns
5
20
High-Z[10, 12]
ns
10
5
[10, 12]
[10]
70
ns
25
ns
Cycle[13]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
Notes:
7. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
8. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
11. If both byte enables are toggled together this value is 10 ns.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05201 Rev. *D
Page 5 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Switching Characteristics Over the Operating Range[9] (continued)
55 ns
Parameter
Description
Min
70 ns
Max
Min
Max
Unit
tAW
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
tBW
BHE/BLE Pulse Width
50
60
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High-Z
[10, 12]
20
[10]
tLZWE
WE HIGH to Low-Z
10
25
10
ns
ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)
DATA VALID
[15, 16]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
BHE/BLE
ttLZOE
LZOE
tHZOE
tDOE
tHZBE
tLZBE
DATA OUT
tDBE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
Notes:
14. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05201 Rev. *D
Page 6 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
[13, 17, 18]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 19
tHZOE
Write Cycle No. 2 (CE Controlled)
[13, 17, 18]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 19
tHZOE
Notes:
17. Data I/O is high-impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05201 Rev. *D
Page 7 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[18]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tHD
tSD
DATAI/O
NOTE 19
DATAIN VALID
tLZWE
tHZWE
[18]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 19
Document #: 38-05201 Rev. *D
tHD
DATAIN VALID
Page 8 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C)
.
Operating Current vs. Supply Voltage
14.0
12.0
12.0
12.0
12.0
ICC (mA)
10.0
MoBL
(f = fmax,
55 ns)
8.0
(f = fmax,
70 ns)
6.0
10.0
(f = fmax,
55 ns)
MoBL
8.0
(f = fmax,
70 ns)
6.0
4.0
4.0
2.0
(f = 1 MHz)
0.0
2.2
2.5 2.7
SUPPLY VOLTAGE (V)
10.0
8.0
(f = fmax,
55 ns)
MoBL
6.0
(f = fmax,
70 ns)
4.0
2.0
2.0
(f = 1 MHz)
0.0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
ICC (mA)
14.0
ICC (mA)
14.0
ICC (mA)
14.0
(f = 1 MHz)
0.0
3.6
3.3
3.0
SUPPLY VOLTAGE (V)
10.0
8.0
MoBL
(f = fmax,
70 ns)
6.0
4.0
2.0
(f = 1 MHz
0.0
3.6
3.3
2.7
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
8.0
MoBL
6.0
6.0
4.0
2.0
MoBL
8.0
10.0
8.0
6.0
6.0
4.0
4.0
4.0
2.0
2.0
2.0
0
0
0
0
2.2 2.5 2.7
SUPPLY VOLTAGE (V)
12.0
MoBL
10.0
ISB (µA)
8.0
MoBL
12.0
10.0
ISB (µA)
10.0
ISB (µA)
ISB (µA)
12.0
3.0
2.7
3.3
3.0
SUPPLY VOLTAGE (V)
3.3
3.6
LL
SL
2.7
SUPPLY VOLTAGE (V)
3.3
3.6
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
MoBL
60
MoBL
60
MoBL
50
50
40
40
40
40
30
30
30
30
20
20
20
10
10
10
0
0
0
2.2
2.5
2.7
SUPPLY VOLTAGE (V)
Document #: 38-05201 Rev. *D
2.7
3.0
3.3
SUPPLY VOLTAGE (V)
TAA (ns)
50
TAA (ns)
50
TAA (ns)
TAA (ns)
60
MoBL
20
10
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
0
2.7
3.3
3.6
SUPPLY VOLTAGE (V)
Page 9 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High-Z
Deselect/Power-down
Standby (ISB)
X
X
X
H
H
High-Z
Deselect/Power-down
Standby (ISB)
L
H
L
L
L
Data Out (I/OO–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
L
H
High-Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/OO–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/OO–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
Voltage
Range (V)
Package
Name
70
CY62137CV25LL-70BAI
2.2–2.7
BA48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
55
Package Type
CY62137CV25LL-70BVI
2.2–2.7
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV30LL-70BAI
2.7–3.3
BA48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62137CV30LL-70BVI
2.7–3.3
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV33LL-70BAI
3.0–3.6
BA48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62137CV33LL-70BVI
3.0–3.6
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CVLL-70BAI
2.7–3.6
BA48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62137CVLL-70BVI
2.7–3.6
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CVSL-70BAI
2.7–3.6
BA48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62137CVSL-70BVI
2.7–3.6
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV25LL-55BAI
2.2–2.7
BA48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62137CV25LL-55BVI
2.2–2.7
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV30LL-55BAI
2.7–3.3
BA48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62137CV30LL-55BVI
2.7–3.3
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV33LL-55BAI
3.0–3.6
BA48A
48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62137CV33LL-55BVI
3.0–3.6
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Document #: 38-05201 Rev. *D
Operating
Range
Industrial
Page 10 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Package Diagrams
48-ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
Document #: 38-05201 Rev. *D
Page 11 of 13
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05201 Rev. *D
Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document History Page
Document Title: CY62137CV25/30/33 MoBL® and CY62137CV MoBL® 2M (128K x 16) Static RAM
Document Number: 38-05201
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
112393
02/19/02
GAV
New Data Sheet (advance information)
*A
114015
04/25/02
JUI
Added BV package diagram
Changed from Advance Information to Preliminary
*B
117064
07/12/02
MGN
Changed from Preliminary to Final
*C
118122
09/10/02
MGN
Added new part number: CY62137CV with wider voltage (2.7V – 3.6V).
Added new SL power bin for new part number.
For TAA = 55 ns, improved tPWE min. from 45 ns to 40 ns.
For TAA = 70 ns, improved tPWE min. from 50 ns to 45 ns.
For TAA = 70 ns, improved tLZWE min. from 5 ns to 10 ns.
*D
118761
09/23/02
MGN
Improved Typ. ICC spec to 7 mA (for 55 ns) and 5.5 mA (for 70 ns).
Improved Max ICC spec to 15 mA (for 55 ns) and 12 mA (for 70 ns).
For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns.
Changed upper spec. for Supply Voltage to Ground Potential to VCCMAX + 0.5V.
Changed upper spec. for DC Voltage Applied to Outputs in High-Z State and DC
Input Voltage to VCC + 0.3V.
Document #: 38-05201 Rev. *D
Page 13 of 13
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