AD AD7999 4-channel, 12-/10-/8-bit adc with i2ccompatible interface in 8-lead sot23 Datasheet

Preliminary Technical Data
4-Channel, 12-/10-/8-Bit ADC with I2CCompatible Interface in 8-Lead SOT23
AD7991/AD7995/AD7999
FUNCTIONAL BLOCK DIAGRAM
FEATURES
12-/10-/8-bit ADC with fast conversion time: 2 µs typ
4 Channel / 3 Channel with Reference input
Specified for VDD of 2.7 V to 5.5 V
Sequencer operation
Temperature Range: -40 °C to 125 °C
I2C®-compatible serial interface supports standard, fast,
and High-speed modes
2 versions allow 2 I2C addresses
Low power consumption
Shutdown mode: 1 µA max
8-lead SOT23 package
VDD
VIN0
VIN1
VIN2
VIN3/Vref
I/P
MUX
12-/10-/8-BIT
SAR
ADC
T/H
CONTROL
LOGIC &
I2C
SCL
SDA
INTERFACE
AD7991/7995/7999
APPLICATIONS
GND
System Monitoring
Battery Powered Systems
Data Acquisition
Medical Instruments
Figure 1.
GENERAL DESCRIPTION
The AD7991/AD7995/AD7999 are 12-/10-/8-bit, low power,
successive approximation ADCs with an I2C-compatible
interface. The parts operate from a single 2.7 V to 5.5 V power
supply and feature a 2 µs conversion time. The part contains a
4-channel multiplexer and track-and-hold amplifier that can
handle input frequencies up to 11 MHz.
PRODUCT HIGHLIGHTS
The AD7991/AD7995/AD7999 provides a 2-wire serial
interface compatible with I2C interfaces. The parts come in two
versions with each part having an individual I2C address. This
will allow two of the same devices be connected to the same I2C
bus. Both parts support standard, fast and high-speed I2C
interface modes
The AD7991/AD7995/AD7999 normally remain in a shutdown
state while not converting, and power up only for conversions.
The conversion process is controlled by a command mode,
where every time an I2C read operation is executed on the
AD7991/AD7995/AD7999, a conversion is performed and the
result is returned on the I2C bus.
The reference for the part is taken from VDD, this allows the
widest dynamic input range to the ADC. Thus the analog input
range to the ADC is 0V to VDD. An external reference may also
be used with this part. The external reference may be applied
through the Ain3 input.
1.
4 single ended analog input channels, with the option of
having 3 single ended analog input channels and 1
reference input channel.
2.
I2C compatible serial Interface. Standard, Fast and HsModes
3.
Automatic shutdown.
4.
Reference derived from the power supply or external
reference.
5. 8-lead SOT23 Package.
Table 1 Related Devices
Device Number
Resolution
Input Channels
AD7998
12
8
AD7997
10
8
AD7994
12
4
AD7993
10
4
AD7992
12
2
Rev. PrB
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD7991/AD7995/AD7999
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Connection Diagram ................................................... 16
Applications....................................................................................... 1
Analog Input ............................................................................... 16
Functional Block Diagram .............................................................. 1
Internal Register Structure ............................................................ 18
General Description ......................................................................... 1
Configuration Register .............................................................. 18
Revision History ............................................................................... 2
SAMPLE DELAY and BIT TRIAL DELAY ............................ 18
ad7991 Specifications....................................................................... 3
Conversion Result Register ....................................................... 19
ad7995 Specifications....................................................................... 5
Serial Interface ................................................................................ 20
ad7999 Specifications....................................................................... 7
Serial Bus Address...................................................................... 20
I2C Timing Specifications ................................................................ 9
Writing to the AD7991/AD7995/AD7999.................................. 21
Absolute Maximum Ratings.......................................................... 11
Writing a Single Byte of Data to the Configuration Register 21
ESD Caution................................................................................ 11
reading from the AD7991/AD7995/AD7999 ............................. 22
Pin Configuration and Function Descriptions........................... 12
Placing the AD7991/AD7995/AD7999................................... 23
Typical Performance Characteristics ........................................... 13
into High Speed Mode............................................................... 23
Terminology .................................................................................... 14
Mode of operation.......................................................................... 24
Theory of Operation ...................................................................... 15
Outline Dimensions ....................................................................... 25
Converter Operation.................................................................. 15
Ordering Guide............................................................................... 25
REVISION HISTORY
PrB/Sept 06—Revision 0: Initial Version
Rev.PrB | Page 2 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
AD7991 SPECIFICATIONS
Temperature range is as follows: B version −40°C to +85°C, Y version -40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; fSCL
= 3.4 Mhz Unless otherwise noted; TA = TMIN to TMAX.
Table 2.
Parameter
DYNAMIC PERFORMANCE1
B Version
Y Version
Unit
Signal-to-Noise + Distortion
(SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise
(SFDR)2
Intermodulation Distortion (IMD)2
70.5
70.5
dB min
71
–78
–79
71
–78
–79
dB min
dB max
dB max
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation2
–90
–90
-90
–90
–90
-90
dB typ
dB typ
dB typ
Full Power Bandwidth2
11
2
11
2
MHz typ
MHz typ
12
±1
±0.2
+1/–0.9
12
±1
±0.2
+1/–0.9
Bits
LSB max
LSB typ
LSB max
±0.2
±4
±0.5
TBD
±2
±0.5
TBD
±0.2
±4
±0.5
TBD
±2
±0.5
TBD
LSB typ
LSB max
LSB max
ppm/°C typ
LSB max
LSB max
ppm/°C typ
0 to REFIN
±1
30
0 to REFIN
±1
30
V
µA max
pF typ
1.2 to VDD
1.2 to VDD
±1
30
69
±1
pF typ
69
V min/V
max
µA max
kΩ typ
0.7 (VDD)
0.3 (VDD)
±1
10
0.7 (VDD)
0.3 (VDD)
±1
10
V min
V max
µA max
pF max
DC ACCURACY
Resolution
Integral Nonlinearity1, 2
Differential Nonlinearity1, 2
Offset Error2
Offset Error Matching
Offset Temperature drift
Gain Error2
Gain Error Matching
Gain Temperature drift
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage Range
DC Leakage Current
REFIN Input Capacitance
Input Impedance
LOGIC INPUTS (SDA, SCL)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN3
Test Conditions/Comments
FIN = 10 kHz sine wave for fSCL from 1.7
MHz to
3.4 MHz
FIN = 1 kHz sine wave for fSCL up to 400
kHz
fa = 10.1 kHz, fb = 9.9 kHz for fSCL from
1.7 MHz to 3.4 MHz
fa = 1.1 kHz, fb = 0.9 kHz for fSCL up to
400 kHz
Rev. PrB | Page 3 of 25
FIN = 108 Hz; see the Terminology
Section
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 12
bits
VIN = 0 V or VDD
AD7991/AD7995/AD7999
Parameter
Input Hysteresis, VHYST
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
THROUGHPUT RATE
Preliminary Technical Data
B Version
0.1 (VDD)
0.4
0.6
±1
10
Y Version
0.1 (VDD)
0.4
V max
0.6
V max
±1
µA max
10
pF max
Straight (Natural) Binary
ADC Operating, Interface Active
Power Down, Interface Active
Power-Down , Interface Inactive
Power Down, Interface Inactive
ISINK = 3 mA
ISINK = 6 mA
2.7/5.5
us max
2.7/5.5
V min/max
Digital inputs = 0 V or VDD
0.06/0.1
0.3/0.6
TBD
TBD
1/2
0.06/0.1
0.3/0.6
TBD
TBD
1/2
mA max
mA max
mA max
mA max
µA max
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
0.495/2.2
1.98/6.05
3.3/11
mW max
mW max
mW max
mW max
µW max
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
Power Dissipation
Fully Operational
ADC Operating, Interface Active
Test Conditions/Comments
See the Serial Interface section
18 * (1/fSCL)
POWER REQUIREMENTS
VDD
IDD
Unit
V min
0.495/2.2
1.98/6.05
3.3/11
1
Max/min AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-mode SCL frequencies. Specifications
outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2
See the terminology section
3
Guaranteed by Initial Characterization.
Rev.PrB | Page 4 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
AD7995 SPECIFICATIONS
Temperature range for Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; fSCL = 3.4 Mhz Unless otherwise noted;
TA = TMIN to TMAX.
Table 3.
Parameter
DYNAMIC PERFORMANCE1
Y Version
Unit
Signal-to-Noise + Distortion (SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
61
–75
–76
dB min
dB max
dB max
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation2
Full Power Bandwidth2
–86
–86
-90
11
2
dB typ
dB typ
dB typ
MHz typ
MHz typ
10
±0.5
±0.5
±2
±0.5
TBD
±1.5
±0.5
TBD
Bits
LSB max
LSB max
LSB max
LSB max
ppm/°C typ
LSB max
LSB max
ppm/°C typ
0 to REFIN
±1
30
V
µA max
pF typ
1.2 to VDD
±1
30
69
V min/V max
µA max
pF typ
kΩ typ
0.7 (VDD)
0.3 (VDD)
±1
10
0.1 (VDD)
V min
V max
µA max
pF max
V min
DC ACCURACY
Resolution
Integral Nonlinearity1, 2
Differential Nonlinearity1, 2
Offset Error2
Offset Error Matching
Offset Temperature drift
Gain Error2
Gain Error Matching
Gain Temperature drift
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage Range
DC Leakage Current
REFIN Input Capacitance
Input Impedance
LOGIC INPUTS (SDA, SCL)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN3
Input Hysteresis, VHYST
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
THROUGHPUT RATE
Test Conditions/Comments
FIN = 10 kHz sine wave for fSCL from 1.7 MHz to
3.4 MHz
FIN = 1 kHz sine wave for fSCL up to 400 kHz
fa = 10.1 kHz, fb = 9.9 kHz for fSCL from 1.7 MHz
to 3.4 MHz
fa = 1.1 kHz, fb = 0.9 kHz for fSCL up to 400 kHz
0.4
0.6
±1
10
V max
V max
µA max
pF max
Straight (Natural) Binary
FIN = 108 Hz; see the Terminology Section
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 10 bits
When Vin3/VREF = VIN3, Vref = VDD
VIN = 0 V or VDD
ISINK = 3 mA
ISINK = 6 mA
See the Serial Interface section
18 * (1/fSCL)
us max
Rev. PrB | Page 5 of 25
AD7991/AD7995/AD7999
Parameter
POWER REQUIREMENTS
VDD
IDD
ADC Operating, Interface Active
Power Down, Interface Active
Power-Down , Interface InActive
Preliminary Technical Data
Y Version
Unit
2.7/5.5
V min/max
Digital inputs = 0 V or VDD
0.06/0.1
0.3/0.6
TBD
TBD
1/2
mA max
mA max
mA max
mA max
µA max
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
0.495/2.2
1.98/6.05
3.3/11
mW max
mW max
mW max
mW max
µW max
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
Power Dissipation
Fully Operational
ADC Operating, Interface Active
Power Down, Interface Inactive
Test Conditions/Comments
1
Max/min AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-mode SCL frequencies. Specifications
outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2
See the Terminology section
3
Guaranteed by Initial Characterization.
Rev.PrB | Page 6 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
AD7999 SPECIFICATIONS
Temperature range for Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; fSCL = 3.4 Mhz Unless otherwise noted;
TA = TMIN to TMAX.
Table 4.
Parameter
DYNAMIC PERFORMANCE1
Y Version
Unit
Signal-to-Noise + Distortion (SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
49
–65
–65
dB min
dB max
dB max
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation2
Full Power Bandwidth2
–76
–76
-90
11
2
dB typ
dB typ
dB typ
MHz typ
MHz typ
8
±0.3
±0.3
±0.5
±0.3
TBD
±0.3
±0.3
TBD
Bits
LSB max
LSB max
LSB max
LSB max
ppm/°C typ
LSB max
LSB max
ppm/°C typ
0 to REFIN
±1
30
V
µA max
pF typ
1.2 to VDD
±1
30
69
V min/V max
µA max
pF typ
kΩ typ
0.7 (VDD)
0.3 (VDD)
±1
10
0.1 (VDD)
V min
V max
µA max
pF max
V min
DC ACCURACY
Resolution
Integral Nonlinearity1, 2
Differential Nonlinearity1, 2
Offset Error2
Offset Error Matching
Offset Temperature drift
Gain Error2
Gain Error Matching
Gain Temperature drift
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage Range
DC Leakage Current
REFIN Input Capacitance
Input Impedance
LOGIC INPUTS (SDA, SCL)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN3
Input Hysteresis, VHYST
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
THROUGHPUT RATE
Test Conditions/Comments
FIN = 10 kHz sine wave for fSCL from 1.7 MHz to
3.4 MHz
FIN = 1 kHz sine wave for fSCL up to 400 kHz
fa = 10.1 kHz, fb = 9.9 kHz for fSCL from 1.7 MHz
to 3.4 MHz
fa = 1.1 kHz, fb = 0.9 kHz for fSCL up to 400 kHz
0.4
0.6
±1
10
V max
V max
µA max
pF max
Straight (Natural) Binary
FIN = 108 Hz; see the Terminology section
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 8 bits
When Vin3/VREF = VIN3, Vref = VDD
VIN = 0 V or VDD
ISINK = 3 mA
ISINK = 6 mA
See the Serial Interface section
18 * (1/fSCL)
us max
Rev. PrB | Page 7 of 25
AD7991/AD7995/AD7999
Parameter
POWER REQUIREMENTS
VDD
IDD
ADC Operating, Interface Active
Power Down, Interface Active
Power-Down , Interface Inactive
Preliminary Technical Data
Y Version
Unit
2.7/5.5
V min/max
Digital inputs = 0 V or VDD
0.06/0.1
0.3/0.6
TBD
TBD
1/2
mA max
mA max
mA max
mA max
µA max
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
0.495/2.2
1.98/6.05
3.3/11
mW max
mW max
mW max
mW max
µW max
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
Power Dissipation
Fully Operational
ADC Operating, Interface Active
Power Down, Interface Inactive
Test Conditions/Comments
1
Max/min AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-mode SCL frequencies. Specifications
outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2
See the Terminology section
3
Guaranteed by Initial Characterization.
Rev.PrB | Page 8 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
I2C TIMING SPECIFICATIONS
Guaranteed by initial characterization. All values measured with the input filtering enabled. CB refers to the capacitive load on the bus
line. tr and tf measured between 0.3 VDD and 0.7 VDD.
Standard, Fast and High speed mode timing specifications apply to the AD7991/AD7995/AD7999-1. See Figure 2.Unless otherwise noted,
VDD = 2.7 V to 5.5 V; TA =TMIN to TMAX.
Table 5.
Parameter
fSCL
t1
t2
t3
t41
t5
t6
t7
t8
t9
Conditions
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High Speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High Speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Min
Limit at TMIN, TMAX
Max
100
400
3.4
1.7
Unit
kHz
kHz
4
0.6
MHz
MHz
µs
µs
60
120
4.7
1.3
ns
ns
µs
µs
160
320
250
100
10
0
0
ns
ns
ns
ns
ns
µs
µs
0
0
4.7
0.6
160
4
0.6
160
4.7
1.3
4
0.6
160
3.45
0.9
702
150
20 + 0.1 CB
1000
300
ns
ns
µs
µs
ns
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
10
20
80
160
ns
ns
Rev. PrB | Page 9 of 25
Description
Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
tSU;DAT, data setup time
tHD;DAT, data hold time
tSU;STA, setup time for a repeated START condition
tHD;STA, hold time for a repeated START condition
tBUF, bus free time between a STOP and a START condition
tSU;STO, setup time for STOP condition
tRDA, rise time of SDA signal
AD7991/AD7995/AD7999
Parameter
t10
Limit at TMIN, TMAX
Max
300
20 + 0.1 CB
300
Conditions
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
t11
t11A
Min
10
20
tSP
2
40
80
1000
ns
ns
ns
20 + 0.1 CB
300
ns
10
20
80
160
300
300
ns
ns
ns
ns
40
80
50
10
ns
ns
ns
ns
µs typ
20 + 0.1 CB
10
20
0
0
1
Description
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
tRCL1, rise time of SCL signal after a repeated START
condition and after an acknowledge bit
tFCL, fall time of SCL signal
Pulse width of suppressed spike
Power-up time
A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
For 3 V supplies, the maximum hold time with CB = 100 pF max is 100 ns max.
t11
t12
t6
t2
SCL
t6
t5
t3
t4
t8
t1
t9
t10
SDA
t7
P
S
S
P
03623-0-019
1
ns
ns
ns
ns
10
20
tPOWER-UP
Unit
ns
ns
80
160
1000
300
20 + 0.1 CB
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Fast mode
High speed mode
t12
Preliminary Technical Data
S = START CONDITION
P = STOP CONDITION
Figure 2. Two-Wire Serial Interface Timing Diagram
Rev.PrB | Page 10 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to GND
Analog Input Voltage to GND
Reference Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B Version)
Industrial (Y Version)
Storage Temperature Range
Junction Temperature
8-Lead SOT-23 Package
θJA Thermal Impedance
θJC Thermal Impedance
Pb/SN Temperature, Soldering
Reflow (10 sec to 30 sec)
Pb-Free Temperature, Soldering Reflow
ESD
1
Rating
−0.3 V to 7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +85°C
−40°C to +125°C
−65°C to +150°
150°C
TBD °C/W
TBD °C/W
TBD °C
TBD °C
TBD kV
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 11 of 25
AD7991/AD7995/AD7999
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCL
1
SDA
2
VIN0
3
VIN1
4
8
VDD
AD7991/
AD7995/
AD7999
7
GND
6
VIN3/VREF
TOP VIEW
5
VIN2
(Not to Scale)
Figure 3.AD7991/AD7995/AD7999 Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
SCL
SDA
VIN0
VIN1
VIN2
VIN3/VREF
7
GND
8
VDD
Function
Digital Input. Serial bus clock. External pull-up resistor required.
Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required.
Analog Input 1. Single-ended analog input channel. The input range is 0 V to Vref.
Analog Input 2. Single-ended analog input channel. The input range is 0 V to Vref.
Analog Input 3. Single-ended analog input channel. The input range is 0 V to Vref.
Analog Input 4. Single-ended analog input channel. The input range is 0 V to Vref. Can also be used to input an
external Vref signal.
Analog Ground. Ground reference point for all circuitry on the AD7991/AD7995/AD7999. All analog input
signals should be referred to this AGND voltage.
Power Supply Input. The VDD range for the AD7991/AD7995/AD7999 is from 2.7 V to 5.5 V.
Table 8. I2C Address Selection
Part Number
AD7991 -0
AD7991-1
AD7995-0
AD7995-1
AD7999-0
AD7999-1
I2C Address
010 1000
010 1001
010 1000
010 1001
010 1000
010 1001
Rev.PrB | Page 12 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4
Figure 7
Figure 5
Figure 8
Figure 6
Rev. PrB | Page 13 of 25
AD7991/AD7995/AD7999
Preliminary Technical Data
TERMINOLOGY
Signal-to-Noise and Distortion Ratio (SINAD)
The measured ratio of signal-to-noise and distortion at the output of the A/D converter. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-noise and distortion ratio for
an ideal N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, the SINAD is 49.92 dB for an 8-bit converter, 61.96 dB for
a 10-bit converter and 74 dB for a 12-bit converter.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7991/AD7995/AD7999, it is defined as
tanced in frequency from the original sine waves while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second and third-order terms are
specified separately. The calculation of intermodulation distortion is, like the THD specification, the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals, expressed in dB.
Channel-to-Channel Isolation
A measure of the level of crosstalk between channels, taken
by applying a full-scale sine wave signal to the unselected input
channels, and determining how much the 108 Hz signal is
attenuated in the selected channel. The sine wave signal applied
to the unselected channels is then varied from 1 kHz up to
2 MHz, each time determining how much the 108 Hz signal in
the selected channel is attenuated. This figure represents the
worst-case level across all channels.
Full-Power Bandwidth
The input frequency at which the amplitude of the reconstructed
fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.
V2 2 + V3 2 + V4 2 + V5 2 + V6 2
THD (dB) = 20 log
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through
sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Typically, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n equal zero. For example,
second-order terms include (fa + fb) and (fa − fb), while
third-order terms include (2fa + fb), (2fa − fb),(fa + 2fb) and
(fa − 2fb).
The AD7993/AD7994 is tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually dis-
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00…000) to
(00…001) from the ideal—that is, AGND + 1 LSB.
Offset Error Match
The difference in offset error between any two channels.
Gain Error
The deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, REFIN − 1 LSB) after the
offset error has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
Rev.PrB | Page 14 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
THEORY OF OPERATION
The AD7991/AD7995/AD7999 provides the user with a 4channel multiplexer, an on-chip track-and-hold, an A/D
converter, and an I2C-compatible serial interface, all housed in a
8-lead SOT23 package that offers the user considerable space
saving advantages over alternative solutions.
The AD7991/AD7995/AD7999 normally remains in a powerdown state while not converting. When supplies are first
applied, the part comes up in a power-down state. Power-up is
initiated prior to a conversion, and the device returns to powerdown upon completion of the conversion. This automatic
power-down feature allows power saving between conversions.
This means any read or write operations across the I2C interface
can occur while the device is in power-down.
When the ADC starts a conversion, as shown in Figure 10,
SW2 opens and SW1 moves to position B, causing the
comparator to become unbalanced. The input is disconnected
once the conversion begins. The control logic and the capacitive
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 11 shows the ADC transfer function.
CAPACITIVE
DAC
A
VIN
B
SW2
Figure 10. ADC Conversion Phase
The AD7991/AD7995/AD7999 is a successive approximation,
analog-to-digital converter based around a capacitive DAC.
Figure 9 and Figure 10 show simplified schematics of the ADC
during its acquisition and conversion phases, respectively.
Figure 9 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in position A, the comparator is held in a
balanced condition, and the sampling capacitor acquires the
signal on VIN.
ADC Transfer Function
The output coding of the AD7991/AD7995/AD7999 is straight
binary. The designed code transitions occur at successive
integer LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size
for the AD7991/AD7995/AD7999 is REFIN/4096. Figure 11
shows the ideal transfer characteristic for the
AD7991/AD7995/AD7999.
CAPACITIVE
DAC
111...111
111...110
ADC CODE
A
CONTROL
LOGIC
SW1
B
COMPARATOR
03473-0-018
SW2
COMPARATOR
AGND
CONVERTER OPERATION
VIN
CONTROL
LOGIC
SW1
03473-0-019
The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit,
single-supply, 4-channel A/D converters. The parts can be
operated from a 2.35 V to 5.5 V supply.
AGND
Figure 9. ADC Acquisition Phase
111...000
011...111
AD7991 1 LSB = REFIN/4096
AD7995 1 LSB = REFIN/1024
AD7995 1 LSB = REFIN/256
000...010
000...001
000...000
AGND +1 LSB
+REFIN -1LSB
ANALOG INPUT
0 V TO REFIN
Figure 11. AD7991/AD7995/AD7999 Transfer Characteristic
Rev. PrB | Page 15 of 25
AD7991/AD7995/AD7999
Preliminary Technical Data
TYPICAL CONNECTION DIAGRAM
ANALOG INPUT
Figure 13 shows the typical connection diagram for the
AD7991/AD7995/AD7999.
Figure 12 shows an equivalent circuit of the
AD7991/AD7995/AD7999 analog input structure. The two
diodes, D1 and D2, provide ESD protection for the analog
inputs. Care must be taken to ensure that the analog input
signal does not exceed the supply rails
by more than 300 mV. This causes these diodes to become
forward-biased and start conducting current into the substrate.
These diodes can conduct a maximum current of 10 mA
without causing irreversible damage to the part.
The reference voltage can be taken from the supply voltage VDD.
However, the AD7991/AD7995/AD7999 can be configured to
be a three-channel device with the reference voltage applied to
the VIN3/REFIN pin.
SDA and SCL form the 2-wire I2C compatible interface.
External pull-up resisters are required for both SDA and SCL
lines.
VDD
The AD7991/AD7995/AD7999-0 and the
AD7991/AD7995/AD7999-1 both support the standard, fast
and high speed I2C interface modes. Both the -0 and the -1
device will have an independent I2C address. This will allow
both device to connect to the same I2C bus without any
contention issues.
D1
R1
C1
4pF
03473-0-022
VIN
D2
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
Wake up from power-down prior to a conversion is
approximately 1 µs, and conversion time is approximately 2 µs.
The AD7991/AD7995/AD7999 enters shutdown mode again
after each conversion, which is useful in applications where
power consumption is a concern.
Figure 12. Equivalent Analog Input Circuit
Capacitor C1 in Figure 12 is typically about 4 pF and can
primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance (RON) of
a track-and-hold switch, and also the RON of the input multiplexer. The total resistor is typically about 400 Ω. C2, the ADC
sampling capacitor, has a typical capacitance of 30 pF.
+5V SUPPLY
10µF
0.1µF
RP
VIN0
VIN1
VIN2
VIN3/Vref
VDD
AD7991/
AD7995/
AD7999
C2
30pF
RP
TWO WIRE SERIAL
INTERFACE
SDA
SCL
µC/µP
GND
Figure 13. AD7991/AD7995/AD7999 Typical Connection Diagram
Rev.PrB | Page 16 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC bandpass filter on the relevant analog input pin. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function
of the particular application.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. THD increases as the
source impedance increases, and performance degrades. Figure
14 and Figure 15 shows the THD vs. the analog input signal
frequency for different source impedances. at 3V and 5V
respectively.
Figure 15. THD vs Analog Input Frequency for various source
Impedances for VDD = 5V
Figure 14. THD vs Analog Input Frequency for various source
Impedances for VDD = 3V
Rev. PrB | Page 17 of 25
AD7991/AD7995/AD7999
Preliminary Technical Data
INTERNAL REGISTER STRUCTURE
CONFIGURATION REGISTER
The configuration register is an 8-bit write only register that is used to set the operating modes of the AD7991/AD7995/AD7995. The bit
functions are outlined in Table 9. A single-byte write is necessary when writing to the configuration register. D7 is the MSB. When the
master writes to the AD7991/AD799/AD7999, the first byte is written to the status register.
Table 9. Configuration Register Bit Function Descriptions and * shows the default Settings at Power-Up
D7
CH3
1*
D6
CH2
1*
D5
CH1
1
D4
CH0
1*
D3
REF_SEL
0*
D2
FLTR
0*
D1
Bit Trial Delay
0*
D0
Sample Delay
0*
Table 10. Bit Function Descriptions
Bit
D7–D4
Mnemonic
CH3–CH0
D3
REF_SEL
D2
FLTR
D1
Bit Trial
Delay
Sample
Delay
D0
Comment
These four channel address bits select the analog input channel(s) to be converted. A 1 in any of Bits D7 to D4
selects a channel for conversion. If more than one channel bit is set to 1, the AD7991/AD7995/AD7999 sequence
through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Table 11
shows how these four channel address bits are decoded. Prior to initiating a conversion, the channel(s) must be
selected in the configuration register.
This bit allows the user to select the supply voltage as the reference or use an external reference. If this bit is a 0
the supply is used as the reference and the device acts as a four channel input part, if it is set to a 1 an external
reference must be used and applied to the Vin3/VREF pin, in this case the device acts as a three channel input
part.
The value written to this bit of the control register determines whether the filtering on SDA and SCL is enabled or
is to be bypassed. If this bit is a 0, then the filtering is enabled; if it is a 1, the filtering is bypassed.
See paragraph below entitled: SAMPLE DELAY AND BIT TRIAL DELAY
See paragraph below entitled: SAMPLE DELAY AND BIT TRIAL DELAY
Table 11. Channel Selection
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Analog Input Channel
No channel selected.
Convert on VIN0.
Convert on VIN1.
Sequence between VIN0 and VIN1.
Convert on VIN2.
Sequence between VIN0 and VIN2.
Sequence between VIN1 and VIN2.
Sequence between VIN0, VIN1, and VIN2.
Convert on VIN3.
Sequence between VIN0 and VIN3.
Sequence between VIN1 and VIN3.
Sequence between VIN0, VIN1, and VIN3.
Sequence between VIN2 and VIN3.
Sequence between VIN0, VIN2, and VIN3.
Sequence between VIN1, VIN2, and VIN3.
Sequence between VIN0, VIN1, VIN2, and VIN3.
Comments
The AD7991/AD7995/AD7999 converts on the selected
channel in the sequence in ascending order, starting
with the lowest channel in the sequence.
SAMPLE DELAY AND BIT TRIAL DELAY
It is recommended that no I2C bus activity occur when a conversion is taking place. However, if this is not always possible, then in order
to maintain the performance of the ADC, Bits D0 and D1 in the configuration register are used to delay critical sample intervals and bit
trials from occurring while there is activity on the I2C bus. This results in a quiet period for each bit decision. In certain cases where there
Rev.PrB | Page 18 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
is excessive activity on the interface lines, this may have the effect of increasing the overall conversion time. However, if bit trial delays
extend longer than 1 µs, the conversion terminates.
When Bits D0 and D1 are both 0, the bit trial and sample interval delaying mechanism is implemented. The default setting of D0 and D1
is 0. To turn off both delay mechanisms, set D0 and D1 to 1.
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit read-only register that stores the conversion result from the ADC in straight binary format. A 2byte read is necessary to read data from this register. Table 12 shows the contents of the first byte to be read, from
AD7991/AD7995/AD7999 and Table 13 shows the contents of the second byte to be read.
Table 12. Conversion Value Register (First Read)
D15
Leading Zero
D14
Leading Zero
D13
CHID1
D12
CHID0
D11
MSB
D10
B10
D9
B9
D8
B8
Table 13. Conversion Value Register (Second Read)
D7
B7
D6
B6
D5
B5
D4
B4
D3
B3 /0
D2
B2 /0
D1
B1/0
D0
B0/0
The AD7991/AD7995/AD7999 conversion result consists of 2 leading zeros, two channel identifier bits, and the 12-/10-/8- bit data result.
For the AD7995, the 2 LSB (D1 and D0) of the second read contain two trailing 0s. For the AD7999, the 4 LSB (D3, D2, D1 and D0) of
the second read contain 4 trailing zeros
Rev. PrB | Page 19 of 25
AD7991/AD7995/AD7999
Preliminary Technical Data
SERIAL INTERFACE
Control of the AD7991/AD7995/AD7999 is carried out via the
I2C-compatible serial bus. The AD7991/AD7995/AD7999 is
connected to this bus as a slave device under the control of a
master device, such as the processor.
SERIAL BUS ADDRESS
Like all I2C-compatible devices, the AD7991/AD7995/AD7999
has a 7-bit serial address. The devices comes in two versions,
the AD7991/AD7995/AD7999-0 and the
AD7991/AD7995/AD7999-1. Each version has a different
address. See Table 8. By giving different addresses for the two
versions, up to 2 AD7991/AD7995/AD7999 devices can be
connected to a single serial bus.
The serial bus protocol operates as follows:
The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA, while the serial clock line, SCL, remains high.
This indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the START
condition and shift in the next eight bits, consisting of a 7-bit
address (MSB first) plus an R/W bit that determines the
direction of the data transfer—that is, whether data is written to
or read from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit from
the receiver of data. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, because a low-to-high transition when
the clock is high may be interpreted as a STOP signal.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a STOP condition. In
read mode, the master device pulls the data line high during the
low period before the ninth clock pulse. This is known as no
acknowledge. The master then takes the data line low during
the low period before the 10th clock pulse, then high during the
10th clock pulse to assert a STOP condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit. All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the R/W
bit is a 0, the master writes to the slave device. If the R/W bit is
a 1, the master reads from the slave device.
Rev.PrB | Page 20 of 25
Preliminary Technical Data
AD7991/AD7995/AD7999
WRITING TO THE AD7991/AD7995/AD7999
WRITING A SINGLE BYTE OF DATA TO THE
CONFIGURATION REGISTER
This part can be used in read-only mode if the user wishes to
use all 4 channels sequentially as the default on the configure
register allows. However, the user must write to the
configuration register of the part AD7991/AD7995/AD7999 if
they want to change from the default settings on the
configuration register.
1
The configuration register is an 8-bit register, so only one byte
of data can be written. Writing a single byte of data to this
register consists of the serial bus write address, followed by the
data byte written to the configuration register. See Figure 16
below.
9
1
9
SCL
SDA
0
1
0
1
0
0
START BY
MASTER
A0
D7
R/9
D6
D5
D4
D3
D2
D1
ACK. BY
ADC
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
AD7992
CONTROL REGISTER BYTE
Figure 16.Writing to the AD7991/AD7995/AD7999 Configuration Register
Rev. PrB | Page 21 of 25
D0
STOP
AD7991/AD7995/AD7999
Preliminary Technical Data
READING FROM THE AD7991/AD7995/AD7999
Reading data from the conversion result register is a 2-byte
operation, as shown in Figure 17. Since this register is the only
one that a user can read, a read operation is always at least two
bytes.
After the master has addressed the AD7991/AD7995/AD7999,
the part begins to power up on the 9th SCLK falling edge. After
about 0.5us, the input is sampled and a conversion begins. This
is done in parallel to the read operation and should not affect
the read operation. The master reads back 2 bytes of data. On
the 9th SCLK falling edge of the second byte, if the master sends
an ACK, this means that the master desires to keep reading
back more conversion results, the AD7991/AD7995/AD7999
powers up and performs a second conversion. If the master
sends a NO ACK the AD7991/AD7995/AD7999 doesn’t power
up on the 9th falling edge of SCLK of the second byte. If a
further conversion is required the part will convert on the next
channel, that is the next channel as selected in the configuration
register. See table 10 for Channel selection.
Once the AD7991/AD7995/AD7999 has received a read address
any number of reads can be performed from the conversion
result register.
Following a start condition, the master writes the 7 bit address
of the AD7991/AD7995/AD7999, followed by the R/W set to 1.
The AD7991/AD7995/AD7999 acknowledges by pulling low
the SDA line (A). It then outputs on the I2C bus the conversion
result, proceeded by 4 status bits. The status bits are 2 leading
zeros, then the channel identifier bits. For the AD7995 there are
two trailing zeros and for the AD7999 there are four trailing
zeros.
1
If the master send a NO ACK on the 9th SCLK falling edge of
the 2nd byte then the conversion is finished and no further
conversion is preformed.
9
1
9
SCL
SDA
0
1
0
1
0
0
A0
R/9
START BY
MASTER
0
0
ACK. BY
ADC
D11
D10
D9
D8
ACK. BY
MASTER
CH ID1 CH ID0
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM ADC
FRAME 1
SERIAL BUS ADDRESS BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK. BY
MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM ADC
Figure 17. Reading Two Bytes of Data from the Conversion Result Register
Rev.PrB | Page 22 of 25
STOP BY
MASTER
Preliminary Technical Data
AD7991/AD7995/AD7999
PLACING THE AD7991/AD7995/AD7999
INTO HIGH SPEED MODE.
High speed mode communication commences after the master
addresses all devices connected to the bus with the master code,
00001XXX, to indicate that a high speed mode transfer is to
begin. No device connected to the bus is allowed to
acknowledge the high speed master code; therefore, the code is
followed
by a not-acknowledge (see Figure 18). The master must then
issue a repeated start followed by the device address with a R/W
bit. The selected device then acknowledges its address.
All devices continue to operate in high speed mode until the
master issues a STOP condition. When the STOP condition is
issued, the devices all return to fast mode.
HIGH-SPEED MODE
FAST MODE
1
9
1
9
SCL
SDA
0
0
0
0
1
X
X
X
0
NACK.
START BY
MASTER
1
0
1
0
0
A0
Sr
HS-MODE MASTER CODE
ACK. BY
ADC
SERIAL BUS ADDRESS BYTE
Figure 18. Placing the Part into High Speed Mode
Rev. PrB | Page 23 of 25
AD7991/AD7995/AD7999
Preliminary Technical Data
MODE OF OPERATION
The AD7991/AD7995/AD7999 powers up in shut down mode.
Once the master addresses the AD7991/AD7995/AD7999 with
the correct I2C address the ADC will acknowledge. During this
acknowledge the AD7991/AD7995/AD7999 will power up and
start a conversion.
of the conversion result. For the AD7991 this second byte will
contain the lower 8 bits of conversion data. For the AD7995 this
second byte will contain 6 bits of conversion data plus 2 trailing
zeros. For the AD7999 this second byte will contain 4 bits of
conversion data and 4 trailing zeros.
During this wake up time the AD7991/AD7995/AD7999 exits
shut down mode and begins to acquire the analog input. The
channels being converted will depend on the status of the
channel bits in the Control register.
The master will then send a NAK to the
AD7991/AD7995/AD7999 if no further reads are required. If
the master does not issue a NAK and sends an ACK to the
AD7991/AD7995/AD7999 the ADC will once again power up
and complete a conversion. If more than one channel bit has
been set in the control register then this conversion will be
preformed on the second channel in the selected sequence. If
only one channel was selected the ADC will convert again on
the selected channel.
After the read address acknowledge the ADC will output two
bytes of data. The first byte will contain 4 status bits and the 4
MSBs of the conversion result. The status bits will contain 2
leading zeros and 2 channel identifier bits. After this first byte
the AD7991/AD7995/AD7999 will then output the second byte
1
9
9
9 1
SCL
SDA
Sr
7-BIT ADDRESS
R
A
ACK BY
ADC
FIRST DATA BYTE (MSBs)
A
SECOND DATA BYTE (LSBs)
ACK BY
MASTER
Figure 19. Mode Of Operation
Rev.PrB | Page 24 of 25
)
Sr/
P
NACK BY
MASTER
Preliminary Technical Data
AD7991/AD7995/AD7999
OUTLINE DIMENSIONS
2.90 BSC
8
7
6
5
1
2
3
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.30
1.15
0.90
1.95
BSC
1.45 MAX
0.15 MAX
0.38
0.22
SEATING
PLANE
0.22
0.08
8°
4°
0°
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 20.8-Lead Small Outline Transistor Package (SOT-23)
(RJ-8)
Dimensions shown in millimeter
ORDERING GUIDE
Model
AD7991BRJZ-11
AD7991BRJZ-01
AD7991YRJZ-11
AD7991YRJZ-01
AD7995YRJZ-11
AD7995YRJZ-01
AD7999YRJZ-11
AD7999YRJZ-01
1
Temperature Range
-40°C to 85° C
-40°C to 85° C
-40°C to 125° C
-40°C to 125° C
-40°C to 125° C
-40°C to 125° C
-40°C to 125° C
-40°C to 125° C
Z = Pb-free part.
©2006 Rev. PrB | Page 25 of 25
Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their
respective owners.
PR06461-0-10/06(PrB)
Package Description
8-LEAD SOT-23
8-LEAD SOT-23
8-LEAD SOT-23
8-LEAD SOT-23
8-LEAD SOT-23
8-LEAD SOT-23
8-LEAD SOT-23
8-LEAD SOT-23
Package Option
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