NSC DM74LS109AM Dual positive-edge-triggered j-k flip-flops with preset, clear, and complementary output Datasheet

54LS109/DM54LS109A/DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and
K data is accepted by the flip-flop on the rising edge of the
clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge of
the clock. The data on the J and K inputs may be changed
while the clock is high or low as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Features
Y
Alternate Military/Aerospace device (54LS109) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications
Connection Diagram
Dual-In-Line Package
TL/F/6368 – 1
Order Number 54LS109DMQB, 54LS109FMQB, DM54LS109AJ,
DM54LS109AW, DM74LS109AM or DM74LS109AN
See NS Package Number J16A, M16A, N16E or W16A
Function Table
Inputs
Outputs
PR
CLR
CLK
J
K
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
L
H
L
H
X
X
X
X
L
L
H
H
X
H
L
L
H
H*
H*
L
H
Toggle
Q0
Q0
H
L
Q0
Q0
u
u
u
u
L
C1995 National Semiconductor Corporation
TL/F/6368
Q
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
u e Rising Edge of Pulse
* e This configuration is nonstable; that is, it will not persist when preset
and/or clear inputs return to their inactive (high) state.
Q0 e The output logic level of Q before the indicated input conditions were
established.
Toggle e Each output changes to the complement of its previous level on
each active transition of the clock pulse.
RRD-B30M105/Printed in U. S. A.
54LS109/DM54LS109A/DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs
June 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
DM54LS and 54LS
DM74LS
0§ C to a 70§ C
Storage Temperature Range
b 65§ C to a 150§ C
Recommended Operating Conditions
Symbol
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
fCLK
Clock Frequency (Note 2)
fCLK
tW
tW
tSU
tSU
DM54LS109A
Parameter
DM74LS109A
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
0.8
V
b 0.4
mA
4
8
mA
0
25
MHz
0
20
MHz
Clock Frequency (Note 3)
0
20
Pulse Width
(Note 2)
Clock High
18
18
Preset Low
15
15
Clear Low
15
15
Setup Time
(Notes 1 & 3)
Clock High
25
25
Preset Low
20
20
Clear Low
20
20
Data High
30u
30u
Data Low
20u
20u
Data High
35u
35u
Data Low
25u
25u
tH
Hold Time (Note 4)
0u
TA
Free Air Operating Temperature
b 55
Note 1: The symbol (
V
0.7
25
Setup Time
(Notes 1 & 2)
ns
ns
ns
ns
0u
125
u) indicates the rising edge of the clock pulse is used for reference.
Note 2: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
Note 3: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
Note 4: TA e 25§ C and VCC e 5V.
2
V
b 0.4
0
Pulse Width
(Note 3)
Units
Min
0
ns
70
§C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
b 1.5
V
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High Level Output
Voltage
VCC e Min, IOH e Max
VIL e Max, VIH e Min
Low Level Output
Voltage
VCC e Min, IOL e Max
VIL e Max, VIH e Min
DM54
0.25
DM74
0.35
0.5
IOL e 4 mA, VCC e Min
DM74
0.25
0.4
VCC e Max
VI e 7V
J, K
VOL
II
IIH
Input Current @ Max
Input Voltage
High Level Input
Current
VCC e Max
VI e 2.7V
V
0.4
0.1
Clock
0.1
Preset
0.2
Clear
0.2
J,K
20
Clock
20
Preset
40
Clear
IIL
Low Level Input
Current
VCC e Max
VI e 0.4V
ICC
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
VCC e Max (Note 3)
mA
mA
40
J, K
b 0.4
Clock
b 0.4
Preset
b 0.8
Clear
IOS
V
mA
b 0.8
DM54
b 20
b 100
DM74
b 20
b 100
4
8
mA
mA
Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL e 2 kX
From (Input)
To (Output)
CL e 15 pF
Min
Max
CL e 50 pF
Min
Units
Max
fMAX
Maximum Clock
Frequency
tPLH
Propagation Delay Time
Low to High Level Output
Clock to
Q or Q
25
35
ns
tPHL
Propagation Delay Time
High to Low Level Output
Clock to
Q or Q
30
35
ns
tPLH
Propagation Delay Time
Low to High Level Output
Clear
to Q
25
35
ns
tPHL
Propagation Delay Time
High to Low Level Output
Clear
to Q
30
35
ns
tPLH
Propagation Delay Time
Low to High Level Output
Preset
to Q
25
35
ns
tPHL
Propagation Delay Time
High to Low Level Output
Preset
to Q
30
35
ns
25
20
MHz
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2.25V and 2.125V for DM54 and
DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test
equipment.
Note 3: ICC is measured with all outputs open, with CLOCK grounded after setting the Q and Q outputs high in turn.
3
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54LS109DMQB or DM54LS109AJ
NS Package Number J16A
4
Physical Dimensions inches (millimeters) (Continued)
16-Lead Small Outline Molded Package (M)
Order Number DM74LS109AM
NS Package Number M16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS109AN
NS Package Number N16E
5
54LS109/DM54LS109A/DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package
Order Number 54LS109FMQB or DM54LS109AW
NS Package Number W16A
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