Cypress CY62147VLL-70ZI 4m (256k x 16) static ram Datasheet

CY62147V MoBL®
4M (256K x 16) Static RAM
Features
•
•
•
•
•
•
•
deselected (CE HIGH) or when CE is LOW and both BLE and
BHE are HIGH. The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Wide voltage range: 2.7V–3.6V
Ultra-low active, standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a standard 44-pin TSOP Type II
(forward pinout) package
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Functional Description[1]
The CY62147V is a high-performance CMOS static RAM
organized as 256K words by 16 bits. These devices feature
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL®) in
portable applications such as cellular telephones. The devices
also have an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
2048 x 2048
I/O0 – I/O7
I/O8 – I/O15
BHE
WE
CE
OE
BLE
A17
A13
A14
A15
A16
A11
A12
COLUMN DECODER
CE
Power-down
Circuit
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05050 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 28, 2002
CY62147V MoBL®
Pin Configurations
TSOP II (Forward)
A4
Top View
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
Range
Ambient
Temperature
VCC
Industrial
–40°C to +85°C
2.7V to 3.6V
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62147VLL
VCC(min.) VCC(typ.)
2.7
3.0
[3]
VCC(max.)
Speed
(ns)
3.6
70
Standby ISB2, (µA)
Operating ICC, (mA)
Typ.[3]
7
Maximum
Typ.[3]
Maximum
15
2
20
Electrical Characteristics Over the Operating Range
CY62147V-70
Parameter
Description
Test Conditions
Min.
Typ.[3]
Max.
2.4
Unit
VOH
Output HIGH Voltage
IOH = –1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
IIX
Input Load Current
GND < VI < VCC
–1
±1
+1
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
+1
µA
ICC
VCC Operating Supply IOUT = 0 mA, f = fMAX = 1/tRC, CMOS
Current
Levels
7
15
mA
2
mA
VCC = 3.6V
2.2
VCC = 2.7V
–0.5
VCC = 3.6V
V
IOUT = 0 mA, f = 1 MHz, CMOS Levels
1
Notes:
2. VIL(min.) = –2.0V for pulse durations less than 20 ns.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05050 Rev. *A
0.4
V
VCC +
0.5V
V
Page 2 of 9
CY62147V MoBL®
Electrical Characteristics Over the Operating Range (continued)
CY62147V-70
Parameter
Description
Test Conditions
Min.
ISB1
Automatic CE
CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN
Power-down Current— < 0.3V, f = fMAX
CMOS Inputs
ISB2
Automatic CE
CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN VCC = 3.6V
Power-down Current— < 0.3V, f = 0
CMOS Inputs
Typ.[3]
Max.
Unit
2
20
µA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
6
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)[4]
ΘJC
Thermal Resistance
(Junction to Case)[4]
Test Conditions
BGA
TSOPII
Units
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
55
60
°C/W
16
22
°C/W
AC Test Loads and Waveforms
R1
R1
VCC
ALL INPUT PULSES
VCC
OUTPUT
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
VCC Typ
10%
5 pF
(a)
GND
Rise TIme: 1 V/ns
R2
INCLUDING
JIG AND
SCOPE
Fall Time: 1 V/ns
(b)
Equivalent to:
90%
10%
90%
(c)
THÉVENIN EQUIVALENT
RTH
OUTPUT
Parameter
VTH
3.0V
Unit
R1
1105
Ω
R2
1550
Ω
RTH
645
Ω
VTH
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.[3]
1.0
Max.
Unit
3.6
V
10
µA
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[4]
Chip Deselect to Data
Retention Time
0
ns
tR[5]
Operation Recovery Time
70
ns
VCC = 1.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN <
0.3V; No input may exceed VCC + 0.3V
1
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05050 Rev. *A
Page 3 of 9
CY62147V MoBL®
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min.)
VCC(min.)
VDR > 1.0 V
tR
tCDR
CE
Switching Characteristics Over the Operating Range[6]
70 ns
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
25
ns
Low-Z[7, 9]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[9]
Low-Z[7]
tLZCE
CE LOW to
tHZCE
CE HIGH to High-Z[7, 9]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
tDBE
BHE / BLE LOW to Data Valid
tLZBE[8]
BHE / BLE LOW to Low-Z
tHZBE
BHE / BLE HIGH to High-Z
70
ns
70
10
ns
ns
5
ns
20
10
ns
ns
20
0
ns
ns
70
ns
70
ns
5
ns
20
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
40
ns
tBW
BHE / BLE Pulse Width
60
ns
tSD
Data Set-up to Write End
30
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[7, 9]
tLZWE
WE HIGH to
Low-Z[7]
ns
25
10
ns
ns
Notes:
5. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable at VCC(min.) >10 µs.
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. If both byte enables are toggled together this value is 10ns
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05050 Rev. *A
Page 4 of 9
CY62147V MoBL®
Switching Waveforms
Read Cycle No. 1 [12, 13]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [13, 14]
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
BHE/BLE
tLZOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
[10, 15, 16]
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05050 Rev. *A
Page 5 of 9
CY62147V MoBL®
Switching Waveforms (continued)
[8, 15, 16]
Write Cycle No. 2 (CE Controlled)
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tBW
BHE/BLE
tPWE
WE
tSD
DATA I/O
tHD
DATAIN VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
[11, 16]
tWC
ADDRESS
CE
tAW
tBW
BHE/BLE
WE
tHA
tSA
tSD
DATA I/O
NOTE 17
tHZWE
tHD
DATAIN VALID
tLZWE
Notes:
15. Data I/O is high-impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05050 Rev. *A
Page 6 of 9
CY62147V MoBL®
Switching Waveforms (continued)
[17]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
tWC
ADDRESS
CE
tAW
tHA
tBW
BHE/BLE
tSA
WE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tLZWE
tHZWE
Typical DC and AC Characteristics
Normalized Operating Current
vs. Supply Voltage
1.4
Standby Current vs. Supply Voltage
45
MoBL
40
1.2
MoBL
35
ISB (µA)
ICC
1.0
0.8
0.6
30
20
15
0.4
10
0.2
5
0.0
2.7
3.7
2.8
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
2.7
3.7
2.8
SUPPLY VOLTAGE (V)
80
MoBL
70
60
TAA (ns)
50
40
30
20
10
2.8
2.7
3.7
SUPPLY VOLTAGE (V)
Document #: 38-05050 Rev. *A
Page 7 of 9
CY62147V MoBL®
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
X
X
H
H
High-Z
Deselect/Power-down
Standby (ISB)
L
H
L
L
L
Data Out (I/OO–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Deselect/Output Disabled
Active (ICC)
L
H
H
H
L
High-Z
Deselect/Output Disabled
Active (ICC)
L
H
H
L
H
High-Z
Deselect/Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/OO–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/OO–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
70
Ordering Code
CY62147VLL-70ZI
Package
Name
Z44
Package Type
44-pin TSOP II
Operating
Range
Industrial
Package Diagram
44-Pin TSOP II Z44
51-85087-A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05050 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62147V MoBL®
Document Title: CY62147V MoBL® 4M (256K x 16) Static RAM
Document Number: 38-05050
REV.
ECN NO.
Issue Date
Orig. of
Change
**
109958
12/16/01
SZV
Changed from Spec number: 38-00757 to 38-05050
A
116514
09/04/02
GBI
Added footnote 1.
Deleted fBGA package (replacement fBGA package is available in
CY62147CV30).
Document #: 38-05050 Rev. *A
Description of Change
Page 9 of 9
Similar pages