TMP1962F10AXBG 32-Bit RISC Microprocessor TX19 Family TMP1962F10AXBG 1. Features The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction set of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000ATM architecture. Additionally, the TX19 supports the MIPS16 Application-Specific Extensions (ASE) for improved code density. The TMP1962 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1962 is suitable for low-voltage and low-power applications. Features of the TMP1962 include the following: (1) TX19 core processor 1) 2) Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed • The 16-bit ISA is object-code compatible with the code-efficient MIPS16 ASE. • The 32-bit ISA is object-code compatible with the high-performance TX39 family. High performance combined with low power consumption — High performance • Single clock cycle execution for most instructions • 3-operand computational instructions for high instruction throughput • 5-stage pipeline • On-chip high-speed memory • DSP function: Executes 32-bit x 32-bit multiplier operations in a single clock cycle. 030619EBP • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. 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TMP1962F-1 TMP1962F10AXBG — Low power consumption 3) • Optimized design using a low-power cell library • Programmable standby modes in which processor clocks are stopped Fast interrupt response suitable for real-time control • Distinct starting locations for each interrupt service routine • Automatically generated vectors for each interrupt source • Automatic updates of the interrupt mask level (2) On-chip ROM/RAM Product On-chip ROM On-chip RAM TMP1962C10BXBG 1 Mbyte 40 kbyte TMP1962F10AXBG 1 Mbyte (Flash) 40 Kbyte Collection function on ROM (8 words x 8 blocks) (3) External memory expansion • 16-Mbyte off-chip address space for code and data • External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (Separate bus/multiplex bus) (4) 8-channel DMA controller • Interrupt- or software-triggered • DMA transfers between on-chip or external memory and I/O module (5) 12-channel 8-bit timer • 8-bit/16-bit/24-bit/32-bit interval timer mode • 8-bit PWM mode • 8-bit PPG mode (6) 4-channel 16-bit timer • 16-bit interval timer mode • 16-bit event counter mode • 16-bit PPG output • Input capture function • 2-channel dual input counter function (7) 32-bit input capture • 8-channel 32-bit input capture register • 8-channel 32-bit compare register • 1-channel 32-bit time base timer (8) 7-channel general-purpose serial interface Either UART mode or synchronous transfer mode can be selected. (9) 1-channel serial bus interface Either I2C bus mode or clock-synchronous mode can be selected. (10) 24-channel 10-bit A/D converter (with internal sample/hold) TMP1962F-2 TMP1962F10AXBG • External trigger start function • Fixed channel/scan mode • Single/repeat mode • Timer monitor function (11) Watchdog timer (12) 4-channel chip select/wait controller (13) Interrupt sources • 4 CPU interrupts: software interrupt instruction • 55 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt • 25 external interrupts: 7 priority levels, with the exception of the NMI interrupt 1 used for an interrupt source and 14 used for KWUP (14) 202-pin input/output ports (15) Four standby modes • IDLE (HALT, DOZE), STOP (16) Clock generator • On-chip PLL (x3) • Clock gear: Divides the operating speed of the CPU by 1/2, 1/4 or 1/8 TMP1962F-3 TMP1962F10AXBG (17) Endian ......... Bi-Endian Big-endian Higher address 31 24 23 16 15 8 7 0 Word address 8 9 10 11 8 4 5 6 7 4 0 1 2 3 0 Lower address Byte 0 is the most significant byte (MSB) (bits 31-24) The address of a word data item is the address of its MSB (byte 0). Little-endian Higher address 31 24 23 16 15 8 7 0 Word address 11 10 9 8 8 7 6 5 4 4 3 2 1 0 0 Lower address Byte 0 is the least significant byte (LSB) (bits 7-0) The address of a word data item is the address of its LSB (byte 0). (18) Operating frequency 40.5 MHz (Vcc = 2.2 V to 2.7 V) (19) Package P-FBGA281 (13 x 13 x 0.65 mm pitch) TMP1962F-4 TMP1962F10AXBG TX19 Processor Core TX19 CPU MAC DSU 1 Mbyte Flash ROM 40 Kbyte RAM ROM correction DMAC (8ch) CG INTC EBIF I/O Bus I/F 8-bit TMRA 0/1 to A/B (12ch) PORT0 to PORT6 (Shared with External Bus I/F) 16-bit TMRB 0 to 3 (4ch) PORT7 to PORT9 (Shared with ADC Input) 32-bit TMRC TBT (1ch) 32-bit TMRC Input Capture 0 to 7 (8ch) PORTA to PORTL, PORTN (Shared with Function Pins) 32-bit TMRC Compare 0 to 7 (8ch) 10-bit ADC (24ch) PORTM, PORTO to PORTP (General Port) SIO 0 to 6 (7ch) KWUP 0 to D (14ch) 2 IC (1ch) WDT Figure 1.1 TMP1962F10AXBG Block Diagram TMP1962F-5 TMP1962F10AXBG 2. Pin Assignment This section contains pin assignments for the TMP1962F10AXBG as well as brief description of the TMP1962F10AXBG input and output signals. 2.1 Pin Assignment The following illustrates the TMP1962F10AXBG pin assignment. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 F1 F2 F3 F4 F5 F7 F8 F9 F10 F11 F12 F14 F15 F16 F17 F18 G1 G2 G3 G4 G5 G6 G13 G14 G15 G16 G17 G18 H1 H2 H3 H4 H5 H6 H13 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J6 J13 J14 J15 J16 J17 J18 K1 K2 K3 K4 K5 K6 K13 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L6 L13 L14 L15 L16 L17 L18 M1 M2 M3 M4 M5 M6 M13 M14 M15 M16 M17 M18 N1 N2 N3 N4 N5 N14 N15 N16 N17 N18 P1 P2 P3 P4 P5 R1 R2 R3 R4 T1 T2 T3 U1 U2 V2 N7 N8 N9 N10 N11 N12 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 Figure 2.1 Pin Assignment (P-FBGA281) The following provides a pin cross reference by pin number. Table 2.1 Pin Cross Reference by Pin Number (1/2) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name A1 NC A13 PK1/KEY1 B8 P75/AIN5 C2 PCST3 (DSU) C14 PK6/KEY6 A2 VREFL A14 PI1/INT1 B9 PL0/TA4IN C3 P92/AIN18 C15 PI5/INT9 A3 P90/AIN16 A15 PI3/INT3 B10 PL3/TAAIN C4 P95/AIN21 C16 TCK (JTAG) A4 P93/AIN19 A16 PI6/INTA B11 PM1 C5 P82/AIN10 C17 CVCC2 A5 P80/AIN8 A17 X2 B12 PM4 C6 P85/AIN13 C18 XT2 A6 P83/AIN11 B1 AVCC31 B13 PK2/KEY2 C7 P72/AIN2 D1 SDAO/TPC (DSU) A7 P70/AIN0 B2 VREFH B14 PI2/INT2 C8 AVSS D2 PCST2 (DSU) A8 P74/AIN4 B3 P91/AIN17 B15 PI4/INT4 C9 PL1/TA6IN D3 SDI/ DINT (DSU) A9 NC B4 P94/AIN20 B16 PI7 C10 PL4/TB0IN0 D4 DVCC2 A10 PL2/TA8IN B5 P81/AIN9 B17 CVSS C11 PM2 D5 P96/AIN22 A11 PM0 B6 P84/AIN12 B18 X1 C12 PM5 D6 P86/AIN14 A12 PK0/KEY0 B7 P71/AIN1 C1 PCST0 (DSU) C13 PK3/KEY3 D7 P73/AIN3 TMP1962F-6 TMP1962F10AXBG Table 2.1 Pin Cross Reference by Pin Number (2/2) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name D8 DVCC2 F18 P44/SCOUT D9 DVSS G1 RESET K14 P12/D10/AD10 N18 DVSS T8 PD4/TXD4 K15 P13/D11/AD11 P1 PP0 T9 D10 PL5/TB0IN1 G2 TEST5 K16 PC0/TXD0 P14/D12/AD12 P2 PB2/TB2IN0/INT5 T10 PC3/TXD1 D11 PM3 G3 FVCC2 K17 DVCC33 P3 PB3/TB2IN1/INT6 T11 PH4/TCOUT4 D12 PM6 G4 FVSS K18 P15/D13/AD13 P4 PB4/TB2OUT T12 PE2/SCLK5/ CTS5 D13 PK4/KEY4 G5 PJ0/INT0 L1 FVCC3 P5 PB5/TB3IN0/INT7 T13 PE5/KEYB D14 PK7/KEY7 G6 BW0 L2 PO1 P6 PG5/TC5IN T14 P53/A3 D15 DVCC34 G13 TRST L3 PO2 P7 PG7/TC7IN T15 P56/A6 D16 TDI (JTAG) G14 CAP1 L4 PO3 P8 PD6/SCLK4/ CTS4 T16 P62/A10 D17 TDO (JTAG) G15 P41/ CS1 L5 PO4 P9 PC2/SCLK0/ CTS0 T17 P65/A13 D18 XT1 G16 P37/ALE L6 PO7 P10 PC5/SCLK1/ CTS1 T18 P20/A16/A0 E1 DCLK (DSU) G17 P35/ BUSAK L13 TEST3 P11 PH6/TCOUT6 U1 PA0/TA0IN E2 PCST1 (DSU) G18 FVCC2 L14 P06/D6/AD6 P12 NC U2 PA3/TA3OUT PA6/TA9OUT E3 DBGE H1 NMI L15 FVCC2 P13 P50/A0 U3 E4 PJ3/INTLV H2 DVCC31 L16 P07/D7/AD7 P14 P51/A1 U4 PF1/SI/SCL E5 PJ4/ENDIAN H3 PN7 L17 P10/D8/AD8 P15 P54/A4 U5 PF5/ DREQ3 E6 P97/AIN23 H4 BW1 L18 P11/D9/AD9 P16 P23/A19/A3 U6 PG2/TC2IN E7 P87/AIN15 H5 PLLOFF M1 PO0 P17 P24/A20/A4 U7 PD2/RXD3 E8 P76/AIN6 H6 TEST1 M2 PP5 P18 P25/A21/A5 U8 DVCC32 E9 P77/AIN7 H13 TEST2 M3 PP6 R1 PB0/TB0OUT U9 PC7/RXD2 E10 PL6/TB1IN0 H14 P31/ WR M4 PP7 R2 PB1/TB1OUT U10 PH1/TCOUT1 E11 PL7/TB1IN1 H15 P32/ HWR M5 PB7/TB3OUT R3 PF3/ DREQ2 U11 PH3/TCOUT3 E12 PM7 H16 P33/WAIT/RDY M6 DVCC32 R4 PF4/ DACK 2 U12 PE1/RXD5 E13 PK5/KEY5 H17 P30/ RD M13 TEST4 R5 PF7/TBTIN U13 PE4/KEYA E14 NC H18 P40/ CS0 M14 P02/D2/AD2 R6 PG4/TC4IN U14 DVCC32 E15 TMS (JTAG) J1 PN2/SCLK6/ CTS6 M15 FVSS R7 PG6/TC6IN U15 P57/A7 E16 CVCCH J2 PN3 M16 P03/D3/AD3 R8 PD5/RXD4 U16 P63/A11 E17 NC J3 PN4 M17 P04/D4/AD4 R9 PC1/RXD0 U17 P66/A14 E18 DVCC2 J4 PN5 M18 P05/D5/AD5 R10 PC4/RXD1 U18 DVCC33 F1 DVSS J5 PN6 N1 PP1 R11 PH5/TCOUT5 V2 PA2/TA2IN F2 DRESET J6 DVCC2 N2 PP2 R12 PH7/TCOUT7 V3 PA5/TA7OUT F3 SYSRDY J13 FVSS N3 PP3 R13 PE6/KEYC V4 PF0/SO/SDA F4 PJ1/BUSMD J14 P16/D14/AD14 N4 PP4 R14 P52/A2 V5 PG0/TC0IN F5 PJ2/ BOOT J15 DVSS N5 PB6/TB3IN1/INT8 R15 P55/A5 V6 PG1/TC1IN F7 AVSS J16 P17/D15/AD15 N7 DVSS R16 P61/A9 V7 PD1/TXD3 F8 AVSS J17 P36/ R / W N8 PD7/KEY8 R17 P21/A17/A1 V8 PD0/SCLK2/ CTS2 F9 AVCC32 J18 P34/ BUSRQ N9 DVCC2 R18 P22/A18/A2 V9 PC6/TXD2 F10 DVCC34 K1 PN0/TXD6 N10 DVSS T1 PA1/TA1OUT V10 PH0/TCOUT0 F11 PI0/ ADTRG K2 PN1/RXD6 N11 RSTPUP T2 PA4/TA5OUT V11 PH2/TCOUT2 F12 DVSS K3 PO5 N12 DVSS T3 PA7/TABOUT V12 PE0/TXD5 F14 CAP2 K4 PO6 N14 P26/A22/A6 T4 PF2/SCK V13 PE3/KEY9 F15 P42/ CS2 K5 FVSS N15 P27/A23/A7 T5 PF6/ DACK3 V14 PE7/KEYD F16 P43/ CS3 K6 DVSS N16 P00/D0/AD0 T6 PG3/TC3IN V15 P60/A8 F17 DVCC33 K13 TEST0 N17 P01/D1/AD1 T7 PD3/SCLK3/ CTS3 V16 P64/A12 V17 P67/A15 TMP1962F-7 TMP1962F10AXBG 2.2 Pin Usage Information Table 2.2 lists input and output pins of the TMP1962F10AXBG. Table 2.2 Pin Names and Function (1/6) Pin Name P00-P07 # of Pins Type 8 Function Input/Output Port 0: Individually programmable input or output D0-D7 Input/Output Data (Lower): Bits 0-7 of the data bus (separate bus mode) AD0-D7 Input/Output Address /Data (Lower): Bits 0-7 of the address/data bus (multiplex bus mode) Input/Output Port 1: Individually programmable input or output D8-D15 Input/Output Data (Upper): Bits 8-15 of the data bus (separate bus mode) AD8-AD15 Input/Output Address /Data (Upper): Bits 8-15 of the address/data bus (multiplex bus mode) A8-A15 Output Address: Bits 8-15 of the address bus (multiplex bus mode) P10-P17 P20-P27 8 Input/Output Port 2: Individually programmable input or output A16-A23 Output Address: Bit 15-23 of the address bus (separate bus mode) A0-A7 Output Address: Bit 0-7 of the address bus (multiplex bus mode) A16-A23 Output Address: Bit 16-23 of the address bus (multiplex bus mode) 1 Output Port 30: Output-only Output Read Strobe: Asserted during a read operation from an external memory device 1 Output Port 31: Output-only P30 8 RD P31 Output Write Strobe: Asserted during a write operation on D0-D7 1 Input/Output Port 32: Programmable as input or output (with internal pull-up register) Output Higher Write Strobe: Asserted during a write operation on D8-D15 1 Input/Output Port 33: Programmable as input or output (with internal pull-up resister) WAIT Input Wait: Causes the CPU to suspend external bus activity RDY Input Ready: Informs the CPU of bus ready condition Input/Output Port 34: Programmable as input or output (with internal pull-up resister) Input Bus Request: Asserted by an external bus master to request bus mastership Input/Output Port 35: Programmable as input or output (with internal pull-up resister) Output Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to BUSRQ . Input/Output Port 36: Programmable as input or output (with internal pull-up resister) Output Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle Input/Output Port 37: Programmable as input or output Output Address Latch Enable (This signal is driven out only when external memory is accessed.) Input/Output Port 40: Programmable as input or output (with internal pull-up resister) WR P32 HWR P33 P34 1 BUSRQ P35 1 BUSAK P36 1 R/ W P37 1 ALE P40 1 Output Chip Select 0: Asserted low to enable external devices at programmed addresses 1 Input/Output Port 41: Programmable as input or output (with internal pull-up resister) Output Chip Select 1: Asserted low to enable external devices at programmed addresses 1 Input/Output Port 42: Programmable as input or output (with internal pull-up resister) Output Chip Select 2: Asserted low to enable external devices at programmed addresses Input/Output Port 43: Programmable as input or output (with internal pull-up resister) Output Chip Select 3: Asserted low to enable external devices at programmed addresses Input/Output Port 44: Programmable as input or output Output System Clock Output: Drives out a clock signal at the frequency equal to or one half of CPU clock (high-speed or low-speed) Input/Output Port 5: Individually programmable as input or output Output Address: Address bus 0-7 (separate bus mode) Input/Output Port 6: Individually programmable as input or output Output Address: Address bus 8-15 (separate bus mode) CS0 P41 CS1 P42 CS2 P43 1 CS3 P44 1 SCOUT P50-P57 8 A0-A7 P60-P67 8 A8-A15 P70-P77 8 AN0-AN7 P80-P87 AN8-AN15 8 Input Port 7: Input-only Input Analog Input: Input to the on-chip A/D converter Input Port 8: Input-only Input Analog Input: Input to the on-chip A/D converter TMP1962F-8 TMP1962F10AXBG Table 2.2 Pin Names and Function (2/6) Pin Name P90-P97 # of Pins 8 AN16-AN23 PI0 1 ADTRG Type Input Function Port 9: Input-only Input Analog Input: Input to the on-chip A/D converter Input/Output Port I0: Programmable as input or output Input AD Trigger: Starts an A/D conversion Schmitt trigger input PI1 1 INT1 Input/Output Port I1: Programmable as input or output Input Interrupt Request 1: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt trigger input PI2 1 INT2 Input/Output Port I2: Programmable as input or output Input Interrupt Request 2: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt trigger input PI3 1 INT3 Input/Output Port I3: Programmable as input or output Input Interrupt Request 3: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt trigger input PI4 1 INT4 Input/Output Port I4: Programmable as input or output Input Interrupt Request 4: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt trigger input PI5 1 INT9 Input/Output Port I5: Programmable as input or output Input Interrupt Request 9: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt trigger input PI6 1 INTA Input/Output Port I6: Programmable as input or output Input Interrupt Request A: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt trigger input PI7 1 Input/Output Port I7: Programmable as input or output PA0 1 Input/Output Port A0: Programmable as input or output Input 8-Bit Timer 0 Input: Input to 8-bit Timer 0 1 Input/Output Port A1: Programmable as input or output Output 8-Bit Timer 01 Output: Output from either 8-bit Timer 0 or Timer 1 Input/Output Port A2: Programmable as input or output Input 8-Bit Timer 2 Input: Input to 8-bit Timer 2 Input/Output Port A3: Programmable as input or output Output 8-Bit Timer 23 Output: Output from either 8-bit Timer 2 or Timer 3 Input/Output Port A4: Programmable as input or output Output 8-Bit Timer 45 Output: Output from either 8-bit Timer 4 or Timer 5 Input/Output Port A5: Programmable as input or output Output 8-Bit Timer 67 Output: Output from either 8-bit Timer 6 or Timer 7 Input/Output Port A6: Programmable as input or output Input 8-Bit Timer 89 Output: Output from either 8-bit Timer 8 or Timer 9 Input/Output Port A7: Programmable as input or output Output 8-Bit Timer AB Output: Output from either 8-bit Timer A or Timer B Input/Output Port B0: Programmable as input or output Output 16-Bit Timer 0 Output: Output from 16-bit Timer 0 Input/Output Port B1: Programmable as input or output Output 16-Bit Timer 1 Output: Output from 16-bit Timer 1 Input/Output Port B2: Programmable as input or output TB2IN0 Input 16-Bit Timer 2 Input 0: Count/capture trigger input to 16-bit Timer 2 INT5 Input Interrupt Request 5: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive TA0IN PA1 TA1OUT PA2 1 TA2IN PA3 1 TA3OUT PA4 1 TA5OUT PA5 1 TA7OUT PA6 1 TA9OUT PA7 1 TABOUT PB0 1 TB0OUT PB1 1 TB1OUT PB2 1 TMP1962F-9 TMP1962F10AXBG Table 2.2 Pin Names and Function (3/6) Pin Name PB3 # of Pins Type 1 Input/Output TB2IN1 Input INT6 Input PB4 1 Input/Output 1 Input/Output TB2OUT PB5 Output TB3IN0 Input INT7 Input PB6 1 Input/Output TB3IN1 Input INT8 Input PB7 1 Input/Output 1 Input/Output TB3OUT PC0 Output TXD0 PC1 Output 1 RXD0 PC2 Input/Output Input 1 Input/Output SCLK0 Input CTS0 Input PC3 1 Input/Output 1 Input/Output TXD1 PC4 Output RXD1 PC5 Input 1 Input/Output SCLK1 Input CTS1 Input PC6 1 Input/Output 1 Input/Output 1 Input/Output TXD2 PC7 Output RXD2 PD0 Input SCLK2 Input CTS2 Input PD1 1 TXD3 PD2 Output 1 Input/Output 1 Input/Output RXD3 PD3 Input/Output Input SCLK3 Input CTS3 Input PD4 1 Input/Output 1 Input/Output TXD4 PD5 Output RXD4 PD6 Input 1 Input/Output SCLK4 Input CTS4 Input PD7 KEY8 1 Input/Output Input Function Port B3: Programmable as input or output 16-Bit Timer 2 Input 1: Capture trigger input to 16-bit Timer 2 Interrupt Request 6: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port B4: Programmable as input or output 16-Bit Timer 2 Output: Output from 16-bit Timer 2 Port B5: Programmable as input or output 16-Bit Timer 3 Input 0: Count/capture trigger input to 16-bit Timer 3 Interrupt Request 7: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port B6: Programmable as input or output 16-Bit Timer 3 Input 1: Capture trigger input to 16-bit Timer 3 Interrupt Request 8: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port B7: Programmable as input or output 16-Bit Timer 3 Output: Output from 16-bit Timer 3 Port C0: Programmable as input or output Serial Transmit Data 0: Programmable as a push-pull or open-drain output Port C1: Programmable as input or output Serial Receive Data 0 Port C2: Programmable as input or output Serial Clock Input/Output 0 Serial Clear-to-Send 0 Programmable as a push-pull or open-drain output Port C3: Programmable as input or output Serial Transmit Data 1: Programmable as a push-pull or open-drain output Port C4: Programmable as input or output Serial Receive Data 1 Port C5: Programmable as input or output Serial Clock Input/Output 1 Serial Clear-to-Send 1 Programmable as a push-pull or open-drain output Port C6: Programmable as input or output Serial Transmit Data 2: Programmable as a push-pull or open-drain output Port C7: Programmable as input or output Serial Receive Data 2 Port D0: Programmable as input or output Serial Clock Input/Output 2 Serial Clear-to-Send 2 Programmable as a push-pull or open-drain output Port D1: Programmable as input or output Serial Transmit Data 3: Programmable as a push-pull or open-drain output Port D2: Programmable as input or output Serial Receive Data 3 Port D3: Programmable as input or output Serial Clock Input/Output 3 Serial Clear-to-Send 3 Programmable as a push-pull or open-drain output Port D4: Programmable as input or output Serial Transmit Data 4: Programmable as a push-pull or open-drain output Port D5: Programmable as input or output Serial Receive Data 4 Port D6: Programmable as input or output Serial Clock Input/Output 4 Serial Clear-to-Send 4 Programmable as a push-pull or open-drain output Port D7: Programmable as input or output KEY on wake up Input 8: (dynamic pull-up selectable) (with internal pull-up register) Schmitt trigger input TMP1962F-10 TMP1962F10AXBG Table 2.2 Pin Names and Function (4/6) Pin Name PE0 # of Pins Type 1 Input/Output Port E0: Programmable as input or output Output Serial Transmit Data 5: Programmable as a push-pull or open-drain output Input/Output Port E1: Programmable as input or output TXD5 PE1 1 RXD5 Function Input Serial Receive Data 5 Input/Output Port E2: Programmable as input or output SCLK5 Input Serial Clock Input/Output 5 CTS5 Input Serial Clear-to-Send 5 PE2 1 Programmable as a push-pull or open-drain output PE3 1 KEY9 Input/Output Port E3: Programmable as input or output Input KEY on wake up Input 9: (dynamic pull-up selectable) (with internal pull-up register) Schmitt trigger input PE4 1 KEYA Input/Output Port E4: Programmable as input or output Input KEY on wake up Input A: (dynamic pull-up selectable) (with internal pull-up register) Schmitt trigger input PE5 1 KEYB Input/Output Port E5: Programmable as input or output Input KEY on wake up Input B: (dynamic pull-up selectable) (with internal pull-up register) Schmitt trigger input PE6 1 Input/Output Port E6: Programmable as input or output Input KEY on wake up Input C: (dynamic pull-up selectable) (with internal pull-up register) Input/Output Port C7: Programmable as input or output Input KEY on wake up Input D: (dynamic pull-up selectable) (with internal pull-up register) Input/Output Port F0: Programmable as input or output SO Output Data transmit pin when the Serial Bus Interface is in SIO mode SDA Input/Output Data transmit/receive pin when the Serial Bus Interface is in I2C mode; programmable as a push-pull or open-drain output KEYC Schmitt trigger input PE7 1 KEYD Schmitt trigger input PF0 1 Schmitt trigger input PF1 1 Input/Output Port F1: Programmable as input or output SI Input Data receive pin when the Serial Bus Interface is in SIO mode SCL Input/Output Clock input/output pin when the Serial Bus Interface is in I2C mode; programmable as a push-pull or open-drain output Schmitt trigger input PF2 1 SCK PF3 1 DREQ2 PF4 1 INT0 Port F4: Programmable as input or output Input DMA Request 3: DMA transfer request from an external I/O device to DMAC3 1 Input/Output Port F6: Programmable as input or output 1 8 8 TCOUT0-TCO UT7 PJ0 DMA Request 2: DMA transfer request from an external I/O device to DMAC2 Input/Output DMA Acknowledge 2: Acknowledge signal for DMA transfer requested by DREQ2 TC0IN-TC7IN PH0-PH7 Port F3: Programmable as input or output Input Port F5: Programmable as input or output TBTIN PG0-PG7 Input/Output Input/Output DACK3 PF7 Clock input/output pin when the Serial Bus Interface is in SIO mode 1 DREQ3 PF6 Port F2: Programmable as input or output Input/Output Output DACK 2 PF5 Input/Output 1 Output DMA Acknowledge 3: Acknowledge signal for DMA transfer requested by DREQ3 Input/Output Port F7: Programmable as input or output Input 32-bit Time-Base Timer Input: Count input to 32-bit time-base Timer Input/Output Port G: Individually programmable as input or output Input 32-Bit Timer Capture Trigger Input Input/Output Port H: Individually programmable as input or output Output 32-Bit Timer Compare Match Output Input/Output Port J0: Programmable as input or output Input Interrupt Request 0: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Schmitt trigger input TMP1962F-11 TMP1962F10AXBG Table 2.2 Pin Names and Function (5/6) Pin Name PJ1 # of Pins Type 1 Input/Output Port J1: Programmable as input or output Input External Bus Mode: If this pin is sampled high (DVCC21) at the rising edge of RESET, the TMP1962F10AXBG enters multiplex bus mode. If this pin is sampled low at the rising edge of RESET, the TMP1962F10AXBG enters separate bus mode. During a reset sequence, this pin should be pulled up to a logic 1or pulled down to a logic 0 depending on the bus mode to be used. Input/Output Port J2: Programmable as input or output Input Single Boot Mode: If this pin is sampled low at the rising edge of RESET, the TMP1962F10AXBG enters Single Boot mode for re-programming of the on-chip flash. If this pin is sampled high (DVCC21) at the rising edge of RESET, the TMP1962F10AXBG enters NORMAL mode. During a reset sequence, this pin should be pulled up to a logic 1 commonly. Input/Output Port J3: Programmable as input or output Input Interleave Mode: The TMP1962F10AXBG enters Interleave mode when this pin is sampled high (DVCC21) at the rising edge of RESET. During a reset sequence, this pin should be pulled up to a logic 1. Input/Output Port J4: Programmable as input or output Input This pin is used to set the mode. If this pin is sampled high (DVCC21) at the rising edge of RESET, the TMP1962F10AXBG enters Big-endian mode. If this pin is sampled low at the rising edge of RESET, the TMP1962F10AXBG enters Little-endian mode. During a reset sequence, this pin should be pulled up to a logic 1or pulled down to a logic 0 depending the endian to be used. Input/Output Port K: Programmable as input or output Input Key on wake up input 0-7 (dynamic pull-up selectable) (with internal pull-up register) BUSMD PJ2 1 BOOT PJ3 1 INTLV PJ4 1 ENDIAN PK0-PK7 8 KEY0-KEY7 Function Schmitt trigger input PL0 1 TA4IN PL1 1 TA6IN PL2 1 TA8IN PL3 1 TAAIN PL4 1 TB0IN0 PL5 1 TB0IN1 PL6 1 TB1IN0 PL7 1 TB1IN1 Input/Output Port L0: Programmable as input or output Input 8-bit Timer 4 Input: Input to 8-bit Timer 4 Input/Output Port L1: Programmable as input or output Input 8-bit Timer 6 Input: Input to 8-bit Timer 6 Input/Output Port L2: Programmable as input or output Input 8-bit Timer 8 Input: Input to 8-bit Timer 8 Input/Output Port L3: Programmable as input or output Input 8-bit Timer A Input: Input to 8-bit Timer A Input/Output Port L4: Programmable as input or output Input 16-Bit Timer 0 Input 0: Count/capture trigger input to 16-bit Timer 0 Input/Output Port L5: Programmable as input or output Input 16-Bit Timer 0 Input 1: Capture trigger input to 16-bit Timer 0 Input/Output Port L6: Programmable as input or output Input 16-Bit Timer 1 Input 0: Count/capture trigger input to 16-bit Timer 1 Input/Output Port L7: Programmable as input or output Input 16-Bit Timer 1 Input 1: Capture trigger input to 16-bit Timer 1 PM0-PM7 8 Input/Output Port M: Individually programmable input or output PN0 1 Input/Output Port N0: Programmable as input or output Output Serial Transmit Data 6: Programmable as a push-pull or open-drain output 1 Input/Output Port N1: Programmable as input or output Input Serial Receive Data 6 TXD6 PN1 RXD6 PN2 Input/Output Port N2: Programmable as input or output SCLK6 1 Input Serial Clock Input/Output 6 CTS6 Input Serial Clear-to-Send 6 Programmable as a push-pull or open-drain output PN3-PN7 5 Input/Output PO0-PO7 8 Input/Output Port N3-N7: Individually programmable input or output Port O: Individually programmable input or output PP0-PP7 8 Input/Output Port P: Individually programmable input or output TMP1962F-12 TMP1962F10AXBG Table 2.2 Pin Names and Function (6/6) Pin Name # of Pins Type Function NMI 1 Input Nonmaskable Interrupt Request: Causes an NMI interrupt on the falling edge PLLOFF 1 Input This pin should be tied to High (DVCC21) when the frequency multiplied clock from the PLL is used; Otherwise, it should be tied to Low. Schmitt trigger input RSTPUP 1 Input During a reset sequence, Port 3 and Port 4 are pull-up enabled if this pin is sampled High (DVCC32), and disabled if this pin is sampled Low. Schmitt trigger input RESET 1 Input Reset (with internal pull-up register): Initializes the whole TMP1962F10AXBG Schmitt trigger input X1/X2 2 Input/Output Connection pins for a high-speed crystal XT1/XT2 2 Input/Output This pin should be left open. DRESET 1 Input Debug Reset: Signal for DSU- ICE (Schmitt trigger input, with internal pull-up register) DCLK 1 Output Debug Clock: Signal for DSU-ICE DBGE 1 Input Debug Enable: Signal for DSU-ICE (Schmitt trigger input, with internal pull-up register) PCST3-0 4 Output PC Trace Status: Signal for DSU-ICE SDI/ DINT 1 Input Serial Data Input/Debug Interrupt: Signal for DSU-ICE (Schmitt trigger input, with internal pull-up register) SDAO/TPC 1 Output Serial Data and Address Output/Target PC: Signal for DSU-ICE TCK 1 Input Test Clock Input: Signal for JTAG test (Schmitt trigger input, with internal pull-up register) TMS 1 Input Test Mode Select Input: Signal for JTAG test (Schmitt trigger input, with internal pull-up register) TDI 1 Input Test Data Input: Signal for JTAG test (Schmitt trigger input, with internal pull-up register) TDO 1 Output Test Data Output: Signal for JTAG test TRST 1 Input Test Reset Input: Signal for JTAG test (Schmitt trigger input, with internal pull-up register) BW0-1 2 Input Both BW0 and BW1 should be tied to High (DVCC21). (Schmitt trigger input) VREFH 1 Input Input pin for high reference voltage for the A/D Converter This pin should be connected to the AVCC pin when the A/D Converter is not used. VREFL 1 Input Input pin for low reference voltage for the A/D Converter This pin should be connected to the AVCC pin when the A/D Converter is not used. AVCC31-32 2 ⎯ Power supply pins for the A/D Converter. These pins should always be connected to power supply even when the A/D Converter is not used. AVSS 3 ⎯ Ground pins for the A/D Converter. These pins should always be connected to ground even when the A/D Converter is not used. TEST0 1 ⎯ Test pin: This pin should be left open or tied to ground. TEST1 1 TEST2 1 ⎯ Test pin: This pin should be left open or tied to ground. TEST3 1 ⎯ Test pin: This pin should be left open or tied to ground. TEST4 1 ⎯ Test pin: This pin should be left open or tied to ground. TEST5 1 Input SYSRDY 1 Output CVCC2 1 ⎯ Power supply pins for an oscillator: 2.5 V CVSS 1 ⎯ Ground pin for an oscillator (0 V) CVCCH 1 ⎯ This pin should be left open. CAP1 1 ⎯ This pin should be left open. CAP2 1 ⎯ This pin should be left open. FVCC2 3 ⎯ Power supply pins for a Flash memory: 2.5 V FVCC3 1 ⎯ Power supply pin for a flash memory: 3 V FVSS 4 ⎯ Ground pins for a flash memory (0 V) DVCC21-22 5 ⎯ Power supply pins: 2.5 V DVCC31-34 9 ⎯ Power supply pins: 3 V DVSS 9 ⎯ Ground pins (0V) Test pin: This pin should be tied to ground. Input Test pin: This pin should be tied to ground. Signal to grant access to a flash memory TMP1962F-13 TMP1962F10AXBG Note 1: PJ1, PJ2, PJ3 and PJ4 should be held at the prescribed logic states for one system clock cycle before and after the rising edge of RESET, with the RESET signal being stable in either logic state. Note 2: Debugging with a DSU-probe is enabled on the TMP1962F10AXBG. Connection to the DSU-probe is available on the TMP1962C10BXBG, but a DSU-probe can not read the contents of on-chip ROM or write to registers other than the processor core, on-chip memory and external device. Table 2.3 shows correspondence between pins and power supply pins. Table 2.3 Pins and Corresponding Power Supply Pins Pin Power Supply Mask Type Flash Type P0 DVCC33 DVCC33 P1 DVCC33 P2 P3 Pin Power Supply Mask Type Flash Type PO DVCC31 DVCC31 DVCC33 PP DVCC31 DVCC31 DVCC33 DVCC33 X1 CVCC15 CVCC2 DVCC33 DVCC33 X2 CVCC15 CVCC2 P4 DVCC33 DVCC33 RESET DVCC2 DVCC21 P5 DVCC33 DVCC33 NMI DVCC2 DVCC21 P6 DVCC33 DVCC33 PLLOFF DVCC2 DVCC21 P7 AVCC32 AVCC32 DRESET DVCC2 DVCC21 P8 AVCC32 AVCC32 DCLK DVCC2 DVCC21 P9 AVCC31 AVCC31 DBGE DVCC2 DVCC21 PA DVCC32 DVCC32 PCST3-0 DVCC2 DVCC21 PB DVCC32 DVCC32 SDI/ DINT DVCC2 DVCC21 PC DVCC32 DVCC32 SDAO/TPC DVCC2 DVCC21 PD DVCC32 DVCC32 TCK DVCC34 DVCC34 PE DVCC32 DVCC32 TMS DVCC34 DVCC34 PF DVCC32 DVCC32 TDI DVCC34 DVCC34 PG DVCC32 DVCC32 TDO DVCC34 DVCC34 PH DVCC32 DVCC32 TRST DVCC34 DVCC34 PI DVCC34 DVCC34 BW1-0 DVCC2 DVCC21 PJ DVCC2 DVCC21 RSTPUP DVCC32 DVCC32 PK DVCC34 DVCC34 PL DVCC34 DVCC34 PM DVCC34 DVCC34 PN DVCC31 DVCC31 TMP1962F-14 TMP1962F10AXBG Table 2.4 shows the supply voltage for power supply pins. Table 2.4 Supply Voltage for Power Supply Pins Power Supply Pin Supply Voltage DVCC15 1.35 V - 1.65 V CVCC15 1.35 V - 1.65 V DVCC2 2.3 V - 3.3 V DVCC21 2.2 V - 2.7 V DVCC22 2.2 V - 2.7 V CVCC2 2.2 V - 2.7 V FVCC2 2.2 V - 2.7 V FVCC3 2.9 V - 3.6 V DVCC31 - 34 1.65 V - 3.3 V AVCC31 - 32 2.7 V - 3.3 V Applied for Mask Type Flash Type Mask/Flash Type Note 1: AVCC32 ≤ AVCC31 • When P7 to P9 are used as A/D converter inputs: 2.7 ≤ AVCC3* • When P9 (powered by AVCC31) is used as an A/D converter input while P7 and P8 (powered by AVCC32) are used as ports: 2.7 V ≤ AVCC31 ≤ 3.3 V 1.65 V ≤ AVCC32 ≤ AVCC31 • When P7 (powered by AVCC32) is used as an A/D converter input which P8 (powered by AVCC32) and P9 (powered by AVCC31) are used as ports: 2.7 V ≤ AVCC32 ≤ AVCC31 ≤ 3.3 V Note2: With power supplies for CPU and internal logic (mask type: DVCC15/DVCC2/DVCC15, and flash type: DVCC21/DVCC22/CVCC2/FVCC2/FVCC3) being applied, power supplies for other I/O ports can be interrupted on the TMP1962. However, when AVCC31 for analog power supply is interrupted, overlap current is generated on the TMP1962F10A with on-chip flash memory during the transition to be stable in 0 V. Overlap current can be suppressed by AD conversion of the conversion result 0 V before interrupting AVCC31 power supply, but suppress it on devices. TMP1962F-15 TMP1962F10AXBG 3. Flash Memory This chapter describes the flash memory of the TMP1962F10AXBG, a flash version of the TMP1962C10BXBG. The TMP1962F10AXBG contains a 1-Mbyte flash EEPROM and 40-kbyte RAM whereas the TMP1962C10BXBG contains a 1-Mbyte ROM and a 40-kbyte RAM. In other respects, the hardware configuration and the functionality of the TMP1962F10AXBG are identical to those of the TMP1962C10BXBG. For descriptions of the on-chip I/O peripherals, refer to the TMP1962C10BXBG datasheet. 3.1 Features (1) Organization The TMP1962F10AXBG contains 8 Mbits (1024 kbytes) of flash memory, which is divided into a total of 8 blocks (128-kbyte x 8) to allow for independent protection from program and erase for each block. While the CPU can access information in the flash through a full 32-bit data bus, an external flash programmer can only perform 16-bit data bus writes to the flash. (2) Access Types The flash memory of the TMP1962F10AXBG provides the interleaved access type. (3) Program/Erase Time • Chip programming time: 15 seconds (typ.) including verify operations • Chip erase time: 40 seconds (typ.), including verify operations Note: These program and erase times are typical values and do not include data transfer overhead. The actual chip program and erase times depend on the programming method used. (4) Programming Modes Several options exist to program the TMP1962F10AXBG flash memory. On-Board Programming modes allow for re-programming of the flash memory while the chip is soldered on a printed circuit board. Programmer mode utilizes an EPROM programmer to perform code updates. • On-Board Programming modes 1) User Boot mode Supports use of a user-written programming algorithm. 2) Single Boot mode Downloads the new program code using a Toshiba-defined serial interface protocol. • Programmer Mode Supports use of a general-purpose EPROM programmer. (5) Re-programming The TMP1962F10AXBG flash memory is compatible with the JEDEC standards, except a few unique functions. Thus, it is easy to migrate from a discrete flash memory device to the on-chip flash memory of the TMP1962F10AXBG. The TMP1962F10AXBG contains hardware to perform programming and erase operations automatically. This eliminates the need for the user to code complex program and erase sequences. The security feature of the TMP1962F10AXBG flash memory prevents the stored data from being read while it is being re-programmed with programming equipment. The TMP1962F10AXBG also allows the user to protect individual blocks of the flash memory against program or erase through software commands; however, 12-V VPP programming does not support data protection on a block-by-block basis. The flash memory is secured automatically by all of 8 blocks being protected. Unsecuring the flash memory automatically erases the stored data prior to unprotecting the blocks. TMP1962F-15 TMP1962F10AXBG JEDEC Standard Changes and Enhancements Auto Program Added feature: Security Auto Program Auto Chip Erase Changed feature: Block protection is available only under software control. Auto Block Erase Removed feature: Erase Resume/Suspend mode Auto Multi-Block Erase Data Polling / Toggle Bit Block Diagram Internal Address Bus Internal Data Bus Internal Control Bus Mode Setup Pins Mode Control ROM Controller / Interleave Control Control Address Data Flash Memory Control Logic (Including Automatic Sequence Control Logic) RDY/BSY Output Command Register Address Latch Data Latch Column Decoder / Sense Amp Row Decoder 3.2 Flash Memory Array 1024 KB Erase Block Decoder Figure 3.1 Flash Memory Block Diagram TMP1962F-16 TMP1962F10AXBG 3.3 Operating Modes 3.3.1 Overview The TMP1962F10AXBG offers a total of five operating modes, including the one in which the flash memory is unused. Table 3.1 Operating Modes Operating Mode Single-Chip Mode Normal Mode User Boot Mode Description After a reset, the TX19 core processor executes out of the on-chip flash memory. Set the INTLV pin to High level when RESET is released. Single-Chip mode is further divided into Normal mode in which the user application executes and User Boot mode which allows for re-programming of the flash memory while the TMP1962F10AXBG is installed on a printed circuit board. The user can freely define how to switch between Normal mode and User Boot mode. For example, the logic state on, say, Port 00, can be used to determine whether to put the flash memory in Normal mode or User Boot mode. The user must include a routine in the application program to test the state of that port. Single Boot Mode After a reset, the TX19 core processor executes out of the on-chip boot ROM (which is a mask ROM). The boot ROM contains a routine to aid users in performing on-board programming of the flash memory via a serial port of the TMP1962F10AXBG. The serial port is connected to an external host which transfers new data according to a prescribed protocol. Programmer Mode This mode allows re-programming of the flash memory with a general-purpose EPROM programmer. Use the programmer and programming adaptor recommended by Toshiba. The on-chip flash memory can be re-programmed in one of the following three modes: User Boot mode, Single Boot mode and Programmer mode. Of these modes, User Boot mode and Single Boot mode are collectively referred to as on-board programming modes. The logic states on the BW0, BW1, BOOT and INTLV pins during a reset sequence determine the mode of operation for the flash memory, as shown in Table 3.2. After RESET is released, PJ2 ( BOOT ) and PA2 (INTLV) can be configured as general-purpose I/O pins. After a reset, the CPU operates in compliance with the selected mode, except for Programmer mode. When Programmer mode is selected, RESET must be held at logic 0. The input pins listed in Table 3.2 must remain stable once the flash memory is put in a given mode of operation. Table 3.2 Modes of Operation # Input Pins Operating Mode RESET BW0 BW1 RESET INTLV (1) Single-Chip Mode 0→1 1 1 1 1 (2) Single Boot Mode 0→1 1 1 0 Note 1 (3) Programmer Mode 0 0 1 Note 1 Note 1 Note 1: Don’t care. The pins must be held at 1 or 0, however. TMP1962F-17 TMP1962F10AXBG (3) Programmer Mode Reset Any condition other than (4) + RESET = 0 (1) (2) RESET = 0 RESET = 0 Single-Chip Mode Normal Mode User-defined condition User Boot Mode Single Boot Mode On-Board Programming Mode Parenthesized numbers indicate that the relevant pins are at the logic states shown in Table 3.2. Figure 3.2 Mode Transitions 3.3.2 Reset Operation To reset the TMP1962F10AXBG, RESET must be asserted for at least 12 system clock periods after the power supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 2.37 µs at 40.5 MHz when the on-chip PLL is utilized. TMP1962F-18 TMP1962F10AXBG 3.3.3 Memory Maps The memory map for the TMP1962F10AXBG varies according to the operation mode selected for the on-chip flash memory. Following are the memory maps in each operation mode. Normal Mode On-Chip Peripherals Single Boot Mode 0xFFFF_FFFF Programmer Mode 0xFFFF_FFFF On-Chip Peripherals 0xFFFF_E000 (Reserved) On-Chip RAM (40 KB) (Reserved) Used for debugging 0xFFFD_6000 0xFF3F_FFFF 0xFFFD_DFFF On-Chip RAM (40 KB) 0xFFFD_6000 (Reserved) 0xFF3F_FFFF Used for debugging (Reserved) 0xFF20_0000 (Reserved) 0xFF00_0000 0xC000_0000 0xBF00_0000 0xFF20_0000 (Reserved) 0xFF00_0000 0xC000_0000 (Reserved) 0xBF00_0000 0x400F_FFFF On-Chip ROM Shadow 0xC000_0000 Inaccessible 0x400F_FFFF On-Chip Flash 0x4000_0000 Inaccessible (512 MB) 0xFFFF_FFFF (Reserved) 0xFFFD_FFFF (Reserved) (Reserved) Inaccessible 0xFFFF_E000 0x2000_0000 0x4000_0000 0x4000_0000 Inaccessible Inaccessible (512 MB) 0x2000_0000 (512 MB) 0x2000_0000 Inaccessible 0x1FCF_FFFF User Program Area 0x1FC0_0400 Maskable Interrupt Area 0x1FC0_1FFF Boot ROM (8 KB) Exception Vector Area 0x000F_FFFF 0x1FC0_0000 0x1FC0_0000 0x0000_0000 0x0000_0000 Note: The addresses shown above are physical addresses. Figure 3.3 TMP1962F10AXBG Memory Maps 128 KB 128 KB 128 KB 128 KB 128 KB 128 KB 128 KB 128 KB Block-0 Block-1 Block-2 Block-3 Block-4 Block-5 Block-6 Block-7 1024 KB Figure 3.4 Flash Memory Block Architecture TMP1962F-19 On-Chip Flash 0x0000_0000 TMP1962F10AXBG Table 3.3 Block Addresses User Boot Mode Boot Mode Programmer Mode Block-0 0x1FC0_0000 - 0x1FC1_FFFF (or 0x4000_0000 - 0x4001_FFFF) 0x1FC0_0000 - 0x1FC1_FFFF 0x0000_0000 - 0x0001_FFFF Block-1 0x1FC2_0000 - 0x1FC3_FFFF (or 0x4002_0000 - 0x4003_FFFF) 0x1FC2_0000 - 0x1FC3_FFFF 0x0000_8000 - 0x0003_FFFF Block-2 0x1FC4_0000 - 0x1FC5_FFFF (or 0x40040000 - 0x4005_FFFF) 0x1FC4_0000 - 0x1FC5_FFFF 0x0001_0000 - 0x0005_FFFF Block-3 0x1FC6_0000 - 0x1FC7_FFFF (or 0x4006_0000 - 0x4007_FFFF) 0x1FC6_0000 - 0x1FC7_FFFF Block-4 0x1FC8_0000 - 0x1FC9_FFFF (or 0x4008_0000 - 0x4009_FFFF) 0x1FC8_0000 - 0x1FC9_FFFF Block-5 0x1FCA_0000 - 0x1FCB_FFFF (or 0x400A_0000 - 0x400B_FFFF) 0x1FCA_0000 - 0x1FCB_FFFF Block-6 0x1FCC_0000 - 0x1FCD_FFFF (or 0x400C_0000 - 0x400D_FFFF) 0x1FCC_0000 - 0x1FCD_FFFF 0x0003_0000 - 0x000B_FFFF Block-7 0x1FCE_0000 - 0x1FCF_FFFF (or 0x400E_0000 - 0x400F_FFFF) 0x1FCE_0000 - 0x1FCF_FFFF 0x0003_8000 - 0x000C_FFFF 3.3.4 Interleave Mode 0x0001_8000 - 0x0007_FFFF 0x0002_0000 - 0x0009_FFFF 0x0002_8000 - 0x000A_FFFF If J3 (PJ3) is sampled high at the rising edge of RESET , the flash memory enters Interleave mode. The flash memory must be configured into Interleave mode. 3.3.5 Block Protection The TMP1962F10AXBG flash memory is organized into a total of 8 blocks (128 kbyte× 8). To protect stored data from any program and erase operations, each block has a protect bit, which can be set by executing the Block Protect command sequence. Blocks in protection mode are protected from even the Chip Erase and Multi-Block Erase commands; these commands erase only unprotected blocks. Since protection status is stored in flash memory cells, it is retained if the chip is powered off. When all blocks are protected, the data stored in these blocks are protected from being read in Programmer mode, which provides a security feature. TMP1962F-20 TMP1962F10AXBG 3.3.6 DSU-probe Interface The DSU-probe interface is used for software debugging using an external DSU-probe unit. This serves as an interface to the DSU-probe, and can not be used as general-purpose port. Consult the DSU-probe operation manual for a description of debugging using theDSU-probe. When the TMP1962F10AXBG is in DSU mode, the on-chip flash memory provides a security feature. (1) Flash security feature The TMP1962F10AXBG supports on-board debugging while it is installed on a printed circuit board. The TMP1962F10AXBG provides a security feature to prevent intrusive access to the flash memory. When the flash memory is in the secure state, a DSU-probe is denied access to the entirety of the flash memory. (2) Securing the flash (Disabling debugging with a DSU-probe) Once program debug is completed, write the Protect command to all of 8 blocks. This turns on the flash security feature. While the flash memory is in the secure state, a DSU-probe can not read its contents. When the chip is powered off and powered on again, the flash memory is secured, which disables debugging using a DSU-probe until the flash memory is unsecured. (3) Unsecuring the flash (Enabling debugging with a DSU-probe) The flash memory may only be unsecured by clearing the SEQON bit in the SEQMOD register and then writing a special code (0x0000_00C5) to the Security Control (SEQCNT) register. This prevents runaway software from inadvertently turning off the security feature. Unsecuring the flash memory enables the DSU interface. The flash memory can be secured again by setting the SEQON bit in the SEQMOD and writing 0x0000_00C5 to the SEQCNT while the chip is powered. SEQMOD (0xFFFF_E510) 7 6 5 4 3 2 1 0 Name ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SEQON Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R/W Reset Value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Function 1 1: Security on 0: Security off Note: This register must be read as a 32-bit quantity. Bits 1 to 31 are read as 0s. TMP1962F-21 TMP1962F10AXBG 7 SEQCNT (0xFFFF_E514) 6 5 4 3 2 1 0 10 9 8 18 17 16 26 25 24 Name Read/Write W Reset Value Function Must be written as 0x0000_00C5. 15 14 13 12 11 Name Read/Write W Reset Value Function Must be written as 0x0000_00C5. 23 22 21 20 19 Name Read/Write W Reset Value Function Must be written as 0x0000_00C5. 31 30 29 28 27 Name Read/Write W Reset Value Function Must be written as 0x0000_00C5. Note 1: This register is read as a 32-bit quantity. Note 2: The security feature of the TMP1962F10AXBG flash memory is not intended to guarantee rigid security protection. In cases where security protection is of utmost importance, use the TMP1962C10BXBG that contains mask ROM. (4) Application example The following flowchart exemplifies how to use the security feature with a DSU-ICE. TMP1962F10AXBG Security on at power-up Protect/unprotect judgment routine (user-created) External port data, etc. No Turn off security feature? Yes Program SEQMOD and SEQCNT to turn off security feature DSU-ICE can not be used. Security remains on. DSU-ICE can be used until the chip is powered off. Figure 3.5 Using the Security Feature TMP1962F-22 TMP1962F10AXBG 3.4 On-Board Programming Mode On-board programming modes allo w for re-programming of the flash memory while the TMP1962F10AXBG is soldered on a printed circuit board. In Single Boot mode, new data comes from a serial port under control of a Toshiba-provided routine in the boot ROM. User Boot mode allows you to create an algorithm of your own for flash memory erase and program operations. The TMP1962F10AXBG flash memory provides a security feature to prevent intrusive access to the flash memory while in Programmer mode. This security feature can be enabled upon completion of on-board programming to reduce the potential risk of software leaks to third parties. 3.4.1 User Boot Mode (Single-Chip Mode) User Boot mode allows you to create a programming algorithm of your own. This mode supports situations where the flash memory is to be re-programmed via a bus other than serial I/O. User Boot mode is one of the two submodes in Single-Chip mode; the other submode is Normal mode in which the CPU executes the user application. To re-program the flash memory, the mode of operation must be switched from Normal mode to User Boot mode. The user application code must include a mode judgment routine as part of the reset procedure. The user must define the conditions for mode switching, based on the logic states on I/O ports of the TMP1962F10AXBG. Additionally, the user must incorporate a programming algorithm into the user application code that is to be executed after User Boot mode is entered. It is not possible to read from the flash memory while it is being erased or programmed; therefore, the programming algorithm must be placed and executed outside of the flash memory. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption. All interrupts including the nonmaskable (NMI) interrupt must be globally disabled while the flash memory is being erased or programmed. The pages that follow describe the general procedures for two cases where the programming routine is: a) stored within the TMP1962F10AXBG flash memory, and b) loaded from an external controller. For a detailed description of the erase and program sequence, refer to Section 3.6, On-Board Programming and Erasure. TMP1962F-23 TMP1962F10AXBG User Boot Mode (1-A) Method 1: Storing a Programming Routine in the Flash Memory (1) Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMP1962F10AXBG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. • Mode judgment routine: Code to determine whether or not to switch to User Boot mode • Programming routine: Code to download new program code from a host controller and re-program the flash memory • Copy routine: Code to copy the flash programming routine from the TMP1962F10AXBG flash memory to either the TMP1962F10AXBG on-chip RAM or external memory device. Host Controller TMP1962F10AXBG New Application Program Code I/O Flash Memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine RAM (c) Copy Routine (2) After RESET is released, the reset procedure determines whether to put the TMP1962F10AXBG flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be globally disabled while in User Boot mode.) Host Controller New Application Program Code I/O TMP1962F10AXBG 0 → 1 RESET Flash Memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine (c) Copy Routine RAM TMP1962F-24 Conditions for entering User Boot mode (defined by the user) TMP1962F10AXBG (3) Once User Boot mode is entered, execute the copy routine to copy the flash programming routine to either the TMP1962F10AXBG on-chip RAM or an external memory device. (In the following figure, the on-chip RAM is used.) Host Controller New Application Program Code I/O TMP1962F10AXBG Flash Memory Old Application Program Code (b) Programming Routine [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine RAM (c) Copy Routine (4) Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block containing the old application program code. Host Controller New Application Program Code I/O TMP1962F10AXBG Flash Memory Erased (b) Programming Routine [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine (c) Copy Routine TMP1962F-25 RAM TMP1962F10AXBG (5) Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. Once programming is complete, turn on the protection of that flash block. Host Controller New Application Program Code I/O TMP1962F10AXBG Flash Memory New Application Program Code (b) Programming Routine [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine RAM (c) Copy Routine (6) Drive RESET low to reset the TMP1962F10AXBG. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. Host Controller (I/O) TMP1962F10AXBG Flash Memory 0 → 1 RESET New Application Program Code e [Reset Procedure] Set to Normal mode (a) Mode Judgment Routine (b) Programming Routine (c) Copy Routine RAM TMP1962F-26 TMP1962F10AXBG (1-B) Method 2: Transferring a Programming Routine from an External Host (1) Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMP1962F10AXBG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. • Mode judgment routine: Code to determine whether or not to switch to User Boot mode • Transfer routine: Code to download new program code from a host controller Also, prepare a programming routine on the host controller: • Programming routine: Code to download new program code from an external host controller and re-program the flash memory Host Controller New Application Program Code I/O (c) Programming Routine TMP1962F10AXBG Flash Memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine RAM (b) Transfer Routine (2) After RESET is released, the reset procedure determines whether to put the TMP1962F10AXBG flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be globally disabled while in User Boot mode.) Host Controller I/O New Application Program Code (c) Programming Routine TMP1962F10AXBG 0 → 1 RESET Flash Memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine (b) Transfer Routine TMP1962F-27 RAM Conditions for entering User Boot mode (defined by the user) TMP1962F10AXBG (3) Once User Boot mode is entered, execute the transfer routine to download the flash programming routine from the host controller to either the TMP1962F10AXBG on-chip RAM or an external memory device. (In the following figure, the on-chip RAM is used.) Host Controller New Application Program Code I/O (c) Programming Routine TMP1962F10AXBG Flash Memory Old Application Program Code (c) Programming routine [Reset Procedure] (a) Mode Judgment Routine RAM (b) Transfer Routine (4) Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block containing the old application program code. Host Controller New Application Program Code I/O (c) Programming Routine TMP1962F10AXBG Flash Memory Erased (c) Programming Routine [Reset Procedure] (a) Mode Judgment Routine (b) Transfer Routine TMP1962F-28 RAM TMP1962F10AXBG (5) Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. Once programming is complete, turn on the protection of that flash block. Host Controller New Application Program Code I/O (c) Programming Routine TMP1962F10AXBG Flash Memory New Application Program Code (c) Programming Routine [Reset Procedure] (a) Mode Judgment Routine RAM (b) Transfer Routine (6) Drive RESET low to reset the TMP1962F10AXBG. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. Host Controller I/O TMP1962F10AXBG 0 → 1 RESET Flash Memory New Application Program Code Set to Normal mode [Reset Procedure] (a) Mode Judgment Routine (b) Transfer Routine TMP1962F-29 RAM TMP1962F10AXBG 3.5 Single Boot Mode In Single Boot mode, the flash memory can be re-programmed by using a program contained in the TMP1962F10AXBG on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selected upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the flash memory is mapped to an address region different from it (see Figure 3.3 on page 19). Single Boot mode allows for serial programming of the flash memory. Channel 0 of the SIO (SIO0) of the TMP1962F10AXBG is connected to an external host controller. Via this serial link, a programming routine is downloaded from the host controller to the TMP1962F10AXBG on-chip RAM. Then, the flash memory is re-programmed by executing the programming routine. The host sends out both commands and programming data to re-program the flash memory. Communications between the SIO0 and the host must follow the protocol described later. To secure the contents of the flash memory, the validity of the application’s password is checked before a programming routine is downloaded into the on-chip RAM. If password matching fails, the transfer of a programming routine itself is aborted. As in the case of User Boot mode, all interrupts including the nonmaskable (NMI) interrupt must be globally disabled in Single Boot mode while the flash memory is being erased or programmed. In Single Boot mode, the boot-ROM programs are executed in Normal mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations. For a detailed description of the erase and program sequence, refer to 3.4 On-Board Programming and Erasure. TMP1962F-30 TMP1962F10AXBG Boot Mode (2-A) General Procedure: Using the Program in the On-Chip Boot ROM (1) The flash block containing the older version of the program code need not be erased before executing the programming routine. Since a programming routine and programming data are transferred via the SIO0, the SIO0 must be connected to a host controller. Prepare a programming routine on the host controller. Host Controller New Application Program Code I/O (a) Programming Routine TMP1962F10AXBG Boot ROM SIO0 Flash Memory Old Application Program Code (or Erased State) RAM (2) Reset the TMP1962F10AXBG with the mode setting pins held at appropriate logic values, so that the CPU re-boots from the on-chip boot ROM. The 12-byte password transferred from the host controller is first compared to the contents of special flash memory locations. (If the flash block has already been erased, the password is 0xFFFF.) Host Controller I/O New Application Program Code (a) Programming Routine TMP1962F10AXBG 0 → 1 RESET Boot ROM SIO0 Flash Memory Conditions for entering Single Boot mode Old Application Program Code (or Erased State) RAM TMP1962F-31 TMP1962F10AXBG (3) If the password was correct, the boot program downloads, via the SIO0, the programming routine from the host controller into the on-chip RAM of the TMP1962F10AXBG. The programming routine must be stored in the address range 0xFFFD_6000 – 0xFFFD_EFFF. Host Controller New Application Program Code I/O (a) Programming routine TMP1962F10AXBG Boot ROM SIO0 Flash Memory (a) Programming Routine Old Application Program Code (or Erased State) RAM (4) The CPU jumps to the programming routine in the on-chip RAM to erase the flash block containing the old application program code. The Block Erase or Chip Erase command may be used. Host Controller New Application Program Code I/O (a) Programming routine TMP1962F10AXBG Boot ROM SIO0 Flash Memory (a) Programming Routine Erased RAM TMP1962F-32 TMP1962F10AXBG (5) Next, the programming routine downloads new application program code from the host controller and programs it into the erased flash block. Once programming is complete, protection of that flash block is turned on. It is not allowed to move program control from the programming routine back to the boot ROM. In the example below, new program code comes from the same host controller via the same SIO channel as for the programming routine. However, once the programming routine has begun to execute, it is free to change the transfer path and the source of the transfer. Create board hardware and a programming routine to suit your particular needs. Host Controller New Application Program Code I/O (a) Programming Routine TMP1962F10AXBG Boot ROM SIO0 Flash Memory (a) Programming Routine New Application Program Code RAM (6) When programming of the flash memory is complete, power off the board and disconnect the cable leading from the host to the target board. Turn on the power again so that the TMP1962F10AXBG re-boots in Single-Chip (Normal) mode to execute the new program. Host Controller TMP1962F10AXBG 0 → 1 RESET Boot ROM SIO0 Flash Memory Set to Single-Chip (Normal) mode New Application Program Code RAM TMP1962F-33 TMP1962F10AXBG 3.5.1 Host-to-Target Connection Examples In Single Boot mode, serial transfer is used to re-program the flash memory while the TMP1962F10AXBG is installed on the board. In this mode, channel 0 of the SIO (SIO0) of the TMP1962F10AXBG is connected to a host controller, which is to issue commands to the target board. Figure 3.6 and Figure 3.7 show examples of host-to-target connections. Target Board Host Controller VCC 100 V a.c. Reg. VCC Reg. VCC TMP1962 MCU DVCC Mode Control BW1 BW0 NMI RESET TMODE RESET Boot Mode Selection Logic BOOT Mode Control ROM RAM RX RS232C TX VSS RXD0 (PC1) TXD0 (PC0) DVSS PC Figure 3.6 Example of a Connection Between a Host Controller and a Target Board (When the SIO0 is Configured for UART Mode) TMP1962F-34 TMP1962F10AXBG Target Board Host Controller VCC 100 V a.c. Reg. VCC Reg. VCC TMP1962 MCU DVCC Mode Control BW1 BW0 NMI RESET Mode Control ROM TMODE RESET Boot Mode Selection Logic BOOT RAM TCK RX RS232C TX TBUSY VSS SCLK0 (PC2) RXD0 (PC1) TXD0 (PC0) PI7 DVSS PC Figure 3.7 Example of a Connection Between a Host Controller and a Target Board (When the SIO0 is Configured for I/O Interface Mode) TMP1962F-35 TMP1962F10AXBG 3.5.2 Configuring for Single Boot Mode For on-board programming, boot the TMP1962F10AXBG in Single Boot mode, as follows: BW0 =1 BW1 =1 BOOT = 0 RESET = 0 → 1 Set the RESET input at logic 0, and the BW0, BW1 and BOOT (PJ2) inputs at the logic values shown above, and then release RESET (high). 3.5.3 Memory Map Figure 3.8 shows a comparison of the memory maps in Normal and Single Boot modes. In single Boot mode, the on-chip flash memory is mapped to physical addresses (0x4000_0000 through 0x400F_FFFF), virtual addresses (0x0000_0000 through 0x000F_FFFF), and the on-chip boot ROM is mapped to physical addresses 0x1FC0_0000 through 0x1FC0_1FFF. Normal Mode On-Chip Peripherals Single Boot Mode 0xFFFF_FFFF On-Chip Peripherals 0xFFFF_E000 (Reserved) On-Chip RAM (40 KB) (Reserved) Used for debugging 0xFFFF_E000 (Reserved) 0xFFFD_DFFF 0xFFFD_6000 0xFF3F_FFFF (Reserved) On-Chip RAM (40 KB) (Reserved) Used for debugging (Reserved) 0xFF20_0000 (Reserved) (Reserved) On-Chip ROM Shadow 0xFF00_0000 0xC000_0000 0xBF00_0000 0xFFFD_DFFF 0xFFFD_6000 0xFF3F_FFFF 0xFF20_0000 (Reserved) (Reserved) 0x400F_FFFF 0xFF00_0000 0xC000_0000 0xBF00_0000 0x400F_FFFF On-Chip Flash ROM 0x4000_0000 Inaccessible (512 MB) 0xFFFF_FFFF 0x4000_0000 Inaccessible (512 MB) 0x2000_0000 0x2000_0000 0x1FCF_FFFF User Program Area Internal ROM Maskable Interrupt Area 0x1FC0_0400 0x1FC0_1FFF Exception Vector Area Boot ROM (6 KB) 0x1FC0_0000 0x1FC0_0000 0x0000_0000 0x0000_0000 Figure 3.8 Memory Maps for Normal and Single Boot Modes (Physical Addresses) TMP1962F-36 TMP1962F10AXBG 3.5.4 Interface Specification In Single Boot mode, an SIO channel is used for communications with a programming controller. Both UART (asynchronous) and I/O Interface (synchronous) modes are supported. The communication formats are shown below. In the subsections that follow, virtual addresses are indicated, unless otherwise noted. • UART mode Communication channel: Transfer mode: Data length: Parity bits: STOP bits: Baud rate: • SIO Channel 0 (SIO0) UART (asynchronous) mode, full-duplex 8 bits None 1 Arbitrary baud rate I/O Interface mode Communication channel: SIO Channel 0 (SIO0) Transfer mode: I/O Interface mode, half-duplex Synchronization clock (SCLK0): Input Handshaking signal: PI7 configured as an output Baud rate: Arbitrary baud rate Table 3.4 Required Pin Connections Interface Pin UART Mode I/O Interface Mode DVCC2 (2.5 V) Required Required DVSS Required Required Mode-Setting Pin BOOT Required Required Reset Pin RESET Required Required Communication Pins TXD0 Required Required RXD0 Required Required SCLK0 Not Required Required (Input Mode) P87 Not Required Required (Input Mode) Power Supply Pins 3.5.5 Data Transfer Format The host controller is to issue one of the commands listed in Table 3.5 to the target board. Table 3.6 to Table 3.8 illustrate the sequence of two-way communications that should occur in response to each command. Table 3.5 Single Boot Mode Commands Code 10H Command RAM Transfer 20H Show Flash Memory Sum 30H Show Product Information TMP1962F-37 TMP1962F10AXBG Table 3.6 Transfer Format for the RAM Transfer Command Byte Boot ROM 1st byte Data Transferred from the Controller to the TMP1962F10AXBG Serial operation mode and baud rate For UART mode 86H For I/O Interface mode 30H Baud Rate Desired baud rate (Note 1) ⎯ 2nd byte Data Transferred from the TMP1962F10AXBG to the Controller ⎯ ACK for the serial operation mode byte For UART mode Normal acknowledge 86H (The boot program aborts if the baud rate is can not be set correctly.) For I/O Interface mode Normal acknowledge 3rd byte Command code ⎯ ACK for the command code byte (Note 2) Normal acknowledge 10H Negative acknowledge x1H Communication error x8H 5th byte thru 16th byte Password sequence (12 bytes) 17th byte Checksum value for bytes 5–16 ⎯ (0x4000_03F4 thru 0x4000_03FF) ⎯ 18th byte ⎯ 19th byte RAM storage start address (bits 31–24) ⎯ 20th byte RAM storage start address (bits 23–16) ⎯ 21st byte RAM storage start address (bits 15–8) ⎯ 22nd byte RAM storage start address (bits 7–0) ⎯ 23rd byte RAM storage byte count (bits 15–8) ⎯ 24th byte RAM storage byte count (bits 7–0) ⎯ 25th byte Checksum value for bytes 19–24 ACK for the checksum byte (Note 2) Normal acknowledge 10H Negative acknowledge 11H Communication error 18H ⎯ 26th byte RAM (10H) ⎯ 4th byte 30H ⎯ ACK for the checksum byte (Note 2) Normal acknowledge 10H Negative acknowledge 11H Communication error 18H ⎯ 27th byte thru mth byte RAM storage data (m + 1)th byte Checksum value for bytes 27–m ⎯ (m + 2)th byte ⎯ ACK for the checksum byte (Note 2) Normal acknowledge 10H Non-acknowledge 11H Communications error 18H (m + 3)th byte ⎯ Jump to RAM storage start address Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Note 3: The 19th to 25th bytes must be within the RAM address range 0xFFFD_6000–0xFFFF_DFFF . TMP1962F-38 TMP1962F10AXBG Table 3.7 Transfer Format for the Show Flash Memory Sum Command Byte Boot ROM 1st byte Data Transferred from the Controller to the TMP1962F10AXBG Serial operation mode and baud rate For UART mode 86H For I/O Interface mode 30H Baud Rate ⎯ Desired baud rate (Note 1) ⎯ 2nd byte Data Transferred from the TMP1962F10AXBG to the Controller ACK for the serial operation mode byte For UART mode Normal acknowledge 86H (The boot program aborts if the baud rate can not be set correctly.) For I/O Interface mode Normal acknowledge 3rd byte Command code 30H ⎯ (20H) 4th byte ⎯ ACK for the command code byte (Note 2) Normal acknowledge 20H Negative acknowledge x1H Communication error x8H 5th byte ⎯ SUM (upper byte) 6th byte ⎯ SUM (lower byte) 7th byte ⎯ Checksum value for bytes 5 and 6 8th byte (Wait for the next command code.) ⎯ Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. TMP1962F-39 TMP1962F10AXBG Table 3.8 Transfer Format for the Show Product Information Command (1/2) Byte Boot ROM 1st byte Data Transferred from the Controller to the TMP1962F10AXBG 2nd byte Serial operation mode and baud rate For UART mode 86H For I/O Interface mode 30H ⎯ 3rd byte Command code Baud Rate Desired baud rate (Note 1) (30H) Data Transferred from the TMP1962F10AXBG to the Controller ⎯ ACK for the serial operation mode byte For UART mode Normal acknowledge 86H (The boot program aborts if the baud rate can not be set correctly.) For I/O Interface mode Normal acknowledge 30H ⎯ 4th byte ⎯ ACK for the command code byte (Note 2) Normal acknowledge 10H Negative acknowledge x1H Communication error x8H 5th byte ⎯ Flash memory data (at address 0x4000_03F0H) 6th byte ⎯ Flash memory data (at address 0x4000_03F1H) 7th byte ⎯ Flash memory data (at address 0x4000_03F2H) 8th byte ⎯ Flash memory data (at address 0x4000_03F3H) 9th byte thru 20th byte ⎯ Product name (12-byte ASCII code) “TX1962F10” from the 9th byte 21st byte thru 24th byte ⎯ Password comparison start address (4 bytes) F4H, 03H, 00H and 00H from the 21st byte 25th byte thru 28th byte ⎯ RAM start address (4 bytes) 00H, 60H, FDH and FFH from the 25th byte 29th byte thru 32nd byte ⎯ Dummy data (4 bytes) FFH, 6FH, FDH and FFH from the 29th byte 33rd byte thru 36th byte ⎯ RAM end address (4 bytes) FFH, DFH, FDH and FFH from the 33rd byte 37th byte thru 40th byte ⎯ Dummy data (4 bytes) 00H, 70H, FDH and FFH from the 37th byte 41st byte thru 44th byte ⎯ Dummy data (4 bytes) FFH, EFH, FDH and FFH from the 41st byte 45th byte thru 46th byte ⎯ Fuse information (2 bytes) 01H and 00H from the 45th byte 47th byte thru 50th byte ⎯ Flash memory start address (4 bytes) 00H, 00H, 00H and 00H from the 47th byte 51st byte thru 54th byte ⎯ Flash memory end address (4 bytes) FFH, FFH, 0FH and 00H from the 51st byte 55th byte thru 56th byte ⎯ Flash memory block count (2 bytes) 08H and 00H from at the 55th byte TMP1962F-40 TMP1962F10AXBG Table 3.8 Transfer Format for the Show Product Information Command (2/2) Byte Boot ROM 57th byte thru 60th byte 61st byte thru 64th byte 65th byte 66th byte 67th byte Data Transferred from the Controller Baud Rate to the TMP1962F10AXBG ⎯ ⎯ ⎯ ⎯ (Wait for the next command code.) Data Transferred from the TMP1962F10AXBG to the Controller Start address of a group of the same-size flash blocks (4 bytes) 00H, 00H, 00H and 00H from the 57th byte Size (in halfwords) of the same-size flash blocks (4 bytes) 00H, 00H, 01H and 00H from the 61st byte Number of flash blocks of the same size (1 byte) 08H Checksum value for bytes 5 to 65 ⎯ Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. 3.5.6 Overview of the Boot Program Commands When Single Boot mode is selected, the boot program is automatically executed on startup. The boot program offers these three commands, the details of which are provided on the following subsections. • RAM Transfer command The RAM Transfer command stores program code transferred from a host controller to the on-chip RAM and executes the program once the transfer is successfully completed. The maximum program size is 36 kbytes. The RAM storage start address must be within the range. The RAM Transfer command can be used to download a flash programming routine of your own; this provides the ability to control on-board programming of the flash memory in a unique manner. The programming routine must utilize the flash memory command sequences described in Section 3.6.17 Before initiating a transfer, the RAM Transfer command checks a password sequence coming from the controller against that stored in the flash memory. If they do not match, the RAM Transfer command aborts. Once the RAM Transfer command is complete, the whole on-chip RAM is accessible. • Show Flash Memory Sum command The Show Flash Memory Sum command adds the contents of the 1024 kbytes of the flash memory together. The boot program does not provide a command to read out the contents of the flash memory. Instead, the Flash Memory Sum command can be used for software revision management. • Show Product Information command The Show Product Information command provides the product name, on-chip memory configuration and the like. This command also reads out the contents of the flash memory locations at addresses 0x0000_03F0 through 0x0000_03F3. In addition to the Show Flash Memory Sum command, these locations can be used for software revision management. TMP1962F-41 TMP1962F10AXBG 3.5.7 RAM Transfer Command See Table 3.6. (1) The 1st byte specifies which one of the two serial operation modes is used. For a detailed description of how the serial operation mode is determined, see Section 3.5.11. If it is determined as UART mode, the boot program then checks if the SIO0 is programmable to the baud rate at which the 1st byte was transferred. During the first-byte interval, the RXE bit in the SC0MOD register is cleared. • To communicate in UART mode Send, from the controller to the target board, 86H in UART data format at the desired baud rate. If the serial operation mode is determined as UART, then the boot program checks if the SIO0 can be programmed to the baud rate at which the first byte was transferred. If that baud rate is not possible, the boot program aborts, disabling any subsequent communications. • To communicate in I/O Interface mode Send, from the controller to the target board, 30H in I/O Interface data format at 1/16 of the desired baud rate. Also send the 2nd byte at the same baud rate. Then send all subsequent bytes at a rate equal to the desired baud rate. In I/O Interface mode, the CPU sees the serial receive pin as if it were a general input port in monitoring its logic transitions. If the baud rate of the incoming data is high or the chip’s operating frequency ishigh, the CPU may not be able to keep up with the speed of logic transitions. To prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of the desired baud rate; then the boot program calculates 16 times that as the desired baud rate. When the serial operation mode is determined as I/O Interface mode, the SIO0 is configured for SCLK Input mode. Beginning with the third byte, the controller must ensure that its AC timing restrictions are satisfied at the selected baud rate. In the case of I/O Interface mode, the boot program does not check the receive error flag; thus there is no such thing as error acknowledge (x8H). (2) The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the 1st byte. The boot program echoes back the first byte: 86H for UART mode and 30H for I/O Interface mode. • UART mode If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred, the boot program programs the BR0CR and sends back 86H to the controller as an acknowledge. If the SIO0 is not programmable at that baud rate, the boot program simply aborts with no error indication. Following the 1st byte, the controller should allow for a time-out period of five seconds. If it does not receive 86H within the alloted time-out period, the controller should give up the communication. The boot program sets the RXE bit in the SC0MOD register to enable reception before loading the SIO transmit buffer with 86H. TMP1962F-42 TMP1962F10AXBG • I/O Interface mode The boot program programs the SC0MOD0 and SC0CR registers to configure the SIO0 in I/O Interface mode (clocked by the rising edge of SCLK0), writes 30H to the SC0BUF. Then, the SIO0 waits for the SCLK0 signal to come from the controller. Following the transmission of the 1st byte, the controller should send the SCLK clock to the target board after a certain idle time (several microseconds). This must be done at 1/16 the desire baud rate. If the 2nd byte, which is from the target board to the controller, is 30H, then the controller should take it as a go-ahead. The controller must then delivers the 3rd byte to the target board at a rate equal to the desired baud rate. The boot program sets the RXE bit in the SC0MOD register to enable reception before loading the SIO transmit buffer with 30H. (3) The 3rd byte, which the target board receives from the controller, is a command. The code for the RAM Transfer command is 10H. (4) The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits x8H and returns to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined — they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 3.5, the boot program echoes it back to the controller. When the RAM Transfer command was received, the boot program echoes back a value of 10H and then branches to the RAM Transfer routine. Once this branch is taken, a password check is done. Password checking is detailed in Section 3.5.12. If the 3rd byte is not a valid command, the boot program sends back x1H to the controller and returns to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined — they hold the same values as the upper four bits of the previously issued command. (5) The 5th to 16th bytes, which the target board receives from the controller, are a 12-byte password. The 5th byte is compared to the contents of address 0x0000_03F4 in the flash memory; the 6th byte is compared to the contents of address 0x0000_03F5 in the flash memory; likewise, the 16th byte is compared to the contents of address 0x0000_03FF in the flash memory. If the password checking fails, the RAM Transfer routine sets the password error flag. (6) The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in Section 3.5.14. TMP1962F-43 TMP1962F10AXBG (7) The 18th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive error in the 5th to 17th bytes. If there was a receive error, the boot program sends back 18H and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 5th to 17th bytes must result in zero (with the carry dropped). If it is not zero, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. Finally, the RAM Transfer routine examines the result of the password check. The following two cases are treated as a password error. In these cases, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. • Irrespective of the result of the password comparison, all of the 12 bytes of a password in the flash memory are the same value other than FFH. • Not all of the password bytes transmitted from the controller matched those contained in the flash memory. When all the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (10H) to the controller. (8) The 19th to 22nd bytes, which the target board receives from the controller, indicate the start address of the RAM region where subsequent data (e.g., a flash programming routine) should be stored. The 19th byte corresponds to bits 31–24 of the address, and the 22nd byte corresponds to bits 7–0 of the address. (9) The 23rd and 24th bytes, which the target board receives from the controller, indicate the number of bytes that will be transferred from the controller to be stored in the RAM. The 23rd byte corresponds to bits 15–8 of the number of bytes to be transferred, and the 24th byte corresponds to bits 7–0 of the number of bytes. (10) The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum value, add all these bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in Section 3.5.14. (11) The 26th byte, transmitted from the target board to the controller, is an acknowledge response to the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a receive error in the 19th to 25th bytes. If there was a receive error, the RAM Transfer routine sends back 18H and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 19th to 25th bytes must result in zero (with the carry dropped). If it is not zero, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. TMP1962F-44 TMP1962F10AXBG • The RAM storage start address must be within the range 0xFFFD_6000–0xFFFD_EFFF. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (10H) to the controller. (12) The 27th to mth bytes from the controller are stored in the on-chip RAM of the TMP1962F10AXBG. Storage begins at the address specified by the 19th–22nd bytes and continues for the number of bytes specified by the 23rd–24th bytes. (13) The (m+1)th byte is a checksum value. To calculate the checksum value, add the 27th to mth bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in Section 3.5.14. (14) The (m+2)th byte is a acknowledge response to the 27th to (m+1)th bytes. First, the RAM Transfer routine checks for a receive error in the 27th to (m+1)th bytes. If there was a receive error, the RAM Transfer routine sends back 18H and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. (15) Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 27th to (m+1)th bytes must result in zero (with the carry dropped). If it is not zero, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (10H) to the controller. If the (m+2)th byte was a normal acknowledge response, a branch is made to the address specified by the 19th to 22nd bytes in 32-bit ISA mode. 3.5.8 Show Flash Memory Sum Command See Table 3.7. (1) The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. (2) The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Flash Memory Sum command is 20H. (3) The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits x8H and returns to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined — they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 3.5 on page 37, the boot program echoes it back to the controller. When the Show Flash Memory Sum command was received, the boot program echoes back a value of 20H and then branches to the Show Flash Memory Sum routine. If the 3rd byte is not a valid command, the boot program sends back x1H to the controller and returns TMP1962F-45 TMP1962F10AXBG to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined — they hold the same values as the upper four bits of the previously issued command. (4) The Show Flash Memory Sum routine adds all the bytes of the flash memory together. The 5th and 6th bytes, transmitted from the target board to the controller, indicate the upper and lower bytes of this total sum, respectively. For details on sum calculation, see Section 3.5.13. (5) The 7th byte is a checksum value for the 5th and 6th bytes. To calculate the checksum value, add the 5th and 6th bytes together, drop the carry and take the two’s complement of the sum. Transmit this checksum value from the controller to the target board. (6) The 8th byte is the next command code. 3.5.9 Show Product Information Command See Table 3.8. (1) The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. (2) The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Product Information command is 30H. (3) The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits x8H and returns to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined — they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 3.5 on page 37, the boot program echoes it back to the controller. When the Show Flash Memory Sum command was received, the boot program echoes back a value of 30H and then branches to the Show Flash Memory Sum routine. If the 3rd byte is not a valid command, the boot program sends back x1H to the controller and returns to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined — they hold the same values as the upper four bits of the previously issued command. (4) The 5th to 8th bytes, transmitted from the target board to the controller, are the data read from addresses 0x0000_03F0–0x0000_03F3 in the flash memory. Software version management is possible by storing a software id in these locations. (5) The 9th to 20th bytes, transmitted from the target board to the controller, indicate the product name, which is “TX1962F10___” in ASCII code (where _ is a space). TMP1962F-46 TMP1962F10AXBG (6) The 21st to 24th bytes, transmitted from the target board to the controller, indicate the start address of the flash memory area containing the password, i.e., F4H, 03H, 00H, 00H. (7) The 25th to 28th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip RAM, i.e., 00H, 60H, FDH, FFH. (8) The 29th to 32nd bytes, transmitted from the target board to the controller, are dummy data (FFH, 6FH, FDH, FFH). (9) The 33rd to 36th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip RAM, i.e., FFH, FFH, FDH, FFH. (10) The 37th to 40th bytes, transmitted from the target board to the controller, are 00H, 70H, FDH and FFH. The 41st to 44th bytes, transmitted from the target board to the controller, are FFH, EFH, FDH and FFH. (11) The 45th and 46th bytes, transmitted from the target board to the controller, indicate the presence or absence of the security and protect bits and whether the flash memory is divided into blocks. Bit 0 indicates the presence or absence of the security bit; it is 0 if the security bit is available. Bit 1 indicates the presence or absence of the protect bits; it is 0 if the protect bits are available. If bit 2 is 0, it indicates that the flash memory is divided into blocks. The remaining bits are undefined. The 45th and 46th bytes are 01H, 00H. (12) The 47th to 50th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip flash memory, i.e., 00H, 00H, 00H, 00H. (13) The 51st to 54th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip flash memory, i.e., FFH, FFH, 0FH, 00H. (14) The 55th to 56th bytes, transmitted from the target board to the controller, indicate the number of flash blocks available, i.e., 08H, 00H. (15) The 57th to 92nd bytes, transmitted from the target board to the controller, contain information about the flash blocks. Flash blocks of the same size are treated as a group. Information about the flash blocks indicate the start address of a group, the size of the blocks in that group (in halfwords) and the number of the blocks in that group. The 57th to 65th bytes are the information about the 128-kbyte blocks (Block 0 to Block 7). See Table 3.8 for the values of bytes transmitted. (16) The 66th byte, transmitted from the target board to the controller, is a checksum value for the 5th to 65th bytes. The checksum value is calculated by adding all these bytes together, dropping the carry and taking the two’s complement of the total sum. (17) The 67th byte is the next command code. TMP1962F-47 TMP1962F10AXBG 3.5.10 Acknowledge Responses The boot program represents processing states with specific codes. Table 3.9 to Table 3.11 show the values of possible acknowledge responses to the received data. The upper four bits of the acknowledge response are equal to those of the command being executed. Bit 3 of the code indicates a receive error. Bit 0 indicates an invalid command error, a checksum error or a password error. Bit 1 and bit 2 are always 0. Receive error checking is not done in I/O Interface mode. Table 3.9 ACK Response to the Serial Operation Mode Byte Return Value Meaning 86H The SIO can be configured to operate in UART mode. (See Note) 30H The SIO can be configured to operate in I/O Interface mode. Note: If the serial operation mode is determined as UART, the boot program checks if the SIO can be programmed to the baud rate at which the operation mode byte was transferred. If that baud rate is not possible, the boot program aborts, without sending back any response. Table 3.10 ACK Response to the Command Byte Return Value x8H (See Note) Meaning A receive error occurred while getting a command code. x1H (See Note) An undefined command code was received. (Reception was completed normally.) 10H The RAM Transfer command was received. 20H The Show Flash Memory Sum command was received. 30H The Show Product Information command was received. Note: The upper four bits of the ACK response are the same as those of the previous command code. Table 3.11 ACK Response to the Checksum Byte Return Value Meaning 18H A receive error occurred. 11H A checksum or password error occurred. 10H The checksum was correct. TMP1962F-48 TMP1962F10AXBG 3.5.11 Determination of a Serial Operation Mode The first byte from the controller determines the serial operation mode. To use UART mode for communications between the controller and the target board, the controller must first send a value of 86H at a desired baud rate to the target board. To use I/O Interface mode, the controller must send a value of 30H at 1/16 the desired baud rate. Figure 3.9 shows the waveforms for the first byte. Start Point A bit 0 bit 1 Point B bit 2 bit 3 Point C bit 4 bit 5 bit 6 bit 7 Point D Stop UART (86H) tAB bit 0 Point A bit 1 tCD bit 2 bit 3 bit 4 Point B bit 5 bit 6 Point C bit 7 Point D I/O Interface (30H) tAB tCD Figure 3.9 Serial Operation Mode Byte After RESET is released, the boot program monitors the first serial byte from the controller, with the SIO reception disabled, and calculates the intervals of tAB, tAC and tAD. Figure 3.10 shows a flowchart describing the steps to determine the intervals of tAB, tAC and tAD. As shown in the flowchart, the boot program captures timer counts each time a logic transition occurs in the first serial byte. Consequently, the calculated tAB, tAC and tAD intervals are bound to have slight errors. If the transfer goes at a high baud rate, the CPU might not be able to keep up with the speed of logic transitions at the serial receive pin. In particular, I/O Interface mode is more prone to this problem since its baud rate is generally much higher than that for UART mode. To avoid such a situation, the controller should send the first serial byte at 1/16 the desired baud rate. The flowchart in Figure 3.11 shows how the boot program distinguishes between UART and I/O Interface modes. If the length of tAB is equal to or less than the length of tCD, the serial operation mode is determined as UART mode. If the legnth of tAB is greater than the length of tCD, the serial operation mode is determined as I/O Interface mode. Bear in mind that if the baud rate is too high or the timer operating frequency is too low, the timer resolution will be coarse, relative to the intervals between logic transitions. This becomes a problem due to inherent errors caused by the way in which timer counts are captured by software; consequently the boot program might not be able to determine the serial operation mode correctly. For example, the serial operation mode may be determined to be I/O Interface mode when the intended mode is UART mode. To avoid such a situation, when UART mode is utilized, the controller should allow for a time-out period within which it expects to receive an echo-back (86H) from the target board. The controller should give up the communication if it fails to get that echo-back within the alloted time. When I/O Interface mode is utilized, once the first serial byte has been transmitted, the controller should send the SCLK clock after a certain idle time to get an acknowledge response. If the received acknowledge response is not 30H, the controller should give up further communications. TMP1962F-49 TMP1962F10AXBG Start Initialize 16-bit Timer 0 (φT1 = 8/fc, counter cleared) Set TB0RG1 to 0xFFFF Prescaler is on. Point A High-to-low transition on serial receive pin? Yes 16-bit Timer 0 starts counting up Point B Low-to-high transition on serial receive pin? Yes Software-capture and save timer value (tAB) Point C High-to-low transition on serial receive pin? Yes Software-capture and save timer value (tAC) Point D Low-to-high transition on serial receive pin? Yes Software-capture and save timer value (tAD) 16-bit Timer 0 stops counting tAC ≥ tAD? Yes Make backup copy of tAD value Stop operation (infinite loop) Done Figure 3.10 Serial Operation Mode Byte Reception Flow TMP1962F-50 TMP1962F10AXBG Start tCD ← tAD − tAC Yes tAB > tCD? UART Mode I/O Interface Mode Figure 3.11 Serial Operation Mode Determination Flow 3.5.12 Password The RAM Transfer command (10H) causes the boot program to perform a password check. Following an echo-back of the command code, the boot program checks the contents of the 12-byte password area (0x4000_03F4 to 0x4000_03FF) within the flash memory. If all these address locations contain the same bytes of data other than FFH, a password area error occurs. In this case, the boot program returns an error acknowledge (11H) in response to the checksum byte (the 17th byte), regardless of whether the password sequence sent from the controller is all FFHs. The password sequence received from the controller (5th to 16th bytes) is compared to the password stored in the flash memory. Table 3.12 shows how they are compared byte-by-byte. All of the 12 bytes must match to pass the password check. Otherwise, a password error occurs, which causes the boot program to return an error acknowledge in response to the checksum byte (the 17th byte). Start Are all bytes the same? No Yes Are all bytes equal to FFH? Yes No Password area error Figure 3.12 Password Area Check Flow TMP1962F-51 Password area is normal. TMP1962F10AXBG Table 3.12 Relationship between Received Bytes and Flash Memory Locations 3.5.13 Received Byte Compared Flash Memory Data 5th byte Address 0x0000_03F4 6th byte Address 0x0000_03F5 7th byte Address 0x0000_03F6 8th byte Address 0x0000_03F7 9th byte Address 0x0000_03F8 10th byte Address 0x0000_03F9 11th byte Address 0x0000_03FA 12th byte Address 0x0000_03FB 13th byte Address 0x0000_03FC 14th byte Address 0x0000_03FD 15th byte Address 0x0000_03FE 16th byte Address 0x0000_03FF Calculation of the Show Flash Memory Sum Command The Show Flash Memory Sum command adds all 1024 kbytes of the flash memory together and provides the total sum as a halfword quantity. The sum is sent to the controller, with the upper eight bits first, followed by the lower eight bits. Example: A1H B2H For the interest of simplicity, assume the depth of the flash memory is four locations. Then the sum of the four bytes is calculated as: A1H + B2H + C3H + D4H = 02EAH C3H Hence, 02H is first sent to the controller, followed by EAH. D4H 3.5.14 Checksum Calculation The checksum byte for a series of bytes of data is calculated by adding the bytes together, dropping the carries, and taking the two’s complement of the total sum. The Show Flash Memory Sum command and the Show Product Information command perform the checksum calculation. The controller must perform the same checksum operation in transmitting checksum bytes. Example: Assume the Show Flash Memory Sum command provides the upper and lower bytes of the sum as E5H and F6H. To calculate the checksum for a series of E5H and F6H: (1) Add the bytes together. E5H + F6H = 1DBH (2) Drop the carry. (3) Take the two’s complement of the sum, and that is the checksum byte. 0 – DBH = 25H TMP1962F-52 TMP1962F10AXBG 3.5.15 General Boot Program Flowchart Figure 3.13 shows an overall flowchart of the boot program. Single Boot program starts Initialize Get SIO operation mode data SIO Operation Mode? UART I/O Interface Cannot be set Baud rate setting? Can be set Program UART mode and baud rate Set I/O Interface Mode ACK data ← Received data (30H) ACK data ← Received data (86H) (Send 30H) Normal response (Send 86H) Normal response Stop operation Prepare to get a command ACK data ← ACK data & 0xF0 Receive routine Get a command Yes ACK data ← ACK data 0x08 Transmission routine (Send x8H: Receive error) Show Flash Memory Sum? Show Product Information? ACK data ← Received data (10H) Yes (20h) ACK data ← Received data (20H) Yes (30h) ACK data ← Received data (30H) ACK data ← ACK data | 0x01 Transmission routine (Send 10H: normal response) Transmission routine (Send 20H: normal response) Transmission routine (Send 30H: normal response) Transmission routine (Send x1H: Command error) RAM Transfer processing Show Flash Memory Sum processing Show Product Information processing Receive error? No normally RAM Transfer? Yes (10h) Processed normally? Yes normally Jump to RAM Figure 3.13 Overall Boot Program Flow TMP1962F-53 Command error TMP1962F10AXBG 3. 3.6 On-Board Programming and Erasure The TMP1962F10AXBG flash memory is command set compatible with the JEDEC EEPROM standard, with a few exceptions. In User Boot mode and Single Boot mode (the RAM Transfer command), the flash memory can be programmed and erased by the CPU executing software commands. It is the user’s responsibility to create a program/erase routine. Because the flash memory can not be read while it is being programmed or erased, the program/erase routine must be executed out of the on-chip RAM or an external memory device. 3.6.1 Key Features The TMP1962F10AXBG flash memory commands are in principle compatible with the standard JEDEC commands. For program/erase operations, the system can issue a command sequence to the flash memory by using CPU instructions such as LD. After the command sequence is written, the flash memory does not require the system to provide further controls or timings. The flash memory initiates the embedded program or erase algorithm automatically. The entire flash memory or one or more flash blocks can be erased at a time. Table 3.14 Flash Memory Features Feature Auto Program Auto Chip Erase Auto Block Erase Auto Multi-Block Erase Write operation status Security feature Block protection Description Programs and verifies the desired addresses word by word automatically. Erases and verifies the entire memory array automatically. Erases and verifies all memory locations in the selected block automatically. Erases and verifies all memory locations in multiple selected blocks automatically. Provides several status bits such as the Data Polling bit and Toggle bit, which can be used to determine whether a program or erase operation is complete or in progress. Prevents intrusive access to the flash memory while in Programmer mode. When the security feature is turned off, the entire memory array is erased and verified automatically, regardless of whether a given block is protected or not. Disables both program and erase operations in any block. Bear in mind that, due to the on-chip CPU interface, the TMP1962F10AXBG uses addresses different from those of the standard flash command sequences. Unless otherwise noted, programming is done word by word; thus the word load instruction should be used to write to the flash array. TMP1962F-54 TMP1962F10AXBG 3.6.2 Block Architecture 0xxxxx_0000 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 128 kbytes 0xxxxF_FFFF 128 kbytes x: Depends on the TMP1962F10AXBG operation mode Figure 3.16 Flash Memory Block Architecture 3.6.3 CPU-to-Flash Interface Figure 3.17 illustrates the internal interface between the CPU and the flash memory in on-board programming modes. The diagram does not show the actual logic network; instead it is only a conceptual depiction of the CPU-to-flash interface. Single-Chip mode: 0x1FC0_0000 – 0x1FCF_FFFF (physical address) Single Boot mode: 0x4000_0000 – 0x400F_FFFF (physical address) CPU Operation Mode A31 – A17 Flash Memory Decoder CE (1024 kB) A16 – A2 AD14 – AD0 D31 – D0 DQ31 – DQ0 WR WE RD OE CPU RESET RESET Register RDY_ BSY Figure 3.17 Internal CPU-to-Flash Interface TMP1962F-55 TMP1962F10AXBG 3.6.4 Read Mode and Embedded Operation Mode The flash memory of the TMP1962F10AXBG has the following two modes of operation: • Read mode in which array data is read • Embedded Operation mode in which the flash array is programmed or erased The flash memory enters Embedded Operation mode when a valid command sequence is executed in Read mode. In Embedded Operation mode, array data can not be read. 3.6.5 Reading Array Data The flash memory is automatically set to reading array data upon CPU reset after device power-up and after an embedded operation is successfully completed. If an embedded operation terminated abnormally or the flash memory is required to return to the Read mode, the Read/Reset command (software reset) or hardware reset is used. 3.6.6 Writing Commands The operations of the flash memory are selected by commands or command sequences written into the internal command register. This uses the same mechanism as for JEDEC-standard EEPROMs. Commands are made up of data sequences written at specific addresses via the command register. See Table 3.16 on page 63 for the list of command sequences. The command sequence being written can be canceled by issuing the Read/Reset command between sequence cycles. The Read/Reset command clears the command register and resets the flash memory to Read mode. Invalid command sequences also cause the flash memory to clear the command register and return to Read mode. 3.6.7 Reset • Read/Reset command (software reset) The flash memory does not return to Read mode if an embedded operation terminated abnormally. In this case, the Read/Reset command must be issued to put the flash memory back in Read mode. The Read/Reset command may also be written between sequence cycles of the command being written to clear the command register. • Hardware reset ( RESET input) As shown in Figure 3.17, the flash memory has a reset pin, which is connected to the reset signal of the CPU. When the system drives the RESET pin to VIL or when certain events such as a watchdog timer time-out causes a CPU reset, the flash memory immediately terminates any operation in progress and is reset to Read mode. The Read/Reset command is also tied to the RESET pin to reset the flash memory to Read mode. The embedded operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. For a description of the hardware reset operation, see Section 3.3.2, Reset Operation. When a valid reset is achieved, the CPU reads the Reset exception vector from the flash memory and services the Reset exception. TMP1962F-56 TMP1962F10AXBG 3.6.8 Auto Program Command A bit must be programmed to change its state from a 1 to a 0. A bit can not be programmed from a 0 back to a 1. Only an erase operation can change a 0 back to a 1. In User Boot mode and the RAM Transfer command of Single Boot mode, the Auto Program command programs the desired addresses word by word. The Auto Program command requires four bus cycles; the program address and data are written in the fourth cycle, upon completion of which the program operation will commence. As programming is performed on a word-by-word basis, the program address must be a multiple of four. Writing data shorter than a 32-bit word requires special considerations for the bits that are not to be altered. The word in the memory does not need to be in the erased state prior to programming. If the word is in the erased state, a 32-bit write must be performed, with all the bits not to be altered set to 1. Examples: • When a word location is in the erased state To program the least-significant byte of that word to 55H, 0xFFFF_FF55 must be written to the word address. Note : The superscription of data cannot be done in the flash memory. The Auto Program command executes a sequence of internally timed events to program the desired bits of the addressed memory word and verify that the desired bits are sufficiently programmed. The system can determine the status of the programming operation by using write status flags (see Table 3.19 on page 65). Any commands written during the programming operation are ignored. A hardware reset immediately terminates the programming operation. The programming operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. The block protection feature disables programming operations in any block. If an attempt is made to program a protected block, the Auto Program command does nothing; the flash memory returns to Read mode in approximately 3 µm after the completion of the fourth bus cycle of the command sequence. When the embedded Auto Program algorithm is complete, the flash memory returns to Read mode. If any failure occurs during the programming operation, the flash memory remains locked in Embedded Operation mode. The system can determine this status by using write status flags. To put the flash memory back in Read mode, use the Read/Reset command to reset the flash memory or a hardware reset to reset the whole chip. In case of a programming failure, it is recommended to replace the chip or discontinue the use of the failing flash block. 3.6.9 Auto Chip Erase Command The Auto Chip Erase command requires six bus cycles. The flash area is partitioned into two areas, that are Block 0 to Block 3 (Flash 0) and Block 4 to Block 7 (Flash 1). The chip erase operation is performed for individual area. Set A[19] (address 19) = 0 for Flash 0, and A[19] = 1 for Flash 1 by each bus cycle. After completion of the sixth bus cycle, the Auto Chip Erase operation will commence immediately. The embedded Auto Chip Erase algorithm automatically preprograms the entire memory for an all-0 data pattern prior to the erase; then it automatically erases and verifies the entire memory for an all-1 data pattern. The system can determine the status of the chip erase operation by using write status flags (see TMP1962F-57 TMP1962F10AXBG Table 3.19 on page 65). Any commands written during the chip erase operation are ignored. A hardware reset immediately terminates the chip erase operation. The chip erase operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. The block protection feature disables erase operations in any block. The Auto Chip Erase algorithm erases the unprotected blocks and ignores the protected blocks. If all the blocks are protected, the Auto Chip Erase command does nothing; the flash memory returns to Read mode in approximately 100 µm after the completion of the sixth bus cycle of the command sequence. When the embedded Auto Chip Erase algorithm is complete, the flash memory returns to Read mode. If any failure occurs during the erase operation, the flash memory remains locked in Embedded Operation mode. The system can determine this status by using write status flags. To put the flash memory back in Read mode, use the Read/Reset command to reset the flash memory or a hardware reset to reset the whole chip. In case of an erase failure, it is recommended to replace the chip or discontinue the use of the failing flash block. The failing block can be identified by means of the Block Erase command. 3.6.10 Auto Block Erase and Auto Multi-Block Erase Commands The Auto Block Erase command requires six bus cycles. A time-out begins from the completion of the command sequence. After a time-out, the erase operation will commence. The embedded Auto Block Erase algorithm automatically preprograms the selected block for an all-0 data pattern, and then erases and verifies that block for an all-1 data pattern. During the time-out period, additional block addresses and Auto Block Erase commands may be written. Multi-block is selectable in either Flash 0 area or Flash 1 area. Any command other than Auto Block Erase during the time-out period resets the flash memory to Read mode. The block erase time-out period is 50 µm. The system may read DQ3 to determine whether the time-out period has expired. The block erase timer begins counting upon completion of the sixth bus cycle of the Auto Block Erase command sequence. The system can determine the status of the erase operation by using write status flags (see Table 3.19 on page 65). Any commands written during the block erase operation are ignored. A hardware reset immediately terminates the block erase operation. The block erase operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. The block protection feature disables erase operations in any block. The Auto Block Erase algorithm erases the unprotected blocks and ignores the protected blocks. If all the selected blocks are protected, the Auto Block Erase algorithm does nothing; the flash memory returns to Read mode in approximately 100 µm after the final bus cycle of the command sequence. When the embedded Auto Block Erase algorithm is complete, the flash memory returns to Read mode. If any failure occurs during the erase operation, the flash memory remains locked in Embedded Operation mode. The system can determine this status by using write status flags. To put the flash memory back in Read mode, use the Read/Reset command to reset the flash memory or a hardware reset to reset the whole chip. In case of an erase failure, it is recommended to replace the chip or discontinue the use of the failing flash block. If any failure occurred during the multi-block erase operation, the failing block can be identified by running Auto Block Erase on each of the blocks selected for multi-block erasure. TMP1962F-58 TMP1962F10AXBG 3.6.11 Block Protect Command The block protection feature disables both program and erase operations in any block. After completion of the seventh bus write cycle, FCLS<bit2> is 0 during Block Protect operation, and 1 after Block Protect operation. Table 3.15 Effects of the Program and Erase Commands on the Protected Blocks Command Operation Program command on a protected block No programming operation is performed, and the flash memory automatically returns to Read mode. Block Erase command on a protected block No erase operation is performed, and the flash memory automatically returns to Read mode. Chip Erase command when all the blocks are protected No erase operation is performed, and the flash memory automatically returns to Read mode. Chip Erase command when any blocks are protected Only the unprotected blocks are erased. Upon completion, the flash memory automatically returns to Read mode. Multi-Block Erase command when any blocks are protected Only the unprotected blocks are erased. Upon completion, the flash memory automatically returns to Read mode. Any commands written during the Block Protect algorithm are ignored. A hardware reset immediately terminates the block protect operation. The Block Protect command that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence. 3.6.12 Block Unprotect Operation Block unprotect operation is performed for individual area (Flash 0 and Flash 1). Set A[19] in accordance to the area required for block unprotect by the bus cycle. After completion of the seventh bus write cycle, FCLS<bit2> is 0 during block unprotect operation, and 1 after block unprotect operation. Any commands written during the Block Unprotect algorithm are ignored. The hardware reset immediately terminates the block unprotect operation. The Block Protect command should be reinitiated once the flash memory is ready to accept another command sequence. Use the Verify Block Protect command to verify the protect status of a block. 3.6.13 Verify Block Protect Command The Verify Block Protect command is used to verify the protect status of a block. Verify Block Protect is a four-bus-cycle operation. The address of the block to be verified is given in the fourth cycle. Any address within the block range will suffice, provided A0 = A1 = A2 = A3 = 0, A4 = 1 and A6 = 0. To get correct data, a 32-bit read must be performed. Use the last read as valid data. If the selected block is protected, a value of 0x0000_0001 is returned. If the selected block is not protected, a value of 0x0000_0000 is returned. Following the fourth bus cycle, an additional block address may be read. The Verify Block Protect command does not return the flash memory to Read mode. Either the Read/Reset command or a hardware reset is required to reset the flash memory to Read mode or to write the next command. TMP1962F-59 TMP1962F10AXBG 3.6.14 Write Operation Status As shown in Table 3.19, the flash memory provides several flag bits to determine the status of an embedded operation: DQ7, DQ5 and DQ3. These status bits can be read during an embedded operation using the same timing as for Read mode. The flash memory automatically returns to Read mode when an embedded operation completes. The status of an embedded program operation can be monitored to determine whether the hardware sequence flag during an embedded operation, or the data read after completion of an embedded operation match the cell data. Read of the hardware sequence flag is performed by checking start of embedded operation (FLCS<bit2>=0). During the embedded program operation, the system must provide the program address (with A0 = 0 and A1 = 0) to read valid status information. During the embedded erase operation, the system must provide an address (with A0 = 0 and A1 = 0) within any of the blocks selected for erasure to read valid status information. • DQ7 (Data Polling) The Data Polling bit, DQ7, indicates to the host system the status of the embedded operation. Data Polling is valid after the final bus write cycle of an embedded command sequence. When the embedded Program algorithm is in progress, an attempt to read the flash memory will produce the complement of the data last written to DQ7. Upon completion of the embedded Program algorithm, an attempt to read the flash memory will produce the true data last written to DQ7. Therefore, the system can use DQ7 to determine whether the embedded Program algorithm is in progress or complete. When the embedded Erase algorithm is in progress, an attempt to read the flash memory will produce a 0 at the DQ7 output. Upon completion of the embedded Erase algorithm, the flash memory will produce a 1 at the DQ7 output. If there is a failure during an embedded operation, DQ7 continues to output the same value. Thus, DQ7 must always be polled in conjunction with the Exceeded Timing Limits (DQ5) flag. Figure 3.21 shows the DQ7 polling algorithm. The flash memory disables address latching when an embedded operation is complete. Data polling must be performed with a valid programmed address or an address within any of the non-protected blocks selected for erasure. • DQ5 (Exceeded Timing Limits) DQ5 produces a 0 while the program or erase operation is in progress normally. DQ5 produces a 1 to indicate that the program or erase time has exceeded the specified internal limit. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition also appears if the system tries to program a 1 to a location that was previously programmed to a 0. Only an erase operation can change a 1 back to a0. In this case, the embedded Program algorithm halts the operation. Once the operation has exceeded the timing limits, DQ5 will indicate a 1. Note that this is not a device failure condition since the flash memory was used incorrectly. Under both these conditions, the flash memory remains locked in Embedded Operation mode. The system must issue the Read/Reset command to return the flash memory to Read mode. TMP1962F-60 TMP1962F10AXBG • DQ3 (Block Erase Timer) After the completion of the sixth bus cycle of the Auto Block Erase command sequence, the block erase time-out window of 50 µm begins. The erase operation will begin after the time-out has expired. When the time-out is complete and the erase operation has begun, DQ3 switches from 0 to 1. If DQ3 is 0, the flash memory will accept additional Auto Block Erase commands. Each time an Auto Block Erase command is written, the time-out window is reset. To ensure that the command has been accepted, the system should check DQ3 prior to and following each Auto Block Erase command. If DQ3 is 1 on the second status check, the command might not have been accepted. 3.6.15 Flash Control/Status Register This is an 8-bit register that indicates the Ready/Busy status of an embedded algorithm and controls the security feature. 7 FLCS Bit Symbol (0xFFFF_E520) Read/Write Reset Value Function 6 5 4 3 2 FLRMSK RDY/BSY W R 0 1 Ready/ Busy Flash reset mask enable 0: Embedded algorithm is in progress. 1: Reset a flash control circuitry 1 0 0 Must be written as “0”. 1: Embedded algorithm is complete. 0: Unreset a flash control circuitry Figure 3.18 Flash Control/Status Register • Bit 2: Ready/Busy Flag Bit( In Programmer mode, the ALE pin functions as the RDY/ BSY pin. The host system can monitor the state of this pin to determine whether an embedded algorithm is in progress or complete. The CPU can poll the RDY/BSY bit in the FLCS register for the same purpose. The RDY/BSY bit is cleared to 0 when the flash memory is actively erasing or programming. The RDY/BSY bit is set to 1 when an embedded operation has completed and the flash memory is ready to accept the next command. If any failure occurs during the program or erase operation, this bit remains cleared. A hardware reset sets this bit. The RDY/BSY bit is cleared upon completion of the final bus write cycle of an embedded operation command, with one exception. In the case of the Auto Block Erase command, this bit is cleared after the time-out has expired. Any command is ignored while the RDY/BSY bit is cleared. TMP1962F-61 TMP1962F10AXBG • Bit 7: Flash Reset Mask Bit An interval of 30 µs (T.B.D.) is allowed to elapse before starting the processor core operation after a reset upon power on, which is required to initialize an on-chip flash control circuitry. SYSRDY is signaled to indicate the start of the processor core operation from outside of TMP1962. After the processor core is reset, SYSRDY switches from Low to High. The reset operation after power on (do not power off) is controlled by bit 7 (FLRMSK) of the flash control/status register (FLCS) in the flash control part. When the FLRMSK bit is 0 (initial value), the flash control circuitry is always initialized. When the FLRMSK bit is set to 1, the flash control circuitry is not initialized. (Read of the on-chip flash memory is performed correctly.) In this case, the interval of 30 µs (T.B.D.) is not required for the flash control circuitry to be stable after a reset. Immediately the processor core starts operation, and the SYSRDY signal switches to High. The value set to the FLRMSK bit is retained until power off. Set FLRMSK=1 commonly by initial setting afterreset. Note: The Flash Control/Status register must be accessed as a 32-bit quantity. 3.6.16 Flash Security The TMP1962F10AXBG flash memory supports not only on-board programming but also programming using a general-purpose programmer. Therefore, the TMP1962F10AXBG flash memory provides a security feature to prevent intrusive access to the flash memory while in Programmer mode. The TMP1962F10AXBG is secured by all eight blocks being protected, and the contents of a flash memory can not be read by a programmer. • Securing the flash (Disabling read accesses) Securing the flash memory disables a general-purpose programmer to read its contents. To turn on the security feature, once programming is complete, protect all eight blocks. That secures the flash memory. If one of eight blocks is unprotected, the flash memory is unsecured. In on-board operating modes, the CPU can read the flash memory even if the security is on. When the security is ON, any reads by programming equipment will always return a word-length value of 0x0098. • Unsecuring the flash (Enabling read accesses) The security feature is designed to disable reads of the flash memory by programming equipment. While the TMP1962F10AXBG is soldered on a board, the CPU can always read the flashmemory, regardless of whether or not the security is on. Since the flash memory is placed under control of a user’s application program in on-board operating modes, it is not easy for third parties to perform intrusive access to the flash memory. Therefore, within the confines of a board, the flash memory does not need to be secured. To turn off the security feature, unprotect eight blocks. Unsecuring the flash memory enables the flash memory erase operation to occur before turning off the security feature. After a flash memory has been erased, the flash memory unsecure operation is completed by erasing the Block Protect bit. TMP1962F-62 TMP1962F10AXBG 3.6.17 Command Definition Table 3.16 On-Board Programming Mode Command Definition Command Cycles Sequence Required 1st Cycle (Write) Addr Data 2nd Cycle (Write) Bus Cycles 3rd Cycle (Write) Addr Data Addr 4th Cycle (Read/Write) 5th Cycle (Read/Write) Data Addr Data Addr Data Read/Reset 1 0xXXXX F0H Read/Reset 3 0x5554 AAH 0xAAA8 55H 0x5554 F0H RA RD Auto Program 4 0x5554 AAH 0xAAA8 55H 0x5554 A0H PA PD Auto Chip Erase 6 0x5554 AAH 0xAAA8 55H 0x5554 80H 0x5554 AAH 0xAAA8 55H Auto Block Erase 6 0x5554 AAH 0xAAA8 55H 0x5554 80H 0x5554 AAH 0xAAA8 55H Block Protect 7 0x5554 AAH 0xAAA8 55H 0x5554 9AH 0x5554 AAH 0xAAA8 55H Block Unprotect 7 0x5554 AAH 0xAAA8 55H 0x5554 6AH 0x5554 AAH 0xAAA8 55H ID Read/Block Protect Verify 4 0x5554 AAH 0xAAA8 55H 0x5554 90H IA/BPA ID/BD (Continued from above) Bus Cycles Command Cycles Sequence Required 6th Cycle (Write) Addr Data 6 0x5554 10H Auto Block Erase 6 BA 30H Block Protect 7 0x5554 Block Unprotect 7 0x5554 Auto Security On (Note 1) 4 Read/Reset 1 Read/Reset 3 Auto Program 4 Auto Chip Erase 7th Cycle (Write) Addr Data 9AH BPA 9AH 6AH 0x5554 6AH Note 1: After every bus write cycle, execute SYNC and NOP in sequence. Note 2: Set the value corresponding the flash memory address to 16-bit through 19-bit in every bus write cycle. TMP1962F-63 TMP1962F10AXBG The addresses to be provided by the CPU are shown below. Table 3.17 Addresses Provided by the CPU CPU Addresses: A23–A0 Command Address A23–A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 0xXXX0 0x0000 0xAAA8 Flash memory block 0x5554 • A5 A4 A3 A2 A1 A0 X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 F0H, AAH, 55H, A0H, 80H, 10H, 30H: Command data. Write command data as a byte quantity. • RA: Read Address RD: Read Data • PA: Program Address PD: Program Data The address must be a multiple of four. Write data on a word-by-word basis. • BA: Block Address (BA0–BA6) Refer to Table 3.18. • BPA: Verify Block Protect Address BD: Block Protect Data Refer to Table 3.18. The address of the block to be verified can be any of the addresses within the block, with A6 = 0, A4 = 1, A3 = 0, A1 = 0 and A0 = 0. If a block is protected, a value of 0x0000_0001 will be returned. If a block is not protected, a value of 0x0000_0000 will be returned. • IA: ID Read Address • ID: ID Data TMP1962F-64 TMP1962F10AXBG Table 3.18 Block Erase Addresses User Boot Mode Block-0 Block-1 Flash0 Block-2 Block-3 Block-4 Block-5 Flash1 Block-6 Block-7 0x1FC0_0000 - 0x1FC1_FFFF (or 0x4000_0000 - 0x4001_FFFF) 0x1FC2_0000 - 0x1FC3_FFFF (or 0x4002_0000 - 0x4003_FFFF) 0x1FC4_0000 - 0x1FC5_FFFF (or 0x4004_0000 - 0x4005_FFFF) 0x1FC6_0000 - 0x1FC7_FFFF (or 0x4006_0000 - 0x4007_FFFF) 0x1FC8_0000 - 0x1FC9_FFFF (or 0x4008_0000 - 0x4009_FFFF) 0x1FCA_0000 - 0x1FCB_FFFF (or 0x400A_0000 - 0x400B_FFFF) 0x1FCC_0000 - 0x1FCD_FFFF (or 0x400C_0000 - 0x400D_FFFF) 0x1FCE_0000 - 0x1FCF_FFFF (or 0x400E_0000 - 0x400E_FFFF) Boot Mode A19 A18 A17 0x1FC0_0000 - 0x1FC1_FFFF 128 kbyte 0 0 0 0x1FC2_0000 - 0x1FC3_FFFF 128 kbyte 0 0 1 0x1FC4_0000 - 0x1FC5_FFFF 128 kbyte 0 1 0 0x1FC6_0000 - 0x1FC7_FFFF 128 kbyte 0 1 1 0x1FC8_0000 - 0x1FC9_FFFF 128 kbyte 1 0 0 0x1FCA_0000 - 0x1FCB_FFFF 128 kbyte 1 0 1 0x1FCC_0000 - 0x1FCD_FFFF 128 kbyte 1 1 0 0x1FCE_0000 - 0x1FCF_FFFF 128 kbyte 1 1 1 The address of the block to be erased can be any of the addresses within that block with A0=0 and A1=0. Example: To select BA0 in User Boot mode, provide any address in the range between 0x1FC0_0000 and 0x1FC1_FFFF. Table 3.19 Write Status Flags Status D7 (DQ7) D5 (DQ5) D3 (DQ3) Auto Program Embedded operation in progress Time-out in embedded operation DQ7 0 0 Auto Erase (during the time-out window) 0 0 0 Auto Erase 0 0 1 DQ7 1 1 0 1 1 Auto Program Auto Erase Note: D31–D8, D6, D4 and D2–D0 are don’t-cares. TMP1962F-65 TMP1962F10AXBG 3.6.18 Embedded Algorithms Start Auto Program Command Sequence (Shown below) Data Polling Bit (Read as a word quantity) Address = Address + 4 (Word-by-word) No Last Address? Yes Auto Program Done Auto Program Command Sequence (Address/Data) 0x5554 / 0xAA 0xAAA8 / 0x55 0x5554 / 0xA0 Program Address (A1 = A0 = 0) / Program Data (Word-by-word) Figure 3.19 Auto Program Operation TMP1962F-66 TMP1962F10AXBG Start Auto Erase Command Sequence (Shown below) Data Polling Bit (Read as a word quantity) Auto Erase Done Auto Chip Erase Command Sequence (Address/Data) Auto Block/Multi-Block Erase Command sequence (Address/Data) 0x5554 / 0xAA 0x5554 / 0xAA 0xAAA8 / 0x55 0xAAA8 / 0x55 0x5554 / 0x80 0x5554 / 0x80 0x5554 / 0xAA 0x5554 / 0xAA 0xAAA8 / 0x55 0xAAA8 / 0x55 0x5554 / 0x10 Block Address / 0x30 Block Address / 0x30 Block Address / 0x30 Figure 3.20 Auto Erase Operations TMP1962F-67 Additional addresses for Auto Multi-Block Erase (each within 50 µs) TMP1962F10AXBG Start Read a word. Addr = VA (VA: Valid Address) DQ7 = Data ? Yes No No DQ5 = 1 ? Yes Read a word Addr = VA DQ7 = Data ? Yes No Read a word. Addr. = VA Compare with 32-bit quantity. Fail Figure 3.21 Data Polling (DQ7) Algorithm TMP1962F-68 Pass TMP1962F10AXBG 4. Electrical Characteristics The letter x in equations presented in this chapter represents the cycle period of the fsys clock selected through the programming of the SYSCR1.SYSCK bit. The fsys clock may be derived from either the high-speed or low-speed crystal oscillator. The programming of the clock gear function also affects the fsys frequency. All relevant values in this chapter are calculated with the high-speed (fc) system clock (SYSCR1.SYSCK = 0) and a clock gear factor of 1/fc (SYSCR1.GEAR[1:0] = 00). 4.1 Absolute Maximum Ratings Parameter Supply voltage Input voltage Low-level output current Per pin Symbol Rating VCC2 (Core) −0.3 to 3.6 VCC3 (I/O) −0.3 to 4.0 AVCC (A/D) −0.3 to 3.6 FVCC3 (L1 Pin) −0.3 to 4.0 VIN −0.3 to VCC + 0.3 IOL 5 Unit V V Total ΣIOL 50 Per pin IOH −5 Total ΣIOH 50 Power dissipation (Ta = 85°C) PD 600 mW Soldering temperature (10 s) TSOLDER 260 °C Storage temperature TSTG −65 to 150 °C High-level output current Operating temperature Write/erase cycles Except during flash W/E TOPR During flash W/E −20 to 85 mA °C 10 to 60 NEW 100 cycle VCC2 = DVCC21 = DVCC22 = FVCC2 = CVCC2, VCC3 = DVCC3n (n = 1 to 4), AVCC = AVCC31 = AVCC32, VSS = DVSS = FVSS = AVSS = CVSS Note: Absolute Maximum Ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manufacturer should design so that no Absolute Maximum Ratings value is exceeded with respect to current, voltage, power dissipation, temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning. TMP1962F-69 2006-02-21 TMP1962F10AXBG 4.2 DC Electrical Characteristics (1/4) Ta = –20 to 85°C Parameter Supply voltage FVCC2 = CVCC2 Symbol DVCC2m (m = 1 to 2) = DVCC21 = DVCC22 DVCC3n FVSS = CVSS = DVSS = 0 V (n = 1 to 4) FVCC3 P7-P9 (Used as a port) VIL1 Conditions Min Unit fosc = 10 to 13.5 MHz fsys = 3.75 to 40.5 MHz 2.2 2.7 fsys = 3.75 to 40.5 MHz 1.65 3.3 fsys = 3.75 to 40.5 MHz 2.9 PLLON, INTLV = “H” V 3.6 2.7 V ≤ AVCC32 ≤ AVCC31 ≤ 3.5 V 0.3 AVCC31 1.65 ≤ AVCC32 ≤ < 2.7 V 0.3 AVCC32 PA-PC, PD0-PD6, Low-level input voltage Max 1.65 V ≤ DVCC3n ≤ 3.3 V (n = 1 to 4) P0-P6, PE0-PE2, PF2-PF7, Typ (Note 1) VIL2 PG-PH, PI7, 0.3 DVCC3n 2.2 V ≤ DVCC2m ≤ 2.7 V (m = 1 to 2) 0.2 DVCC2m PJ1-PJ4, PL-PP 2.7 V ≤ DVCC3n ≤ 3.3 V (n = 1 to 4) PD7, PE3-PE7, PF0-PF1, PI0-PI6, −0.3 0.15 DVCC3n V PJ0, PK, PLLOFF , RSTPUP, RESET DRESET , DBGE VIL3 SDI/ DINT , TCK, TMS, 1.65 V ≤ DVCC3n < 2.7 V (n = 1 to 4) 0.1 DVCC3n 2.2 V ≤ DVCC2m ≤ 2.7 V (m = 1 to 2) 0.1 DVCC2m TDI, TRST NMI , BW0, BW1 X1 VIL4 2.2 V ≤ CVCC2 ≤ 2.7 V 0.1 CVCC2 Note 1: Ta = 25°C, DVCC3n = 3.0 V, DVCC2m = 2.5 V, AVCC3 = 3.3 V, unless otherwise noted. TMP1962F-70 2006-02-21 TMP1962F10AXBG 4.3 DC Electrical Characteristics (2/4) Ta = –20 to 85°C Parameter P7-P9 (Used as a port) Symbol 2.7 V ≤ AVCC32 ≤ AVCC31 ≤ 3.5 V VIH1 1.65 ≤ AVCC32 < 2.7 V P0-P6, High-level input voltage PA-PC, PD0-PD6, PE0-PE2, PF2-PF7, Conditions Min Typ. (Note 1) Max Unit 0.7 AVCC31 0.7 AVCC32 1.65 V ≤ DVCC3n ≤ 3.3 V (n = 1 to 4) 0.7 DVCC3n 2.2 V ≤ DVCC2m ≤ 2.7 V (m = 1 to 2) 0.8 DVCC2m VIH2 PG-PH, PI7, PJ1-PJ4, PL-PP PD7, PE3-PE7, V PF0-PF1, PI0-PI6, 2.7 V ≤ DVCC3n ≤ 3.3 V (n = 1 to 4) PJ0, PK, PLLOFF , RSTPUP, RESET DRESET , DBGE 0.85 DVCC3n DVCC2m + 0.3 VIH3 SDI/ DINT , TCK, TMS, 1.65 V ≤ DVCC3n < 2.7 V (n = 1 to 4) 0.9 DVCC3n TDI, TRST 2.2 V ≤ DVCC2m ≤ 2.7 V (m = 1 to 2) 0.9 DVCC2m DVCC3n + 0.3 NMI , BW0, BW1 X1 VIH4 2.2 V ≤ CVCC2 ≤ 2.7 V 0.9 CVCC2 DVCC3n ≥ 2.7 V IOL = 2 mA 0.4 0.2 DVCC3n Low-level output voltage VOL IOL = 500 µA DVCC3n < 2.7 V ≤ 0.4 DVCC2m ≤ 2.7 V 0.2 DVCC2 ≤ 0.4 IOH = −2 mA High-level output voltage VOH IOH = −500 µA DVCC3n ≥ 2.7 V 2.4 DVCC3n < 2.7 V 0.8 DVCC3n DVCC2m ≤ 2.7 V 0.8 DVCC2 V Note 1: Ta = 25°C, DVCC3n = 3.0 V, DVCC2m = 2.5 V, AVCC3 = 3.3 V, unless otherwise noted. TMP1962F-71 2006-02-21 TMP1962F10AXBG 4.4 DC Electrical Characteristics (3/4) Ta = –20 to 85°C Parameter Symbol Conditions Min Typ. (Note 1) Max 0.02 ±5 Unit 0.0 ≤ VIN ≤ DVCC2m (m = 1 to 2) Input leakage current ILI 0.0 ≤ VIN ≤ DVCC3n (n = 1 to 4) 0.0 ≤ VIN ≤ AVCC31 0.0 ≤ VIN ≤ AVCC32 0.2 ≤ VIN ≤ DVCC2m − 0.2 (m = 1 to 2) µA 0.2 ≤ VIN ≤ DVCC3n − 0.2 (n = 1 to 4) Output leakage current ILO Power-down voltage (STOP mode RAM backup) VSTOP 0.2 ≤ VIN ≤ AVCC32 − 0.2 VIL2 = 0.2DVCC2m, VIL3 = 0.1DVCC2m (DVCC2) VIH2 = 0.8DVCC2m, VIH3 = 0.9DVCC2m Pull-up resister at Reset RRST 2.2 V ≤ DVCC21 ≤ 2.7 V 20 50 2.7 V ≤ DVCC3n ≤ 3.3 V (n = 2, 4) 0.4 0.9 0.05 0.2 ≤ VIN ≤ AVCC31 − 0.2 2.2 ±10 2.7 V 240 kΩ Schmitt W Idth PD7, PE3-PE7, PF0-PF1, PI0-PI6, PJ0, PK, PLLOFF , RSTPUP, RESET , DRESET , DBGE , SDI/ DINT , TCK, TMS, VTH V 1.65 V ≤ DVCC3n < 2.7 V (n = 2, 4) 2.2 V ≤ DVCC2m ≤ 2.7 V (m = 1 to 2) 0.3 0.6 DVCC3n = 3.0 V ±0.3 V (n = 2 to 4) 15 50 100 DVCC3n = 2.5 V ±0.2 V (n = 2 to 4) 20 50 240 DVCC3n = 2.0 V ±0.2 V (n = 2 to 4) 25 160 600 TDI, TRST , NMI , BW0, BW1 Programmable pull-up/ pull-down resistor P32-P37,P40-P43 KEY0-KEYD, DRESET, PKH DBGE , SDI/ DINT , TCK, TMS, TDI, TRST Pin capacitance (Except power supply pins) CIO fc = 1 MHz 10 kΩ pF Note 1: Ta = 25°C, DVCC3n = 3.0 V, DVCC2m = 2.5 V, AVCC3 = 3.3 V, unless otherwise noted. TMP1962F-72 2006-02-21 TMP1962F10AXBG 4.5 DC Electrical Characteristics (4/4) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ± 0.3 V, DVCC3n = 3.0 V ± 0.3 V, AVCC3m = 3.3 V ± 0.2 V Ta = -20 to 85°C (n = 1 to 4, m = 1, 2) Parameter Symbol Conditions Min Typ. (Note 1) Max NORMAL (Note 2): Gear = 1/1 fsys = 40.5 MHz 90 110 IDLE (Doze) (fOSC = 13.5 MHz, PLLON) 40 60 INTLV = “H” 33 50 55 900 IDLE (Halt) STOP ICC Unit mA DVCC2m = FVCC2 = CVCC2 = 2.2 to 2.7 V DVCC3n = 1.65 to 3.3 V AVCC3m = 2.7 to 3.5 V µA FVCC3 = 3.0 to 3.6 V Note 1: Ta = 25°C, DVCC2m = 2.5 V, DVCC3n = 3.0 V, AVCC3m = 3.3 V, unless otherwise noted. Note 2: Measured with the CPU dhrystone operating, all I/O peripherals channel on, and 16-bit external bus operated with 4 system clocks. Note 3: The supply current flowing through the DVCC2m, FVCC2, DVCC3n, CVCC2, FVCC3 and AVCC3m pins is included in the digital supply current parameter (ICC). TMP1962F-73 2006-02-21 TMP1962F10AXBG 4.6 ADC Electrical Characteristics DVCC15=CVCC15=1.5V±0.15V,DVCC2＝2.5V±0.2V, DVCC3n＝ 3.0V±0.3V , AVCC3m＝3.0V±0.2V Ta＝20∼85℃ （n＝1∼4、m＝1,2） Parameter Symbol Analog reference voltage (+) Condition VREFL Analog input voltage VAIN Analog supply During conversion current ADMOD1.VREFON = 1 IREF Not conversion ADMOD1.VREFON = 0 Typ Max AVCCm− 0.3 AVCC AVCCm+ 0.3 AVSS AVSS AVSS + 0.2 2.7 VREFH Analog reference voltage (–) Min Unit 3.3 VREFL V VREFH AVCCm = VREFH = 3.0V ± 0.3V DVSS = AVSS = VREFL 0.35 1.0 mA AVCCm = VREFH = 3.0V ± 0.3V DVSS = AVSS = VREFL 0.02 10 µA Analog input capacitance − 5.0 pF Analog input impedance − 5.0 ｋΩ Integral linearity error − Differential linearity error − Off set error − Gain error − AVCCm = VREFH = 3.0V ± 0.2V DVSS = AVSS = VREFL AIN input impedance R＜13.3kΩ C＜20pF AVCCm capacitor≧10μF VREFH capacitor≧10μF Conversion time≧7.9μs Note* ±2 ±3 LSB ± 1.5 ±3 LSB ±2 ±3 LSB ±2 ±6 LSB Note 1: 1 LSB = (VREFH – VREFL) / 1024 (V) Note 2: The supply current flowing through the AVCC pin is included in the digital supply current parameter (ICC). Note 3: Please shift to halt condition in AD converter before changing the standby mode of this product to STOP mode. Note*:Recommend to connect an external capacitor* 0.1μF AIN AVSS TMP1962F-74 2006-02-21 TMP1962F10AXBG 4.7 AC Electrical Characteristics 4.7.1 Multiplex Bus Mode (1) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ± 0.3 V, AVCC3m = 3.3 ± 0.2 V, DVCC33 = 3.0 V ± 0.3 V, Ta = -20 to 85°C (m = 1 to 2) 1. ALE width = 0.5 clock cycle, 1 programmed wait state No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 2 A0-A15 valid to ALE low tAL 0.5x − 4.3 8 ns 3 A0-A15 hold after ALE low tLA 0.5x − 1.8 10.5 ns 4 ALE pulse width high tLL 0.5x − 0.3 12 ns 5 ALE low to RD , WR or HWR asserted tLC 0.5x − 2.3 10 ns 6 RD , WR or HWR negated to ALE high tCL x − 0.6 24 ns 7 A0-A15 valid to RD , WR or HWR asserted tACL x − 5.1 19.5 ns 8 A16-A23 valid to RD , WR or HWR asserted tACH x − 5.1 19.5 ns 9 A16-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 10 A0-A15 valid to D0-D15 Data in tADL 11 A16-A23 valid to D0-D15 Data in tADH 12 RD asserted to D0-D15 data in tRD 13 RD width low tRR 14 D0-D15 hold after RD negated tHR 15 RD negated to next A0-A15 output tRAE 16 WR or HWR width low tWW 17 D0-D15 valid to WR or HWR negated 18 D0-D15 hold after WR or HWR negated 19 A16-A23 valid to WAIT input tAWH x (3 + 0.5) − 21.6 64.5 ns 20 A0-A15 valid to WAIT input tAWL x (3 + 0.5) − 21.6 64.5 ns 21 WAIT hold after RD , WR or HWR asserted tCW 67.4 ns Note: 24.6 ns x (2 + W) − 35.8 38 ns x (2 + W) − 35.8 38 ns x (1 + W) − 30.7 18.5 ns x (1 + W) − 2.7 46.5 ns 0 0 ns x − 0.1 24.5 ns x (1 + W) − 3.2 46 ns tDW x (1 + W) − 4.2 45 ns tWD x − 0.1 24.5 ns x (0.5 + 3 + N − 2) x (1.5 + 3 + N − 2) − 4.1 − 18.7 57.4 No. 1 to 18 indicate the values obtained with 1 programmed wait state. N0. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-75 2006-02-21 TMP1962F10AXBG 2. ALE width = 1.5 clock cycles, 1 programmed wait state No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 2 A0-A15 valid to ALE low tAL 1.5x − 3.9 24.6 33 ns ns 3 A0-A15 hold after ALE low tLA 0.5x − 1.8 10.5 ns 4 ALE pulse width high tLL 1.5x − 0.4 36.5 ns 5 ALE low to RD , WR or HWR asserted tLC 0.5x − 2.4 10 ns 6 RD , WR or HWR negated to ALE high tCL x − 0.6 24 ns 7 A0-A15 valid to RD , WR or HWR asserted tACL 2x − 5.2 44 ns 8 A16-A23 valid to RD , WR or HWR asserted tACH 2x − 5.2 44 ns 9 A16-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 10 A0-A15 valid to D0-D15 Data in tADL x (3 + W) − 35.9 62.5 ns 11 A16-A23 valid to D0-D15 Data in tADH x (3 + W) − 35.9 62.5 ns 12 x (1 + W) − 30.7 18.5 ns RD asserted to D0-D15 data in tRD 13 RD width low tRR x (1 + W) − 2.7 46.5 ns 14 D0-D15 hold after RD negated tHR 0 0 ns 15 RD negated to next A0-A15 output tRAE x 24.6 ns 16 WR or HWR width low tWW x (1 + W) − 3.2 46 ns 17 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 4.2 45 ns 18 D0-D15 hold after WR or HWR negated tWD x − 0.1 24.5 ns 19 A16-A23 valid to WAIT input tAWH 20 A0-A15 valid to WAIT input tAWL 21 WAIT hold after RD , WR or HWR asserted Note: tCW x (4 + 0.5) − 21.7 89 ns x (4 + 0.5) − 21.7 89 ns 67.4 ns x (0.5 + 3 + N − 2) x (1.5 + 3 + N − 2) − 4.1 − 18.7 57.4 No. 1 to 18 indicate the values obtained with 1 programmed wait state. N0. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-76 2006-02-21 TMP1962F10AXBG (2) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ± 0.3 V, AVCC3m = 3.3 ± 0.2 V, DVCC33 = 2.5 V ± 0.2 V, Ta = 20 to 85°C (m = 1 to 2) 1. ALE width = 0.5 clock cycle, 1 programmed wait state No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 2 A0-A15 valid to ALE low tAL 0.5x − 2.3 10 ns 3 A0-A15 hold after ALE low tLA 0.5x − 1.8 10.5 ns 4 ALE pulse width high tLL 0.5x − 0.3 12 ns 5 ALE low to RD , WR or HWR asserted tLC 0.5x − 2.3 10 ns tCL x − 0.6 24 ns 6 RD , WR or HWR negated to ALE high 24.6 ns 7 A0-A15 valid to RD , WR or HWR asserted tACL x − 5.1 19.5 ns 8 A16-A23 valid to RD , WR or HWR asserted tACH x − 5.1 19.5 ns 9 A16-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 10 A0-A15 valid to D0-D15 Data in tADL x (2 + W) − 36.8 37 ns 11 A16-A23 valid to D0-D15 Data in tADH x (2 + W) − 36.8 37 ns 12 RD asserted to D0-D15 data in tRD x (1 + W) − 31.7 17.5 ns 13 RD width low tRR x (1 + W) − 2.2 47 ns 14 D0-D15 hold after RD negated tHR 0 0 ns 15 RD negated to next A0-A15 output tRAE x − 0.1 24.5 ns 16 WR or HWR width low tWW x (1 + W) − 2.7 46.5 ns 17 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 3.8 45.5 ns 18 D0-D15 hold after WR or HWR negated tWD x –0.1 24.5 ns 19 A16-A23 valid to WAIT input tAWH 20 A0-A15 valid to WAIT input tAWL 21 WAIT hold after RD , WR or HWR asserted Note: tCW x (3 + 0.5) − 22.6 63.5 ns x (3 + 0.5) − 22.6 63.5 ns 66.4 ns x (0.5 + 3 + N − 2) x (1.5 + 3 + N − 2) − 5.1 − 19.7 56.4 No. 1 to 18 indicate the values obtained with 1 programmed wait state. N0. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-77 2006-02-21 TMP1962F10AXBG 2. ALE width = 1.5 clock cycles, 1 programmed wait state No. Parameter Min 1 System clock period (x) tSYS 2 A0-A15 valid to ALE low tAL 3 A0-A15 hold after ALE low 4 ALE pulse width high 5 40.5 MHz (fsys) (Note) Equation Symbol Max Min Unit Max 24.6 ns 1.5x − 2.4 34.5 ns tLA 0.5x − 1.8 10.5 ns tLL 1.5x − 0.4 36.5 ns ALE low to RD , WR or HWR asserted tLC 0.5x − 2.4 10 ns 6 RD , WR or HWR negated to ALE high tCL x − 0.6 24 ns 7 A0-A15 valid to RD , WR or HWR asserted tACL 2x − 5.2 44 ns 8 A16-A23 valid to RD , WR or HWR asserted tACH 2x − 5.2 44 ns 9 A16-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 10 A0-A15 valid to D0-D15 Data in tADL x (3 + W) − 36.9 61.5 ns 11 A16-A23 valid to D0-D15 Data in tADH x (3 + W) − 36.9 61.5 ns 12 17.5 ns x (1 + W) − 31.7 RD asserted to D0-D15 data in tRD 13 RD width low tRR x (1 + W) − 2.2 47 ns 14 D0-D15 hold after RD negated tHR 0 0 ns 15 RD negated to next A0-A15 output tRAE x − 0.1 24.5 ns 16 WR or HWR width low tWW x (1 + W) − 2.7 46.5 ns 17 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 3.8 45.5 ns 18 D0-D15 hold after WR or HWR negated tWD x –0.1 24.5 ns 19 A16-A23 valid to WAIT input tAWH 20 A0-A15 valid to WAIT input tAWL 21 WAIT hold after RD , WR or HWR asserted Note: tCW x (4 + 0.5) − 22.6 88.1 ns x (4 + 0.5) − 22.6 88.1 ns 66.4 ns x (0.5 + 3 + N − 2) x (1.5 + 3 + N − 2) − 5.1 − 19.7 56.4 No. 1 to 18 indicate the values obtained with 1 programmed wait state. N0. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-78 2006-02-21 TMP1962F10AXBG (3) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ± 0.3 V, AVCC3m = 3.3 ± 0.2 V, DVCC33 = 1.8 V ± 0.15 V, Ta = 20 to 85°C (m = 1 to 2) 1. ALE width = 0.5 clock cycle, 2 programmed wait state No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max 24.6 33333 Min Unit Max 1 System clock period (x) tSYS 2 A0-A15 valid to ALE low tAL 0.5x − 2.3 10 ns 3 A0-A15 hold after ALE low tLA 0.5x − 1.8 10.5 ns 4 ALE pulse width high tLL 0.5x − 0.3 12 ns 5 ALE low to RD , WR or HWR asserted tLC 0.5x − 2.3 10 ns tCL x − 0.6 24 ns 6 RD , WR or HWR negated to ALE high ns 7 A0-A15 valid to RD , WR or HWR asserted tACL x − 5.1 19.5 ns 8 A16-A23 valid to RD , WR or HWR asserted tACH x − 5.1 19.5 ns 9 A16-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 10 A0-A15 valid to D0-D15 Data in tADL x (2 + W) − 42.4 56 ns 11 A16-A23 valid to D0-D15 Data in tADH x (2 + W) − 42.4 56 ns 12 RD asserted to D0-D15 data in tRD x (1 + W) − 37.3 36.5 ns 13 RD width low tRR x (1 + W) − 2.3 71.5 ns 14 D0-D15 hold after RD negated tHR 0 0 ns 15 RD negated to next A0-A15 output tRAE x − 0.1 24.5 ns 16 WR or HWR width low tWW x (1 + W) − 2.8 71 ns 17 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 3.8 70 ns 18 D0-D15 hold after WR or HWR negated tWD x − 0.1 24.5 ns 19 A16-A23 valid to WAIT input tAWH 20 A0-A15 valid to WAIT input tAWL 21 WAIT hold after RD , WR or HWR asserted Note: tCW x (3 + 0.5) − 28.1 58 ns x (3 + 0.5) − 28.1 58 ns 61.4 ns x (0.5 + 3 + N − 2) x (1.5 + 3 + N − 2) − 6.1 − 24.7 55.4 No. 1 to 18 indicate the values obtained with 1 programmed wait state. N0. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-79 2006-02-21 TMP1962F10AXBG 2. ALE width = 1.5 clock cycles, 2 programmed wait states Equation No. Parameter 40.5 MHz (fsys) (Note) Symbol Min 1 System clock period (x) tSYS 2 A0-A15 valid to ALE low tAL 3 A0-A15 hold after ALE low 4 ALE pulse width high 5 6 Max Min Unit Max 24.6 ns 1.5x − 2.4 34.5 ns tLA 0.5x − 1.8 10.5 ns tLL 1.5x − 0.4 36.5 ns ALE low to RD , WR or HWR asserted tLC 0.5x − 2.3 10 ns RD , WR or HWR negated to ALE high tCL x − 0.6 24 ns 7 A0-A15 valid to RD , WR or HWR asserted tACL 2x − 5.2 44 ns 8 A16-A23 valid to RD , WR or HWR asserted tACH 2x − 5.2 44 ns 9 A16-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 10 A0-A15 valid to D0-D15 Data in tADL x (3 + W) − 42.5 80.5 ns 11 A16-A23 valid to D0-D15 Data in tADH x (3 + W) − 42.5 80.5 ns 12 x (1 + W) − 37.3 36.5 ns RD asserted to D0-D15 data in tRD 13 RD width low tRR x (1 + W) − 2.3 71.5 ns 14 D0-D15 hold after RD negated tHR 0 0 ns 15 RD negated to next A0-A15 output tRAE x − 0.1 24.5 ns 16 WR or HWR width low tWW x (1 + W) − 2.8 71 ns 17 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 3.8 70 ns 18 D0-D15 hold after WR or HWR negated tWD x − 0.1 24.5 ns 19 A16-A23 valid to WAIT input tAWH 20 A0-A15 valid to WAIT input tAWL 21 WAIT hold after RD , WR or HWR asserted Note: tCW x (4 + 0.5) − 28.1 82.6 ns x (4 + 0.5) − 28.1 82.6 ns 61.4 ns x (0.5 + 3 + N − 2) x (1.5 + 3 + N − 2) − 6.1 − 24.7 55.4 No. 1 to 18 indicate the values obtained with 1 programmed wait state. N0. 19 and 20 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-80 2006-02-21 TMP1962F10AXBG (1) Read cycle timing, ALE width = 0.5 clock cycle, 1 programmed wait state BUS Cycle = 4 CLK Cycles Internal CLK S1 W1 S2 S3 S1 tLL ALE tAL tCL tLA AD0 to AD15 A0 to A15 D0 to D15 tADL tADH A16 to A23 tHR tACH tACL tLC RD tRR tCAR tRAE tRD CS0 to CS3 R/W TMP1962F-81 2006-02-21 TMP1962F10AXBG (2) Read cycle timing, ALE width = 1.5 clock cycles, 1 programmed wait state BUS Cycle = 5 CLK Cycles Internal CLK S0 S1 W1 S2 S3 S0 tLL ALE tCL tAL tLA AD0 to AD15 A0 to A15 D0 to D15 tADL tADH A16 to A23 tHR tACH tACL tLC tRR tCAR tRAE tRD RD CS0 to CS3 R/W TMP1962F-82 2006-02-21 TMP1962F10AXBG (3) Read cycle timing, ALE width = 1.5 clock cycles, 2 externally generated wait states with N = 1 BUS Cycle = 6 CLK Cycles Internal CLK S1 W W S2 S3 S0 ALE AD0 to AD15 D0 to D15 A0 to A15 AD16 to AD23 RD tCW CS0 to CS3 R/W tAWL/H WAIT TMP1962F-83 2006-02-21 TMP1962F10AXBG (4) Read cycle timing, ALE width = 1.5 clock cycles, 4 externally generated wait states with N=1 BUS Cycle = 8 CLK Cycles Internal CLK S1 W W W W S2 S3 S0 ALE AD0 to AD15 A0 to A15 D0 to D15 AD16 to AD23 RD tCW CS0 to CS3 R/W tAWL/H WAIT TMP1962F-84 2006-02-21 TMP1962F10AXBG (5) Write cycle timing, ALE width = 1.5 clock cycles, zero wait state BUS Cycle = 4 CLK Cycles Internal CLK tLL ALE tAL tCL tLA AD0 to AD15 A0 to A15 D0 to D15 tDW AD16 to AD23 tWD tACH tACL tLC tWW tCAR WR , HWR CS0 to CS3 R/W TMP1962F-85 2006-02-21 TMP1962F10AXBG 4.7.2 Separate Bus Mode (1) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ± 0.3 V, AVCC3m = 3.3 ± 0.2 V, DVCC33 = 3.0 V ± 0.3 V, Ta = -20 to 85°C (m = 1 to 2) 1. SYSCR3<ALESEL> = 0, 1 programmed wait state No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 24.6 2 A0-A23 valid to RD , WR or HWR asserted tAC x − 5.1 19.5 ns 3 A0-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 4 A0-A23 valid to D0-D15 Data in tAD x (2 + W) − 35.8 38 5 RD asserted to D0-D15 data in tRD x (1 + W) − 30.7 18.5 6 RD width low tRR x (1 + W) − 2.7 46.5 ns 7 D0-D15 hold after RD negated tHR 0 0 ns 8 RD negated to next A0-A23 output tRAE x− 0.1 24.5 ns 9 WR or HWR width low tWW x (1 + W) − 3.2 46 WR or HWR asserted to D0-D15 valid tDO 11 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 4.2 45 ns 12 D0-D15 hold after WR or HWR negated tWD x − 0.1 24.5 ns 13 A0-A23 valid to WAIT input tAW 10 14 WAIT hold after RD , WR or HWR asserted Note: tCW ns 1 x (3 + 0.5) − 21.6 x (1.5 + 3 + N − 2) − 18.7 57.4 ns ns ⎯ x (0.5 + 3 + N − 2) − 4.1 ns ns 64.5 ns 67.4 ns No. 1 to 12 indicate the values obtained with 1 programmed wait state. N0. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-86 2006-02-21 TMP1962F10AXBG 2. SYSCR3<ALESEL> = 1, 1 programmed wait state No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 24.6 2 A0-A23 valid to RD , WR or HWR asserted ns tAC 2x − 5.2 44 ns 3 A0-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 4 A0-A23 valid to D0-D15 Data in tAD 5 RD asserted to D0-D15 data in tRD 6 RD width low tRR x (1 + W) − 2.7 7 D0-D15 hold after RD negated tHR 8 RD negated to next A0-A23 output tRAE 9 WR or HWR width low tWW x (3 + W) − 35.9 62.5 x (1 + W) − 30.7 18.5 ns ns 46.5 ns 0 0 ns x 24.6 ns x (1 + W) − 3.2 46 ns ⎯ 10 WR or HWR asserted to D0-D15 valid tDO 11 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 4.2 45 ns 12 D0-D15 hold after WR or HWR negated tWD x − 0.1 24.5 ns 13 A0-A23 valid to WAIT input tAW 14 WAIT hold after RD , WR or HWR asserted Note: tCW 1 x (4 + 0.5) − 21.7 x (0.5 + 3 + N − 2) − 4.1 x (1.5 + 3 + N − 2) − 18.7 57.4 ns 89 ns 67.4 ns No. 1 to 12 indicate the values obtained with 1 programmed wait state. N0. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-87 2006-02-21 TMP1962F10AXBG (2) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ± 0.3 V, AVCC3m = 3.3 ± 0.2 V, DVCC33 = 2.5 V ± 0.2 V, Ta = -20 to 85°C (m = 1 to 2) 1. SYSCR3<ALESEL> = 0, 1 programmed wait state No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 24.6 2 A0-A23 valid to RD , WR or HWR asserted tAC x − 5.1 19.5 ns 3 A0-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 4 A16-A23 valid to D0-D15 Data in tAD x (2 + W) − 36.8 37 ns 5 RD asserted to D0-D15 data in tRD x (1 + W) − 31.7 17.5 ns 6 RD width low tRR x (1 + W) − 2.2 47 ns 7 D0-D15 hold after RD negated tHR 0 0 ns 8 RD negated to next A0-A23 output tRAE x − 0.1 24.5 ns 9 WR or HWR width low tWW x (1 + W) − 2.7 46.5 WR or HWR asserted to D0-D15 valid tDO 11 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 3.8 45.5 ns 12 D0-D15 hold after WR or HWR negated tWD x –0.1 24.5 ns 13 A0-A23 valid to WAIT input tAW 14 WAIT hold after RD , WR or HWR asserted tCW 10 Note: ns ⎯ x (3 + 0.5) − 22.6 x (0.5 + 3 + N − 2) − 5.1 x (1.5 + 3 + N − 2) − 19.7 ns 1.5 56.4 ns 63.5 ns 66.4 ns No. 1 to 12 indicate the values obtained with 1 programmed wait state. N0. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-88 2006-02-21 TMP1962F10AXBG 2. SYSCR3<ALESEL> = 1, 1 programmed wait state No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 24.6 2 A0-A23 valid to RD , WR or HWR asserted tAC 2x − 5.2 44 ns 3 A0-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 4 A16-A23 valid to D0-D15 Data in tAD 5 RD asserted to D0-D15 data in tRD 6 RD width low tRR x (1 + W) − 2.2 47 ns 7 D0-D15 hold after RD negated tHR 0 0 ns 8 RD negated to next A0-A23 output tRAE x − 0.1 24.5 ns 9 WR or HWR width low tWW x (1 + W) − 2.7 46.5 ns 10 WR or HWR asserted to D0-D15 valid tDO 11 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 3.8 45.5 ns 12 D0-D15 hold after WR or HWR negated tWD x –0.1 24.5 ns 13 A0-A23 valid to WAIT input tAW 14 WAIT hold after RD , WR or HWR asserted Note: tCW ns x (3 + W) − 36.9 x (1 + W) − 31.7 ⎯ x (1.5 + 3 + N − 2) − 19.7 ns 17.5 ns 1.5 x (4 + 0.5) − 22.6 x (0.5 + 3 + N − 2) − 5.1 61.5 56.4 ns 88.1 ns 66.4 ns No. 1 to 12 indicate the values obtained with 1 programmed wait state. N0. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-89 2006-02-21 TMP1962F10AXBG (3) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ± 0.3 V, AVCC3m = 3.3 ± 0.2 V, DVCC33 = 1.8 V ± 0.15 V, Ta = -20 to 85°C (m = 1 to 2) 1. SYSCR3<ALESEL> = 0, 2 programmed wait states No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 24.6 2 A0-A23 valid to RD , WR or HWR asserted tAC x − 5.1 19.5 ns 3 A0-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 4 A0-A23 valid to D0-D15 Data in tAD x (2 + W) − 42.4 56 ns 5 RD asserted to D0-D15 data in tRD x (1 + W) − 37.3 36.5 ns 6 RD width low tRR x (1 + W) − 2.3 71.5 ns 7 D0-D15 hold after RD negated tHR 0 0 ns 8 RD negated to next A0-A23 output tRAE x − 0.1 24.5 ns 9 WR or HWR width low tWW x (1 + W) − 2.8 71 WR or HWR asserted to D0-D15 valid tDO 11 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 3.8 70 ns 12 D0-D15 hold after WR or HWR negated tWD x − 0.1 24.5 ns 13 A0-A23 valid to WAIT input tAWH 14 WAIT hold after RD , WR or HWR asserted tCW 10 Note: ns ns ⎯ 2 x (3 + 0.5) − 28.1 x (0.5 + 3 + N − 2) − 6.1 x (1.5 + 3 + N − 2) − 24.7 55.4 ns 58 ns 61.4 ns No. 1 to 12 indicate the values obtained with 1 programmed wait state. N0. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-90 2006-02-21 TMP1962F10AXBG 2. SYSCR3<ALESEL> = 1, 2 programmed states No. Parameter 40.5 MHz (fsys) (Note) Equation Symbol Min Max Min Unit Max 1 System clock period (x) tSYS 24.6 2 A0-A23 valid to RD , WR or HWR asserted tAC 2x − 5.2 44 ns 3 A0-A23 hold after RD , WR or HWR negated tCAR x − 1.6 23 ns 4 A16-A23 valid to D0-D15 Data in tAD 5 RD asserted to D0-D15 data in tRD 6 RD width low tRR 7 D0-D15 hold after RD negated tHR 8 RD negated to next A0-A23 output tRAE 9 WR or HWR width low tWW x (1 + W) − 2.8 10 WR or HWR asserted to D0-D15 valid tDO 11 D0-D15 valid to WR or HWR negated tDW x (1 + W) − 3.8 70 ns 12 D0-D15 hold after WR or HWR negated tWD x − 0.1 24.5 ns 13 A0-A23 valid to WAIT input tAWH 14 WAIT hold after RD , WR or HWR asserted Note: tCW ns x (3 + W) − 42.5 80.5 x (1 + W) − 37.3 x (1 + W) − 2.3 36.5 ns ns 71.5 ns 0 0 ns x − 0.1 24.5 ns 71 ns ⎯ 2 x (4 + 0.5) − 28.1 x (0.5 + 3 + N − 2) − 6.1 x (1.5 + 3 + N − 2) − 24.7 55.4 ns 82.6 ns 61.4 ns No. 1 to 12 indicate the values obtained with 1 programmed wait state. N0. 13 and 14 indicate the values obtained with 4 externally generated wait states with N = 1. AC measurement conditions: • Output levels: High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF • Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V W: Number of wait state cycles inserted (0 to 7 for programmed wait insertion) N: Value of N for (3 + N) wait insertion TMP1962F-91 2006-02-21 TMP1962F10AXBG (1) Read cycle timing (SYSCR3<ALESEL> = 0, 1 programmed wait state) BUS Cycle = 4 CLK Cycles Internal CLK S1 W1 S2 S3 S1 CS0 to CS3 tAD A0 to A23 tAC tHR D0 to D15 D0 to D15 tRR tCAR tRAE tRD RD R/W TMP1962F-92 2006-02-21 TMP1962F10AXBG (2) Read cycle timing (SYSCR3<ALESEL> = 1, 1 programmed wait state) BUS Cycle = 5 CLK Cycles Internal CLK S0 S1 W1 S2 S3 S0 CS0 to CS3 tAD A16 to A23 tAC tHR tAD D0 to D15 D0 to D15 tRR tCAR tRAE tRD RD R/W TMP1962F-93 2006-02-21 TMP1962F10AXBG (3) Read cycle timing SYSCR3<ALESEL> = 1, 2 externally generated wait states with N = 1) BUS Cycle = 6 CLK Cycles Internal CLK S1 W W S2 S3 S0 CS0 to CS3 A0 to A23 D0 to D15 D0 to D15 RD tCW R/W tAW WAIT TMP1962F-94 2006-02-21 TMP1962F10AXBG (4) Read cycle timing (SYSCR3<ALESEL> = 1, 4 externally generated wait states with N = 1) BUS Cycle = 8 CLK Cycles Internal CLK S1 W W W W S2 S3 S0 CS0 to CS3 A0 to A23 D0 to D15 D0 to D15 RD tCW R/W tAW WAIT TMP1962F-95 2006-02-21 TMP1962F10AXBG (5) Write cycle timing (SYSCR3<ALESEL> = 1, zero wait sate) BUS Cycle = 4 CLK Cycles Internal CLK CS0 to CS3 A0 to A23 tAC tDW D0 to D15 tWD D0 to D15 tDO tWW tCAR WR , HWR R/W TMP1962F-96 2006-02-21 TMP1962F10AXBG 4.8 Transfer with DMA Request The following shows an example of a transfer between the on-chip RAM and an external device in multiplex bus mode. • 16-bit data bus width, non-recovery time • Level data transfer mode • Transfer size of 16 bits, device port size (DPS) of 16 bits • Source/destination: on-chip RAM/external device The following shows transfer operation timing of the on-chip RAM to an external bus during write operation (memory-to-memory transfer). (2) (1) DREQn ALE A [23:16] AD [15:0] (N - 2)th transfer (N - 1)th transfer Nth transfer RD WR HWR CSn R/W (1) Indicates the condition under which Nth transfer is performed successfully. (2) Indicates the condition under which (N + 1)th transfer is not performed. TMP1962F-97 2006-02-21 TMP1962F10AXBG (1) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ±0.3 V, AVCC3m = 3.3 ± 0.2 V, DVCC33 = 2.3 V to 3.3 V, Ta = -20 to 85°C (m = 1 to 2) No. 2 3 Parameter RD asserted to DREQn negated (external device to on-chip RAM transfer) WR / HWR rising to DREQn negated (on-chip RAM to external device transfer) Equation Symbol 40.5 MHz (fsys) (Note) Unit (1) Min (2) Max Min Max tDREQ_r Wx − 4.2 (2W + ALE + 6) x − 51 45 195 ns tDREQ_w 0 (2W + ALE + 4) x − 51.8 0 145 ns (2) DVCC2m = FVCC2 = CVCC2 = 2.5 V ± 0.2 V, FVCC3 = 3.3 V ± 0.3 V, AVCC3m = 3.3 ± 0.2 V, DVCC33 = 1.8 V ± 0.15 V, Ta = 20 to 85°C (m = 1 to 2) No. Parameter Equation Symbol 40.5 MHz (fsys) (Note) (1) Min (2) Max Min Max Unit 2 RD asserted to DREQn negated (external device to on-chip RAM transfer) tDREQ_r Wx − 6.2 (2W + ALE + 6) x − 56 43 190 ns 3 WR / HWR rising to DREQn negated (on-chip RAM to external device transfer) tDREQ_w 0 (2W + ALE + 4) x − 56.8 0 140 ns W: Number of wait-state cycles inserted. In the case of (1 + N) externally generated wait states with N = 1, W becomes 2. ALE: Apply ALE = 0 for ALE 0.5 clock, ALE = 1 for ALE 1.5 clock. The values in the above table are obtained with W = 2, ALE = 0. TMP1962F-98 2006-02-21 TMP1962F10AXBG 4.9 Serial Channel Timing (1) I/O Interface Mode (DVCC3n = 3.0 V ± 0.3V) In the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. 1. SCLK input mode (SIO0 to SIO6) Parameter Symbol Equation Min Max 40.5 MHz Min Max Unit SCLK period tSCY 12x 296 ns TxD data to SCLK rise or fall* tOSS 2x − 45 4 ns TxD data hold after SCLK rise or fall* tOHS 8x − 15 182 ns RxD data valid to SCLK rise or fall* tSRD 30 30 ns RxD data hold after SCLK rise or fall* tHSR 2x − 30 19 ns * SCLK rise or fall: Measured relative to the programmed active edge of SCLK. 2. SCLK output mode (SIO0 to SIO6) Parameter SCLK period (programmable) Symbol Equation Min Max 40.5 MHz Min Max Unit tSCY 8x 197 TxD data to SCLK rise tOSS 4x − 10 88 ns TxD data hold after SCLK rise tOHS 4x − 10 88 ns RxD data valid to SCLK rise tSRD 45 45 ns RxD data hold after SCLK rise tHSR 0 0 ns TMP1962F-99 ns 2006-02-21 TMP1962F10AXBG (2) I/O Interface Mode (DVCC3n = 2.5 V ± 0.2 V) In the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. 1. SCLK input mode (SIO0 to SIO6) Parameter Symbol Equation Min Max 40.5 MHz Min Max Unit SCLK period tSCY 16x 395 ns TxD data to SCLK rise or fall* tOSS 4x − 60 38 ns TxD data hold after SCLK rise or fall* tOHS 10x − 15 232 ns RxD data valid to SCLK rise or fall* tSRD 30 30 ns RxD data hold after SCLK rise or fall* tHSR 2x + 10 59 ns * SCLK rise or fall: Measured relative to the programmed active edge of SCLK. 2. SCLK output mode (SIO0 to SIO6) Parameter Symbol SCLK period (programmable) Equation Min Max 40.5 MHz Min 197 Max Unit tSCY 8x ns TxD data to SCLK rise tOSS 4x − 10 88 ns TxD data hold after SCLK rise tOHS 4x − 10 88 ns RxD data valid to SCLK rise tSRD 60 60 ns RxD data hold after SCLK rise tHSR 0 0 ns tSCY SCLK SCK Output Mode/ Active-High SCL Input Mode SCLK Active-Low SCK Input Mode OUTPUT DATA TxD tOHS tOSS 0 1 2 tSRD INPUT DATA RxD 3 tHSR 0 1 2 3 VALID VALID VALID VALID TMP1962F-100 2006-02-21 TMP1962F10AXBG 4.10 SBI Timing (1) I2C Mode In the table below, the letters x and T represent the fsys and φT0 cycle periods, respectively. The letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the SBI0CR1. Parameter Equation Symbol Min Max Fast Mode Standard Mode fSYS = 8 MHz n = 4 fSYS = 32 MHz n = 4 Min Max Min Max 0 100 0 400 SCL clock frequency tSCL Hold time for START condition tHD:STA SCL clock low width (Input) (Note 1) tLOW SCL clock high width (Output) (Note 2) tHIGH 4.7 Setup time for a repeated START condition 0 tSU:STA kHz 0.6 µs 4.7 1.3 µs 4.0 0.6 µs 0.6 µs µs 4.0 (Note 5) Unit Data hold time (Input) (Note 3, 4) tHD:DAT 0.0 0.0 Data setup time tSU:DAT 250 100 ns Setup time for STOP condition tSU:STO 4.0 0.6 µs Bus free time between STOP and START conditions tBUF 4.7 1.3 µs (Note 5) Note 1: SCL clock low width (output) is calculated with (2 (n − 1) + 4) T. Standard mode: 6 µsec＠Typ (fsys = 8 MHz, n = 4) Fast mode: 1.5 µsec＠Typ (fsys = 32 MHz, n = 4) Note 2: SCL clock high width (output) is calculated with (2 (n − 1)) T. Standard mode: 4 µsec＠Typ (fsys = 8MHz, n = 4) Fast mode: 1 µsec＠Typ (fsys = 32 MHz, n = 4) Note 3: The output data hold time is equal to 12x. Note 4: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the fall edge of SCL. However, TMP1962F10AXBG SBI does not satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the SCL and SDA lines. Note 5: Software-dependent tSCL tf tLOW tr tHIGH SCL tHD;STA tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF SDA S Sr P S: START condition Sr: Repeated START condition P: STOP condition Note 6: To operate the SBI in I2C Fast mode, the fysy frequency must be no less than 20 MHz. To operate the SBI in I2C Standard mode, the fsys frequency must be no less than 4 MHz. TMP1962F-101 2006-02-21 TMP1962F10AXBG (2) Clock-Synchronous 8-Bit SIO Mode In the table below, the letters x and T represent the fsys and φT0 cycle periods, respectively. The letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the SBI0CR1. The electrical specifications below are for an SCK signal with a 50% duty cycle. 1. SCK Input Mode Parameter Equation Symbol SCK period Min tSCY 16x SO data to SCK rise tOSS SO data hold after SCK rise tOHS SI data valid to SCK rise SI data hold after SCK rise 40.5 MHz Max Min Max Unit 395 ns (tSCY/2) − (6x + 30) 19 ns (tSCY/2) + 4x 296 ns tSRD 0 0 ns tHSR 4x + 10 108 ns 2. SCK Output Mode Parameter Equation Symbol Min 32 MHz Max n Min Max Unit SCK period (programmable) tSCY 2 •T 1000 ns SO data to SCK rise tOSS (tSCY/2) − 20 480 ns SO data hold after SCK rise tOHS (tSCY/2) − 20 480 ns SI data valid to SCK rise tSRD 2x + 30 92 ns SI data hold after SCK rise tHSR 0 0 ns tSCY SCLK tOHS tOSS OUTPUT DATA TxD 0 1 2 tSRD INPUT DATA TxD 3 tHSR 0 1 2 3 VALID VALID VALID VALID TMP1962F-102 2006-02-21 TMP1962F10AXBG 4.11 Event Counter In the table below, the letter x represents the fsys cycle period. Parameter Equation Symbol Min Max 40.5 MHz Min Max Unit Clock low pulse width tVCKL 2X + 100 149 ns Clock high pulse width tVCKH 2X + 100 149 ns 4.12 Timer Capture In the table below, the letter x represents the fsys cycle period. Parameter Equation Symbol Min Max 40.5 MHz Min Max Unit Low pulse width tCPL 2X + 100 149 ns High pulse width tCPH 2X + 100 149 ns 4.13 General Interrupts In the table below, the letter x represents the fsys cycle period. Parameter Equation Symbol Min Max 40.5 MHz Min Max Unit Low pulse width for INT0-INTA tINTAL X + 100 125 ns High pulse width for INT0-INTA tINTAH X + 100 125 ns 4.14 NMI and STOP Wake-up Interrupts Parameter Equation Symbol Min Max 40.5 MHz Min Max Unit Low pulse width for NMI and INT0-INT4 tINTBL 100 100 ns High pulse width for INT0-INT4 tINTBH 100 100 ns 4.15 SCOUT Pin Parameter Equation Symbol Min Max 40.5 MHz Min Max Unit Clock high pulse width tSCH 0.5T − 5 7.4 ns Clock low pulse width tSCL 0.5T − 5 7.4 ns Note: In the above table, the letter T represents the cycle period of the SCOUT output clock. tSCH SCOUT tSCL TMP1962F-103 2006-02-21 TMP1962F10AXBG 4.16 Bus Request and Bus Acknowledge Signals BUSRQ (Note 1) BUSAK tBAA tABA (Note 2) AD0 to AD15 (Note 2) A0 to A23, RD , WR CS0 to CS3 , R / W , HWR ALE Parameter Symbol Equation 40.5 MHz Min Max Min Max Unit Bus float to BUSAK asserted tABA 0 80 0 80 ns Bus float after BUSAK negated tBAA 0 80 0 80 ns Note 1: If the current bus cycle has not terminated due to wait-state insertion, the TMP1962F10AXBG does not respond to BUSRQ until the wait state ends. Note 2: This broken line indicates that output buffers are disabled, not that the signals are at indeterminate states. The pin holds the last logic value present at that pin before the bus is relinquished. This is dynamically accomplished through external load capacitances. The equipment manufacturer may maintain the bus at a predefined state by means of off-chip restores, but he or she should design, considering the time (determined by the CR constant) it takes for a signal to reach a desired state. The on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal signal states. TMP1962F-104 2006-02-21 TMP1962F10AXBG 4.17 KWUP Input Pull-up Register Active Parameter Symbol Equation Min 40.5 MHz Max Min Max Unit Low pulse width for KEY0-D tkyTBL 100 100 ns High pulse width for KEY0-D tkyTBH 100 100 ns Pull-up Register Inactive Parameter Low pulse width for KEY0-D Symbol tkyTBL Equation Min 40.5 MHz Max 100 Min Max 100 Unit ns 4.18 Dual Pulse Input Parameter Dual input pulse period Symbol Tdcyc Equation Min 40.5MHz Max Min Max Unit 8Y 395 ns Dual input pulse setup Tabs Y + 20 70 ns Dual input pulse hold Tabh Y + 20 70 ns Y: Sampling clock (fsys/2) A Tabs B Tabh Tdcyc 4.19 ADTRG Input Parameter Symbol Equation Min Max 40.5 MHz Min Max Unit ADRG low level pulse width tadL fsysy/2 + 20 32.4 ns ADTRG high level pulse interval Tadh fsysy/2 + 20 32.4 ns TMP1962F-105 2006-02-21 TMP1962F10AXBG 5. Others ESD MM ±200V HBM ±1200V TMP1962F-106 2006-02-21 TMP1962F10AXBG 6.Package P-FBGA281-1313-0.65B6 TMP1962F-107