AD ADM1066ACP Multisupply supervisor/sequencer with margining control and auxiliary adc input Datasheet

Super Sequencer™ with Margining Control
and Auxiliary ADC Inputs
ADM1066
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2
REFIN
REFOUT REFGND
ADM1066
MUX
VREF
SDA SCL A1
A0
SMBus
INTERFACE
12-BIT
SAR ADC
EEPROM
CLOSED-LOOP
MARGINING SYSTEM
VX1
VX3
VX4
VX5
CONFIGURABLE
OUTPUT
DRIVERS
DUALFUNCTION
INPUTS
VX2
PDO1
PDO2
PDO3
(LOGIC INPUTS
OR
SFDs)
(HV CAPABLE
OF DRIVING
GATES OF
N-CHANNEL FET)
PDO4
CONFIGURABLE
OUTPUT
DRIVERS
PDO7
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO9
PDO5
PDO6
SEQUENCING
ENGINE
VP1
VP2
VP3
PROGRAMMABLE
RESET
GENERATORS
VP4
(SFDs)
VH
AGND
PDO8
PDO10
PDOGND
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
VDD
ARBITRATOR
VDDCAP
GND
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1066 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems. In addition to these
functions, the ADM1066 integrates a 12-bit ADC and six 8-bit
voltage output DACs. These circuits can be used to implement a
closed-loop margining system, which enables supply adjustment
by altering either the feedback node or reference of a dc/dc
converter using the DAC outputs.
(continued on Page 3)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
04609-001
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
better than 1% accuracy
5 selectable input attenuators allow supervision:
Supplies up to 14.4 V on VH
Supplies up to 6 V on VP1–4
5 dual-function inputs, VX1–5:
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable output drivers (PDO1–10):
Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external
N-FET (PDO1–6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs:
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow
voltage adjustment via dc/dc converter trim/feedback
node
12-bit ADC for readback of all supervised voltages
2 auxiliary (single-ended) ADC inputs
Reference input, REFIN, has 2 input options:
Driven directly from 2.048V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VP1–4, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
40-lead 6 mm × 6 mm LFCSP and
48-lead 7 mm × 7 mm TQFP packages
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADM1066
TABLE OF CONTENTS
General Description ......................................................................... 3
Timeout Detector ....................................................................... 19
Specifications..................................................................................... 4
Fault Reporting........................................................................... 19
Pin Configurations and Function Descriptions ........................... 7
Voltage Readback............................................................................ 20
Absolute Maximum Ratings............................................................ 8
Supply Supervision with the ADC ........................................... 20
Thermal Characteristics .............................................................. 8
Supply Margining ........................................................................... 21
ESD Caution.................................................................................. 8
Overview ..................................................................................... 21
Typical Performance Characteristics ............................................. 9
Open-Loop Margining .............................................................. 21
Powering the ADM1066 ................................................................ 12
Closed-Loop Supply Margining ............................................... 21
Inputs................................................................................................ 13
Writing to the DACs .................................................................. 22
Supply Supervision..................................................................... 13
Choosing the Size of the Attenuation Resistor....................... 22
Programming the Supply Fault Detectors............................... 13
DAC Limiting/Other Safety Features ...................................... 22
Input Comparator Hysteresis.................................................... 14
Applications Diagram .................................................................... 23
Input Glitch Filtering ................................................................. 14
Communicating with the ADM1066 ........................................... 24
Supply Supervision with VXn Inputs....................................... 14
Configuration Download at Power-Up................................... 24
VXn Pins as Digital Inputs........................................................ 15
Updating the Configuration ..................................................... 24
Outputs ............................................................................................ 16
Updating the Sequencing Engine............................................. 25
Supply Sequencing through Configurable Output Drivers .. 16
Internal Registers........................................................................ 25
Sequencing Engine ......................................................................... 17
EEPROM ..................................................................................... 25
Overview...................................................................................... 17
Serial Bus Interface..................................................................... 25
Warnings...................................................................................... 17
Write Operations ........................................................................ 27
SMBus Jump/Unconditional Jump .......................................... 17
Read Operations......................................................................... 29
Sequencing Engine Application Example ............................... 18
Outline Dimensions ....................................................................... 31
Sequence Detector...................................................................... 19
Ordering Guide .......................................................................... 31
Monitoring Fault Detector ........................................................ 19
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADM1066
GENERAL DESCRIPTION
(continued from Page 1)
Supply margining can be performed with a minimum of
external components. The margining loop can be used for incircuit testing of a board during production (for example, to
verify the board’s functionality at −5% of nominal supplies),
or can be used dynamically to accurately control the output
voltage of a dc/dc converter.
The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by ADI.
The device also provides up to ten programmable inputs for
monitoring under, over, or out-of-window faults on up to ten
supplies. In addition, ten programmable outputs can be used as
logic enables. Six of them can also provide up to a 12 V output
for driving the gate of an N-channel FET, which can be placed
in the path of a supply.
AUX2 AUX1
REFIN REFOUT REFGND SDA SCL A1
ADM1066
A0
SMBus
INTERFACE
VREF
OSC
12-BIT
SAR ADC
DEVICE
CONTROLLER
EEPROM
GPI SIGNAL
CONDITIONING
VX1
CONFIGURABLE
O/P DRIVER
(HV)
SFD
PDO1
PDO2
VX2
PDO3
VX3
PDO4
VX4
PDO5
GPI SIGNAL
CONDITIONING
SEQUENCING
ENGINE
VX5
VP1
CONFIGURABLE
O/P DRIVER
(HV)
PDO6
CONFIGURABLE
O/P DRIVER
(LV)
PDO7
SFD
SELECTABLE
ATTENUATOR
SFD
VP2
VP3
PDO8
VP4
PDO9
SELECTABLE
ATTENUATOR
CONFIGURABLE
O/P DRIVER
(LV)
SFD
PDOGND
SFDGND
VDDCAP
PDO10
VDD
ARBITRATOR
GND
REG 5.25V
CHARGE PUMP
VOUT
DAC
VCCP
DAC1
VOUT
DAC
DAC2
DAC3
Figure 2. Detailed Block Diagram
Rev. 0 | Page 3 of 32
DAC4
DAC5
DAC6
04609-002
VH
ADM1066
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPn
VP
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPn
Additional Currents
All PDO FET Drivers On
Min
Typ
Max
Unit
Test Conditions/Comments
4.75
6.0
14.4
5.4
V
V
V
V
µF
Minimum supply required on one of VPn, VH
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
4.2
6
mA
VDDCAP = 4.75 V, PDO1–10 off, DACs off, ADC off
mA
3.0
2.7
10
1
2.2
1
10
mA
mA
mA
VDDCAP = 4.75 V, PDO1-6 loaded with 1 µA each,
PDO7–10 off
Maximum additional load that can be drawn from
all PDO pull-ups to VDDCAP
6 DACs on with 100 µA maximum load on each
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
±0.05
%
Midrange and high range
Current Available from VDDCAP
DACs Supply Current
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPn Pins
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VX Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
2
6
2.5
±0.05
2.5
1.25
0.573
Input Reference Voltage on REFIN Pin,
VREFIN
Resolution
INL
Gain Error
6
3
1.375
1
V
V
%
Low range and midrange
V
V
V
No input attenuation error
MΩ
0.573
Threshold Resolution
Digital Glitch Filter
ANALOG-TO-DIGITAL CONVERTER
Signal Range
14.4
6
mA
1.375
±1
8
0
100
0
V
%
Bits
µs
µs
VREFIN
2.048
V
No input attenuation error
VREF error + DAC nonlinearity + comparator offset
error + input attenuation error
Minimum programmable filter length
Maximum programmable filter length
The ADC can convert signals presented to the VH,
VPn, and VX_GPIn pins. VPn and VH input signals
are attenuated depending on selected range. A
signal at the pin corresponding to the selected
range is from 0.573 V to 1.375 V at the ADC input.
V
12
±2.5
±0.05
Rev. 0 | Page 4 of 32
Bits
LSB
%
Endpoint corrected, VREFIN = 2.048 V
VREFIN = 2.048 V
ADM1066
Parameter
Conversion Time
Min
Offset Error
Input Noise
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x80 Output Voltage
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
INL
DNL
Gain Error
Load Regulation
Minimum Load Capacitance
Load Regulation
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode (PDO1–6)
Output Impedance
VOH
IOUTAVG
Standard (Digital Output) Mode (PDO1–10)
VOH
Max
0.25
Unit
ms
ms
LSB
LSBrms
8
Bits
±2
0.592
0.796
0.996
1.246
0.6
0.8
1
1.25
601.25
2.36
0.603
0.803
1.003
1.253
±0.75
±0.4
1
-4
2
50
2
2.5
60
40
2.043
2.048
−0.25
0.25
2.053
1
2
60
11
10.5
500
12.5
12
20
14
13.5
2.4
Three-State Output Leakage Current
Oscillator Frequency
VPU − 0.3
0
100
Endpoint corrected
Sourcing Current, IREFOUTMA X= -200µA
Sinking Current, IREFOUTMA X= 100µA
Per mA
DC
100 mV step in 20 ns with 50 pF load
No load
Sourcing current, IDACnMAX = −100 µA
Sinking current, IDACnMAX = 100 µA
Capacitor required for decoupling, stability
Per 100 µA
DC
kΩ
V
V
µA
IOH = 0
IOH = 1µA
2 V < VOH < 7 V
10
110
µA
kHz
Rev. 0 | Page 5 of 32
Same range, independent of center point
V
mV
mV
µF
mV
dB
2
0.50
20
60
20
90
V
V
V
V
mV
mV
LSB
LSB
%
mV
mV
pF
µs
mV
dB
dB
V
V
V
V
mA
mA
kΩ
mA
4.5
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPn)2
Test Conditions/Comments
One conversion on one channel
All 12 channels selected, 16x averaging enabled
VREFIN = 2.048 V
Direct input (no attenuator)
6 DACs are individually selectable for centering on
one of four output voltage ranges
Maximum Load Capacitance
Settling Time into 50 pF Load
Load Regulation
PSRR
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Typ
0.44
84
VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA
VPU to Vpn = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
IOL = 20 mA
Maximum sink current per PDO pin
Maximum total sink for all PDOs
Internal pull-up
Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPDO = 14.4 V
All on-chip time delays derived from this clock
ADM1066
Parameter
DIGITAL INPUTS (VXn, A0, A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current,
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL 2
SERIAL BUS TIMING
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
1
2
Min
Typ
Max
2.0
0.8
−1
1
5
20
2.0
0.8
0.4
400
4.7
4.7
4
4.7
4
1000
300
250
5
1
10
Unit
Test Conditions/Comments
V
V
µA
µA
pF
µA
Maximum VIN = 5.5 V
Maximum VIN = 5.5 V
VIN = 5.5 V
VIN = 0
VDDCAP = 4.75, TA = 25°C, if known logic state is
required
V
V
V
IOUT = −3.0 mA
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µA
VIN = 0
µs
At least one of the VH, VP1-4 pins must be ≥3.0 V to maintain the device supply on VDDCAP.
Specification is not production tested, but is supported by characterization data at initial product release.
Rev. 0 | Page 6 of 32
ADM1066
PDOGND
NC
31
VCCP
PDOGND
32
A0
VCCP
33
A1
A0
34
SCL
A1
35
SDA
SCL
36
AUX2
SDA
37
AUX1
AUX2
38
VDDCAP
AUX1
39
GND
VDDCAP
40
NC
GND
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
NC 1
VX1 1
36 NC
PIN 1
INDICATOR
30
PDO1
VX1 2
29
PDO2
VX2 3
34 PDO2
VX3 3
28
PDO3
VX3 4
33 PDO3
VX4 4
27
PDO4
VX4 5
26
PDO5
VX5 6
ADM1066
31 PDO5
25
PDO6
VP1 7
TOP VIEW
(Not to Scale)
30 PDO6
VP2 7
24
PDO7
VP2 8
29 PDO7
VP3 8
23
PDO8
VP3 9
28 PDO8
VP4 9
22
PDO9
VP4 10
27 PDO9
VH 10
21
PDO10
VH 11
26 PDO10
NC 12
25 NC
PIN 1
INDICATOR
14
15
16
17
18
19
20
21
22
23
24
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
NC
04609-004
13
REFOUT
20
REFIN
19
REFGND
18
32 PDO4
NC
17
DAC3
16
DAC2
15
DAC1
14
REFOUT
REFGND
13
REFIN
12
AGND
11
35 PDO1
AGND
TOP VIEW
(Not to Scale)
04609-003
VP1 6
DAC6
ADM1066
DAC5
VX5 5
DAC4
VX2 2
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin No.
LFCSP TQFP
1, 12–13,
24–25,
36–37, 48
1–5
2–6
Mnemonic
NC
Description
No connection.
VX1–5
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply
fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
Ground Return for Input Attenuators.
Ground Return for On-Chip Reference Circuits.
Reference Input for ADC. Nominally, 2.048 V.
2.048 V Reference Output.
Voltage Output DACs. These pins default to high impedance at power-up.
Programmable Output Drivers.
Ground Return for Output Drivers.
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
and GND.
Logic Input. This pin sets the seventh bit of the SMBus interface address.
Logic Input. This pin sets the sixth bit of the SMBus interface address.
SMBus Clock Pin. Open-drain output requires external resistive pull-up.
SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
Auxiliary, Single-Ended ADC Input.
Auxiliary, Single-Ended ADC Input.
Device Supply Voltage. Linearly regulated from the highest of the VP1–4, VH pins to a typical of 4.75 V.
Supply Ground.
6–9
7–10
VP1–4
10
11
VH
11
12
13
14
15–20
21–30
31
32
14
15
16
17
18–23
26–35
38
39
AGND
REFGND
REFIN
REFOUT
DAC1–6
PDO10–1
PDOGND
VCCP
33
34
35
36
37
38
39
40
40
41
42
43
44
45
46
47
A0
A1
SCL
SDA
AUX2
AUX1
VDDCAP
GND
Rev. 0 | Page 7 of 32
ADM1066
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Voltage on VH Pin
Voltage on VP Pins
Voltage on VX Pins
Voltage on AUX1, AUX2, REFIN Pins
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature, Soldering
Vapor Phase, 60 s
Rating
16 V
7V
−0.3 V to +6.5 V
−0.3 V to +5 V
±5 mA
±20 mA
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
40-lead LFCSP package: θJA = 25°C/W
215°C
48-lead TQFP package: θJA = 14.8°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 32
ADM1066
TYPICAL PERFORMANCE CHARACTERISTICS
180
6
160
5
140
120
IVP1 (µA)
VVDDCAP (V)
4
3
100
80
60
2
40
0
0
1
2
3
4
5
04609-053
04609-050
1
20
0
0
6
1
2
3
4
5
6
VVP1 (V)
VVP1 (V)
Figure 5. VVDDCAP vs. VVP1
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
5.0
6
4.5
5
4.0
3.5
3.0
IVH (mA)
3
2
2.5
2.0
1.5
1.0
04609-051
1
0
0
2
4
6
8
10
12
14
04609-054
VVDDCAP (V)
4
0.5
0
0
16
2
4
6
8
10
12
14
16
VVH (V)
VVH (V)
Figure 9. IVH vs. VVH (VH as Supply)
Figure 6. VVDDCAP vs. VVH
350
5.0
4.5
300
4.0
250
IVH (µA)
3.0
2.5
2.0
1.5
200
150
100
1.0
0.5
0
0
1
2
3
4
5
04609-055
50
04609-052
IVP1 (mA)
3.5
0
0
6
1
2
3
4
VVH (V)
VVP1 (V)
Figure 10. IVH vs. VVH (VH Not as Supply)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
Rev. 0 | Page 9 of 32
5
6
ADM1066
14
1.0
0.8
12
0.4
0.2
DNL (LSB)
VPDO1 CHARGE PUMPED
0.6
10
8
6
0
–0.2
–0.4
4
04609-056
0
0
2.5
5.0
7.5
10.0
12.5
04609-066
–0.6
2
–0.8
–1.0
15.0
0
1000
ILOAD CURRENT (µA)
0.8
4.0
0.6
3.5
0.4
VP1 = 5V
2.5
VP1 = 3V
2.0
0.2
0
–0.2
1.5
–0.4
1.0
–0.6
0.5
0
3
4
5
04609-063
INL (LSB)
3.0
04609-057
VPDO1 (V)
1.0
4.5
2
4000
Figure 14. DNL for ADC
5.0
1
3000
CODE
Figure 11. VPDO1 (FET Drive Mode) vs. ILOAD
0
2000
–0.8
–1.0
6
0
1000
ILOAD (mA)
2000
3000
4000
CODE
Figure 12. VPDO1 (Strong Pull-Up VP) vs. ILOAD
Figure 15. INL for ADC
4.5
12000
4.0
9894
10000
3.5
VP1 = 5V
HITS PER CODE
2.5
VP1 = 3V
2.0
1.5
8000
6000
4000
1.0
0.5
0
0
10
20
30
40
50
25
81
0
60
2047
ILOAD (µA)
2048
2049
CODE
Figure 16. ADC Noise, Midcode Input, 10,000 Reads
Figure 13. VPDO1 (Weak Pull-Up to VP) vs. ILOAD
Rev. 0 | Page 10 of 32
04609-064
2000
04609-058
VPDO1 (V)
3.0
ADM1066
1.005
1.004
1.003
DAC 20kΩ
BUFFER
OUTPUT
47pF
PROBE
POINT
DAC OUTPUT
1.002
1.001
VP1 = 3.0V
1.000
VP1 = 4.75V
0.999
0.998
04609-065
0.997
0.996
04609-059
1
CH1 200mV
M1.00µs
CH1
0.995
–40
–20
0
20
40
60
80
100
80
100
TEMPERATURE (°C)
756mV
Figure 17. Transient Response of DAC Code Change into Typical Load
Figure 19. DAC Output vs. Temperature
2.058
1V
PROBE
POINT
CH1 200mV
M1.00µs
CH1
VP1 = 4.75V
2.043
04609-060
1
VP1 = 3.0V
2.048
944mV
2.038
–40
04609-061
DAC 100kΩ
BUFFER
OUTPUT
REFOUT (V)
2.053
–20
0
20
40
60
TEMPERATURE (°C)
Figure 18. Transient Response of DAC to Turn-On from HI-Z State
Figure 20. REFOUT vs. Temperature
Rev. 0 | Page 11 of 32
ADM1066
POWERING THE ADM1066
VDDCAP
VP1
IN
OUT
4.75V
LDO
EN
VP2
IN
OUT
4.75V
LDO
EN
VP3
IN
OUT
4.75V
LDO
EN
VP4
IN
OUT
4.75V
LDO
EN
VH
An external capacitor to GND is required to decouple the onchip supply from noise. This capacitor should be connected to
the VDDCAP pin, as shown in Figure 21. The capacitor has
another use during brownouts (momentary loss of power).
Under these conditions, when the input supply (VPn or VH)
dips transiently below VDD, the synchronous rectifier switch
immediately turns off so that it does not pull VDD down. The
VDD cap can then act as a reservoir to keep the device active
until the next highest supply takes over the powering of the
device. 10 µF is recommended for this reservoir/decoupling
function.
Note that when two or more supplies are within 100 mV of each
other, the supply that takes control of VDD first keeps control.
For example, if VP1 is connected to a 3.3 V supply, then VDD
powers up to approximately 3.1 V through VP1. If VP2 is then
connected to another 3.3 V supply, VP1 still powers the device,
unless VP2 goes 100 mV higher than VP1.
Rev. 0 | Page 12 of 32
IN
OUT
4.75V
LDO
INTERNAL
DEVICE
SUPPLY
EN
SUPPLY
COMPARATOR
04609-022
The ADM1066 is powered from the highest voltage input on
either the positive-only supply inputs (VPn) or the high voltage
supply input (VH). This technique offers improved redundancy
as the device is not dependent on any particular voltage rail to
keep it operational. The same pins are used for supply fault
detection (discussed later in the next section). A VDD arbitrator
on the device chooses which supply to use. The arbitrator can
be considered an OR’ing of five LDOs together. A supply
comparator chooses which of the inputs is highest and selects
this one to provide the on-chip supply. There is minimal
switching loss with this architecture (~0.2 V), resulting in the
ability to power the ADM1066 from a supply as low as 3.0 V.
Note that the supply on the VXn pins cannot be used to power
the device.
Figure 21. VDD Arbitrator Operation
ADM1066
INPUTS
SUPPLY SUPERVISION
The resolution is given by
The ADM1066 has ten programmable inputs. Five of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VP1–4 by default. The other five inputs are
labeled VX1–VX5 and have dual functionality. They can be
used as either supply fault detectors, with similar functionality
to VH and VP1–4, or CMOS/TTL-compatible logic inputs to
the devices. Therefore, the ADM1066 can have up to ten analog
inputs, a minimum of five analog inputs and five digital inputs,
or a combination. If an input is used as an analog input, it
cannot be used as a digital input. Therefore, a configuration
requiring ten analog inputs has no digital inputs available.
Table 5 shows the details of each of the inputs.
RANGE
SELECT
ULTRA
LOW
+
VPn
VREF
OV
COMPARATOR
–
GLITCH
FILTER
FAULT
OUTPUT
Step Size = Threshold Range/255
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
(14.4 V − 4.8 V)/255 = 37.6 mV
Table 4 lists the upper and lower limit of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 4. Voltage Range Limits
Voltage Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
4.8 to 14.4
VB (V)
0.573
1.25
2.5
4.8
VR (V)
0.802
1.75
3.5
9.6
The threshold value required is given by
VT = (VR × N)/255 + VB
+
LOW
–
where:
FAULT TYPE
UV
SELECT
COMPARATOR
04609-023
MID
Figure 22. Supply Fault Detector Block
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1066 has up to ten supply fault detectors (SFDs) on its
ten input channels. These highly programmable reset generators
enable the supervision of up to ten supply voltages. The supplies
can be as low as 0.573 V and as high as 14.4 V. The inputs can be
configured to detect an undervoltage fault (the input voltage
droops below a preprogrammed value), an overvoltage fault (the
input voltage rises above a preprogrammed value) or an out-ofwindow fault (undervoltage or overvoltage). The thresholds can
be programmed to an 8-bit resolution in registers provided in
the ADM1066. This translates to a voltage resolution that is
dependent on the range selected.
VT is the desired threshold voltage (UV or OV).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is given
by
N = 255 × (VT − VB)/VR
For example, if the user wants to set a 5 V OV threshold on VP1,
the code to be programmed in the PS1OVTH register
(discussed in the AN-698 application note) is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
Table 5. Input Functions, Thresholds, and Ranges
Input
VH
Function
High V Analog Input
VPn
Positive Analog Input
VXn
High Z Analog Input
Digital Input
Voltage Range (V)
2.5–6.0
4.8–14.4
0.573–1.375
1.25–3.00
2.5–6.0
0.573–1.375
0–5
Maximum Hysteresis
425 mV
1.16 V
97.5 mV
212 mV
425 mV
97.5 mV
N/A
Rev. 0 | Page 13 of 32
Voltage Resolution (mV)
13.7
37.6
3.14
6.8
13.7
3.14
N/A
Glitch Filter (µs)
0–100
0–100
0–100
0–100
0–100
0–100
0–100
ADM1066
The UV and OV comparators shown in Figure 22 are always
looking at VPn. To avoid chattering (multiple transitions when
the input is very close to the set threshold level), these comparators have digitally programmable hysteresis. The hysteresis can
be programmed up to the values shown in Table 5.
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program how much above
the UV threshold the input must rise again before a UV fault is
deasserted. Similarly, the user can program how much below the
OV threshold an input must fall again before an OV fault is
deasserted.
The hysteresis figure is given by
INPUT PULSE SHORTER
THAN GLITCH FILTER TIMEOUT
INPUT PULSE LONGER
THAN GLITCH FILTER TIMEOUT
PROGRAMMED
TIMEOUT
PROGRAMMED
TIMEOUT
INPUT
T0
INPUT
TGF
T0
TGF
OUTPUT
T0
VHYST = VR × NTHRESH/255
TGF
OUTPUT
T0
TGF
04609-024
INPUT COMPARATOR HYSTERESIS
Figure 23. Input Glitch Filter Function
SUPPLY SUPERVISION WITH VXn INPUTS
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 5.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators.
This allows the user to remove any spurious transitions such as
supply bounce at turn-on. The glitch filter function is additional
to the digitally programmable hysteresis of the SFD comparators. The glitch filter timeout is programmable up to 100 µs.
For example, when the glitch filter timeout is 100 µs, any pulses
appearing on the input of the glitch filter block that are less than
100 µs in duration are prevented from appearing on the output
of the glitch filter block. Any input pulse that is longer than
100 µs does appear on the output of the glitch filter block. The
output is delayed with respect to the input by 100 µs. The
filtering process is shown in Figure 23.
The VXn inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as an
analog (SFD) input, the VXn pins have very similar functionality
to the VH and VPn pins. The major difference is that the VXn
pins have only one input range: 0.573 V to 1.375 V. Therefore,
these inputs can directly supervise only the very low supplies.
However, the input impedance of the VXn pins is high, allowing
an external resistor divide network to be connected to the pin.
Thus, any supply can be potentially divided down into the input
range of the VXn pin and supervised. This enables the ADM1066
to monitor other supplies such as +24 V, +48 V, and −5 V.
An additional supply supervision function is available when the
VXn pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedicated analog inputs, VP1–4 and VH. The analog function of
VX1 is mapped to VP1, VX2 is mapped to VP2, and so on. VX5
is mapped to VH. In this case, these SFDs can be viewed as a
secondary or warning SFD.
The secondary SFDs are fixed to the same input range as the
primary SFD. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be generated on a single supply using only one pin. For example, if VP1
is set to output a fault if a 3.3 V supply droops to 3.0 V, VX1 can
be set to output a warning at 3.1 V. Warning outputs are available
for readback from the status registers. They are also OR’ed
together and fed into the sequencing engine (SE), allowing
warnings to generate interrupts on the PDOs. Therefore, in the
example above, if the supply droops to 3.1 V, a warning is
generated, and remedial action can be taken before the supply
drops out of tolerance.
Rev. 0 | Page 14 of 32
ADM1066
As mentioned previously, the VXn input pins on the ADM1066
have dual functionality. The second function is as a digital input
to the device. Therefore, the ADM1066 can be configured for up
to five digital inputs. These inputs are TTL/CMOS-compatible.
Standard logic signals can be applied to the pins: RESET from
reset generators, PWRGOOD signals, fault flags, manual resets,
and so on. These signals are available as inputs to the SE, and so
can be used to control the status of the PDOs. The inputs can be
configured to detect either a change in level or an edge.
The digital blocks feature the same glitch filter function that is
available on the SFDs. This enables the user to ignore spurious
transitions on the inputs. For example, the filter can be used to
debounce a manual reset switch.
When configured as digital inputs, each of the VXn pins has a
weak (10 µA) pull-down current source available for placing the
input in a known condition, even if left floating. The current
source, if selected, weakly pulls the input to GND.
VXn
(DIGITAL INPUT)
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, once the logic transition is detected, a pulse of
programmable width is output from the digital block. The width
is programmable from 0 µs to 100 µs.
+
DETECTOR
GLITCH
FILTER
–
VREF = 1.4V
Figure 24. VXn Digital Input Function
Rev. 0 | Page 15 of 32
TO
SEQUENCING
ENGINE
04609-027
VXn PINS AS DIGITAL INPUTS
ADM1066
OUTPUTS
from a backplane supply (a PDO can sustain greater than 10.5 V
into a 1 µA load). The pull-down switches can also be used to
drive status LEDs directly.
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1066 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PnPDOCFG configuration register (see the AN-698 application note for details).
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing
engine (SE). The SE determines what action is to be taken with
the PDOs based on the condition of the inputs of the ADM1066.
Therefore, the PDOs can be set up to assert when the SFDs are
in tolerance, the correct input signals are received on the VXn
digital pins, no warnings are received from any of the inputs of
the device, and so on. The PDOs can be used for a variety of
functions. The primary function is to provide enable signals for
LDOs or dc/dc converters, which generate supplies locally on a
board. The PDOs can also be used to provide a POWER_GOOD
signal when all the SFDs are in tolerance, or a RESET output if
one of the SFDs goes out of specification (this can be used as a
status signal for a DSP, FPGA, or other microcontroller).
The data sources are
• Output from the SE.
• Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.
• On-Chip Clock. A 100 kHz clock is generated on the device.
This clock can be made available on any of the PDOs. It can
be used, for example, to clock an external device such as
an LED.
By default, the PDOs are pulled to GND by a weak (20 kΩ) onchip pull-down resistor. This is also the condition of the PDOs
on power-up, until the configuration is downloaded from
EEPROM and the programmed setup is latched. The outputs
are actively pulled low once a supply of 1 V or greater is on VPn
or VH. The outputs remain high impedance prior to 1 V appearing on VPn or VH. This provides a known condition for the
PDOs during power-up. The internal pull-down can be overdriven with an external pull-up of suitable value tied from the
PDO pin to the required pull-up voltage. The 20 kΩ resistor
must be accounted for in calculating a suitable value. For
example, if PDOn must be pulled up to 3.3 V, and 5 V is available
as an external supply, the pull-up resistor value is given by
The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as follows:
• Open-drain (allowing the user to connect an external pull-up
resistor)
• Open-drain with weak pull-up to VDD
• Push/pull to VDD
• Open-drain with weak pull-up to VPn
• Push/pull to VPn
• Strong pull-down to GND
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
• Internally charge-pumped high drive (12 V, PDO1–6 only)
Therefore,
The last option (available only on PDO1–6) allows the user to
directly drive a voltage high enough to fully enhance an external
N-FET, which is used to isolate, for example, a card-side voltage
RUP = (100 kΩ − 66 kΩ)/3.3 = 10 kΩ
VFET (PDO1-6 ONLY)
VDD
VP4
10Ω
20kΩ
10Ω
10Ω
20kΩ
VP1
SEL
20kΩ
CFG4 CFG5 CFG6
SE DATA
PDO
SMBus DATA
Figure 25. Programmable Driver Output
Rev. 0 | Page 16 of 32
04609-028
20kΩ
CLK DATA
ADM1066
SEQUENCING ENGINE
The ADM1066’s sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex
control of boards such as power-up and power-down sequence
control, fault event handling, interrupt generation on warnings,
and so on. A watchdog function that verifies the continued
operation of a processor clock can be integrated into the SE
program. The SE can also be controlled via the SMBus, giving
software or firmware control of the board sequencing.
• Transition from one state to the next is made in less than
20 µs, which is the time needed to download a state definition
from EEPROM to the SE.
MONITOR
FAULT
STATE
TIMEOUT
SEQUENCE
04609-029
OVERVIEW
Figure 26. State Cell
The SE state machine comprises 63 state cells. Each state has the
following attributes:
• Monitors signals indicating the status of the 10 input pins,
VP1 to VP4, VH, and VX1 to VX5.
• Can be entered from any other state.
• Three exit routes move the state machine on to a next state:
sequence detection, fault monitoring, and timeout.
• Delay timers for the sequence and timeout blocks can be
programmed independently, and change with each state
change. The range of timeouts is from 0 ms to 400 ms.
The ADM1066 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be
generated when the ADC readings violate their limit register
value or when the secondary voltage monitors on VP1–4 and
VH. The warnings are all OR’ed together and are available as a
single warning input to each of the three blocks that enable
exiting from a state.
SMBus JUMP/UNCONDITIONAL JUMP
The SE can be forced to advance to the next state unconditionally. This enables the user to force the SE to advance. Examples
of where this might be used include moving to a margining
state or debugging a sequence. The SMBus jump or go-to
command can be seen as another input to sequence and
timeout blocks, which provide an exit from each state.
• Output condition of the 10 PDO pins is defined and fixed
within a state.
Table 6. Sample Sequence State Entries
State
IDLE1
IDLE2
EN3V3
Sequence
If VX1 is low , go to state IDLE2.
If VP1 is okay, go to state EN3V3.
If VP2 is okay, go to state EN2V5.
DIS3V3
EN2V5
If VX1 is high, go to state IDLE1.
If VP3 is okay, go to state PWRGD.
DIS2V5
FSEL1
FSEL2
PWRGD
If VX1 is high, go to state IDLE1.
If VP3 is not okay, go to state DIS2V5.
If VP2 is not okay, go to state DIS3V3.
If VX1 is high, go to state DIS2V5.
Timeout
Monitor
If VP2 is not okay after 10 ms, go to
state DIS3V3.
If VP1 is not okay, go to state IDLE1.
If VP3 is not okay after 20 ms, go to
state DIS2V5.
If VP1 or VP2 is not okay, go to state FSEL2.
If VP1 or VP2 is not okay, go to state FSEL2.
If VP1 is not okay, go to state IDLE1.
If VP1, VP2, or VP3 is not okay, go to state
FSEL1.
Rev. 0 | Page 17 of 32
ADM1066
SEQUENCE
STATES
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 27 shows how the simple building block of a
single SE state can be used to build a power-up sequence for a
3-supply system.
IDLE1
VX1 = 0
Table 7 lists the PDO outputs for each state in the same SE
implementation. In this system, the presence of a good 5 V
supply on VP1 and the VX1 pin held low are the triggers required
for a power-up sequence to start. The sequence intends to turn
on the 3.3 V supply next, then the 2.5 V supply (assuming
successful turn-on of the 3.3 V supply). Once all three supplies
are good, the PWRGD state is entered, where the SE remains
until a fault occurs on one of the three supplies, or it is instructed
to go through a power-down sequence by VX1 going high.
IDLE2
VP1 = 1
MONITOR FAULT
STATES
TIMEOUT
STATES
EN3V3
10ms
VP1 = 0
VP2 = 1
EN2V5
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following sections, which describe the
individual blocks, use this sample application to demonstrate
the state machine’s actions.
DIS3V3
20ms
(VP1 + VP2) = 0
VX1 = 1
VP3 = 1
PWRGD
DIS2V5
VP2 = 0
(VP1 + VP2 + VP3) = 0
VX1 = 1
FSEL1
VX1 = 1
(VP1 +
VP2) = 0
VP3 = 0
FSEL2
VP1 = 0
04609-030
VP2 = 0
Figure 27. Sample Application Flow Diagram
Table 7. PDO Outputs for Each State
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
IDLE1
0
0
0
IDLE2
0
0
0
EN3V3
1
0
0
EN2V5
1
1
0
DIS3V3
0
1
1
Rev. 0 | Page 18 of 32
DIS2V5
1
0
1
PWRGD
1
1
0
FSEL1
1
1
1
FSEL2
1
1
1
ADM1066
MONITORING FAULT
DETECTOR
SEQUENCE DETECTOR
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the inputs to
the SE to change state, and is most often used as the gate on
successful progress through a power-up or power-down
sequence. A timer block is included in this detector, which
can insert delays into a power-up or power-down sequence,
if required. Timer delays can be set from 10 µs to 400 ms.
Figure 28 is a block diagram of the sequence detector.
1-BIT FAULT
DETECTOR
VP1
MASK
SENSE
1-BIT FAULT
DETECTOR
VX5
VP1
VX5
SUPPLY FAULT
DETECTION
FAULT
SUPPLY FAULT
DETECTION
FAULT
LOGIC INPUT CHANGE
OR FAULT DETECTION
MASK
SENSE
SEQUENCE
DETECTOR
1-BIT FAULT
DETECTOR
LOGIC INPUT CHANGE
OR FAULT DETECTION
TIMER
FAULT
WARNINGS
INVERT
MASK
SELECT
04609-032
FORCE FLOW
(UNCONDITIONAL JUMP)
Figure 28. Sequence Detector Block Diagram
The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 27, the FSEL1
and FSEL2 states first identify which of the VP1,VP2, or VP3
pins has faulted, and then they take the appropriate action.
MONITORING FAULT DETECTOR
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate, which can detect when an input deviates from its
expected condition. The clearest demonstration of the use of
this block is in the PWRGD state, where the monitor block
indicates that a failure on one or more of the VP1,VP2, or VP3
inputs has occurred.
No programmable delay is available in this block, because the
triggering of a fault condition is likely to be caused when a supply
falls out of tolerance. In this situation, the user would want to
react as quickly as possible. Some latency occurs when moving
out of this state, however, because it takes a finite amount of
time (~20 µs) for the state configuration to download from
EEPROM into the SE. Figure 29 is a block diagram of the
monitoring fault detector.
04609-033
WARNINGS
Figure 29. Monitoring Fault Detector Block Diagram
TIMEOUT DETECTOR
The timeout detector allows the user to trap a failure to make
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 27, the timeout nextstate transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted upon entry to this
state (on the PDO1 output pin) to turn on a 3.3 V supply. This
supply rail is connected to the VP2 pin, and the sequence detector looks for the VP2 pin to go above its UV threshold, which is
set in the supply fault detector (SFD) attached to that pin.
The power-up sequence progresses when this change is
detected. If, however, the supply fails (perhaps due to a short
circuit overloading this supply), then the timeout block traps
the problem. In this example, if the 3.3 V supply fails within
10 ms, then the SE moves to the DIS3V3 state and turns off this
supply by bringing PDO1 low. It also indicates that a fault has
occurred by taking PDO3 high. Timeout delays of from 100 µs
to 400 ms can be programmed.
FAULT REPORTING
The ADM1066 has a fault latch for recording faults. Two registers
are set aside for this purpose. A single bit is assigned to each
input of the device, and a fault on that input sets the relevant bit.
The contents of the fault register can be read out over the
SMBus to determine which input(s) faulted. The fault register
can be enabled/disabled in each state. This ensures that only real
faults are captured and not, for example, undervoltage trips
when the SE is executing a power-down sequence.
Rev. 0 | Page 19 of 32
ADM1066
VOLTAGE READBACK
The ADM1066 has an on-board 12-bit accurate ADC for
voltage readback over the SMBus. The ADC has a 12-channel
analog mux on the front end. The twelve channels consist of the
ten SFD inputs (VH, VP1-4, VX1-5) and two auxiliary (singleended) ADC inputs (AXU1, AUX2). Any or all of these inputs
can be selected to be read, in turn, by the ADC. The circuit
controlling this operation is called round-robin. The roundrobin circuit can be selected to run through its loop of conversions just once or continuously. Averaging is also provided for
each channel. In this case, the round-robin circuit runs through
its loop of conversions 16 times before returning a result for
each channel. At the end of this cycle, the results are all written
to the output registers.
The ADC samples single-sided inputs with respect to the AGND
pin. A 0 V input gives out Code 0, and an input equal to the
voltage on REFIN gives out full code (4095 decimal).
The inputs to the ADC come directly from the VXn pins and
from the back of the input attenuators on the VPn and VH pins,
as shown in Figure 30 and Figure 31.
DIGITIZED
VOLTAGE
READING
NO ATTENUATION
12-BIT
ADC
04609-025
VXn
2.048V VREF
ATTENUATION NETWORK
(DEPENDS ON RANGE SELECTED)
DIGITIZED
VOLTAGE
READING
04609-026
12-BIT
ADC
2.048V VREF
Figure 31. ADC Reading on VPn/VH Pins
The voltage at the input pin can be derived from the following
equation:
V=
ADC Code
4095
Attenuation Factor
1
2.181
4.363
10.472
ADC Input Voltage
Range (V)
0–2.048
0–4.46
0–6.01
0–14.41
_______________________________________________
1
The upper limit is the absolute maximum allowed voltage on these pins.
The normal way to supply the reference to the ADC on the
REFIN pin is to simply connect the REFOUT pin to the REFIN
pin. REFOUT provides a 2.048 V reference. As such, the
supervising range covers less than half of the normal ADC
range. It is possible, however, to provide the ADC with a more
accurate external reference for improved readback accuracy.
Supplies can also be connected to the input pins purely for ADC
readback, even though they might go above the expected supervisory range limits (but not above 6 V, because this violates the
absolute maximum ratings on these pins). For instance, a 1.5 V
supply connected to the VX1 pin can be correctly read out as an
ADC code of approximately 3/4 full scale, but it always sits
above any supervisory limits that can be set on that pin. The
maximum setting for the REFIN pin is 2.048 V.
SUPPLY SUPERVISION WITH THE ADC
Figure 30. ADC Reading on VXn Pins
VPn/VH
Table 8. ADC Input Voltage Ranges
SFD Input
Range (V)
0.573–1.375
1.25–3
2.5–6
4.8–14.4
× Attenuation Factor × 2.048 V
The ADC input voltage ranges for the SFD input ranges are
listed in Table 8.
In addition to the readback capability, a further level of supervision is provided by the on-chip 12-bit ADC. The ADM1066 has
limit registers on which the user can program to a maximum or
minimum allowable threshold. Exceeding the threshold generates
a warning that can either be read back from the status registers
or input into the SE to determine what sequencing action the
ADM1066 should take. Only one register is provided for each
input channel, so a UV or OV threshold (but not both) can be
set for a given channel. The round-robin circuit can be enabled
via an SMBus write, or it can be programmed to turn on in any
state in the SE program. For example, it can be set to start once
a power-up sequence is complete and all supplies are known to
be within expected tolerance limits.
Note that a latency is built into this supervision, dictated by the
conversion time of the ADC. With all 12 channels selected, the
total time for the round-robin operation (averaging off) is
approximately 6 ms (500 µs per channel selected). Supervision
using the ADC, therefore, does not provide the same real time
response as the SFDs.
Rev. 0 | Page 20 of 32
ADM1066
SUPPLY MARGINING
OVERVIEW
CLOSED-LOOP SUPPLY MARGINING
It is often necessary for the system designer to adjust supplies,
either to optimize their level or force them away from nominal
values to characterize the system performance under these
conditions. This is a function typically performed during an incircuit test (ICT), such as when the manufacturer, for example,
wants to guarantee that the product under test functions
correctly at nominal supplies minus 10%.
A much more accurate and comprehensive method of margining is to implement a closed-loop system. The voltage on the
rail to be margined can be read back so that the rail can be
accurately margined to the target voltage. The ADM1066
incorporates all the circuits required to do this, with the 12-bit
successive approximation ADC used to read back the level of
the supervised voltages, and the six voltage output DACs,
implemented as described in the Open-Loop Margining section,
used to adjust supply levels. These circuits can be used along
with some other intelligence such as a microcontroller to
implement a closed-loop margining system that allows any
dc/dc or LDO supply to be set to any voltage, accurate to within
±0.5% of the target.
OPEN-LOOP MARGINING
The simplest method of margining a supply is to implement an
open-loop technique. A popular method for this is to switch
extra resistors into the feedback node of a power module, such
as a dc/dc converter or low dropout regulator (LDO). The extra
resistor alters the voltage at the feedback or trim node and
forces the output voltage to margin up or down by a certain
amount.
µCONTROLLER
VIN
ADM1066
VIN
µCONTROLLER
VOUT
DEVICE
CONTROLLER
(SMBus)
FEEDBACK
GND
ATTENUATION
RESISTOR
DACOUTn
Figure 32. Open-Loop Margining System Using the ADM1066
The ADM1066 can be commanded to margin a supply up or
down over the SMBus by updating the values on the relevant
DAC output.
ADC
R1
DACOUTn
FEEDBACK
R2
GND
DAC
DEVICE
CONTROLLER
(SMBus)
PCB
TRACE NOISE
DECOUPLING
CAPACITOR
Figure 33. Closed-Loop Margining System Using the ADM1066
To implement closed-loop margining:
1.
Disable the six DACn outputs.
2.
Set the DAC output voltage equal to the voltage on the
feedback node.
3.
Enable the DAC.
4.
Read the voltage at the dc/dc output, which is connected to
one of the VP1–4, VH, or VX1–5 pins.
5.
If necessary, modify the DACn output code up or down to
adjust the dc/dc output voltage; otherwise, stop, because
the target voltage has been reached.
6.
Set the DAC output voltage to a value that alters the supply
output by the required amount (for example, ±5%).
7.
Repeat from Step 4.
DAC
PCB
TRACE NOISE
DECOUPLING
CAPACITOR
04609-067
DC/DC
CONVERTER
MUX
ATTENUATION
RESISTOR, R3
OUTPUT
ADM1066
OUTPUT
VH/VPn/VXn
DC/DC
CONVERTER
04609-034
The ADM1066 can perform open-loop margining for up to six
supplies. The six on-board voltage DACs (DAC1–6) can drive
into the feedback pins of the power modules to be margined.
The simplest circuit to implement this function is an attenuation resistor, which connects the DACn pin to the feedback
node of a dc/dc converter. When the DACn output voltage is set
equal to the feedback voltage, no current flows in the attenuation resistor, and the dc/dc output voltage does not change.
Taking DACn above the feedback voltage forces current into the
feedback node, and the output of the dc/dc converter is forced
to fall to compensate for this. The dc/dc output can be forced
high by setting the DACn output voltage lower than the
feedback node voltage. The series resistor can be split in two,
and the node between them decoupled with a capacitor to
ground. This can help to decouple any noise picked up from the
board. Decoupling to a ground local to the dc/dc converter is
recommended.
Steps 1 to 3 ensure that when the DACn output buffer is turned
on it has little effect on the dc/dc output. The DAC output buffer
is designed to power up without glitching by first powering up
the buffer to follow the pin voltage. It does not drive out onto
the pin at this time. Once the output buffer is properly enabled,
the buffer input is switched over to the DAC, and the output
stage of the buffer is turned on. Output glitching is negligible.
Rev. 0 | Page 21 of 32
ADM1066
WRITING TO THE DACs
Four DAC ranges are offered. They can be placed with midcode
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are
placed to correspond to the most common feedback voltages.
Centering the DAC outputs in this way provides the best use of
the DAC resolution. For most supplies it is possible to place the
DAC midcode at the point where the dc/dc output is not
modified, thereby giving half of the DAC range to margin up
and the other half to margin down.
The DAC output voltage is set by the code written to the DACn
register. The voltage is linear with the unsigned binary number
in this register. Code 0x7F is placed at the midcode voltage, as
described previously. The output voltage is given by the
following equation:
DAC Output = (DACn − 0x7F)/255 × 0.6015 + VOFF
where VOFF is one of the four offset voltages.
There are 256 DAC settings available. The midcode value is
located at DAC code 0x7F as close as possible to the middle
of the 256 code range. The full output swing of the DACs is
+302 mV (+128 codes) and −300 mV (−127 codes) around the
selected midcode voltage. The voltage range for each midcode
voltage is shown in Table 9.
Table 9. Ranges for Midcode Voltages
Midcode
Voltage (V)
0.6
0.8
1.0
1.25
Minimum Voltage
Output (V)
0.300
0.500
0.700
0.950
Maximum Voltage
Output (V)
0.902
1.102
1.302
1.552
CHOOSING THE SIZE OF THE ATTENUATION
RESISTOR
How much this DAC voltage swing affects the output voltage of
the dc/dc converter that is being margined is determined by the
size of the attenuation resistor, R3 (see Figure 33).
Because the voltage at the feedback pin remains constant, the
current flowing from the feedback node to GND via R2 is a
constant. Also, the feedback node itself is high impedance. This
means that the current flowing through R1 is the same as the
current flowing through R3. Therefore, direct relationship exists
between the extra voltage drop across R1 during margining and
the voltage drop across R3.
This relationship is given by the equation
∂VOUT =
R1
(VFB − VDACOUT)
R3
where:
∂VOUT is the change in VOUT.
VFB is the voltage at the feedback node of the dc/dc converter.
VDACOUT is the voltage output of the margining DAC.
This equation demonstrates that, if the user wants the output
voltage to change by ±300 mV, then R1 = R3. If the user wants
the output voltage to change by ±600 mV, then R1 = 2 × R3, and
so on.
It is best to use the full DAC output range to margin a supply.
Choosing the attenuation resistor in this way provides the most
resolution from the DAC. In other words, with one DAC code
change, the smallest effect on the dc/dc output voltage is
induced. If the resistor is sized up to use a code such as 27(dec)
to 227(dec) to move the dc/dc output by ±5%, then it takes
100 codes to move 5% (each code moves the output by 0.05%).
This is beyond the readback accuracy of the ADC, but should
not prevent the user from building a circuit to use the most
resolution.
DAC LIMITING/OTHER SAFETY FEATURES
Limit registers (called DPLIMn and DNLIMn) on the device
offer the user some protection from firmware bugs, which can
cause catastrophic board problems by forcing supplies beyond
their allowable output ranges. Essentially, the DAC code written
into the DACn register is clipped such that the code used to set
the DAC voltage is actually given by
DAC Code
= DACn, DACn ≥ DNLIMn and DACn ≤ DPLIMn
= DNLIMn,
DACn < DNLIMn
= DPLIMn,
DACn > DPLIMn
In addition, the DAC output buffer is three-stated, if DNLIMn >
DPLIMn. By programming the limit registers in this way, the
user can make it very difficult for the DAC output buffers to be
turned on at all during normal system operation (these are
among the registers downloaded from EEPROM at startup).
Rev. 0 | Page 22 of 32
ADM1066
APPLICATIONS DIAGRAM
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-DC1
EN
VH
5V OUT
3V OUT
3.3V OUT
2.5V OUT
1.8V OUT
1.2V OUT
0.9V OUT
OUT
3.3V OUT
ADM1066
VP1
VP2
VP3
VP4
VX1
VX2
VX3
PDO1
PDO2
VX4
PDO6
IN
DC-DC2
PDO3
PDO4
PDO5
EN
OUT
2.5V OUT
POWER_GOOD
POWER_ON
SIGNAL_VALID
RESET_L
PDO7
IN
SYSTEM RESET
VX5
DC-DC3
PDO8
EN
PDO9
PDO10
OUT
1.8V OUT
3.3V OUT
DAC1*
IN
REFIN VCCP VDDCAP GND
LDO
10µF
10µF
EN
10µF
OUT
0.9V OUT
3.3V OUT
*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC6
WILL ALLOW MARGINING FOR UP TO
SIX VOLTAGE RAILS.
IN
OUT
EN
1.2V OUT
TRIM
04608-068
DC-DC4
Figure 34. Applications Diagram
Rev. 0 | Page 23 of 32
ADM1066
COMMUNICATING WITH THE ADM1066
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1066 (UV/OV thresholds, glitch
filter timeouts, PDO configurations, and so on) is dictated by
the contents of RAM. The RAM is comprised of digital latches
that are local to each of the functions on the device. The latches
are double-buffered and have two identical latches, Latch A and
Latch B. Therefore, when an update to a function occurs, the
contents of Latch A are updated first, and then the contents of
Latch B are updated with identical data. The advantages of this
architecture are explained in detail in this section.
The latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in steps, as follows:
1.
With no power applied to the device, the PDOs are all high
impedance.
2.
When 1 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPn), the PDOs are all weakly
pulled to GND with a 20 kΩ impedance.
3.
When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
4.
The EEPROM downloads its contents to all Latch As.
5.
Once the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
6.
At 0.5 ms after the configuration download completes, the
first state definition is downloaded from EEPROM into
the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1066 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
EEPROM into the RAM registers, the user might need to alter
the configuration of functions on the ADM1066, such as changing the UV or OV limit of an SFD, changing the fault output of
an SFD, or adjusting the rise time delay of one of the PDOs.
The ADM1066 provides several options that allow the user to
update the configuration over the SMBus interface. The
following options are controlled in the UPDCFG register:
1.
Update the configuration in real time. The user writes to
RAM across the SMBus and the configuration is updated
immediately.
2.
Update the Latch As without updating the Latch Bs. With
this method, the configuration of the ADM1066 remains
unchanged and continues to operate in the original setup
until the instruction is given to update the Latch Bs.
3.
Change EEPROM register contents without changing the
RAM contents, and then download the revised EEPROM
contents to the RAM registers. Again, with this method, the
configuration of the ADM1066 remains unchanged and
continues to operate in the original setup until the
instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents, if
revisions to the configuration are unsatisfactory. For example, if
the user needs to alter an OV threshold, this can be done by
updating the RAM register as described in Option 1. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, then the device controller can
issue a command to download the EEPROM contents to the
RAM again, as described in Option 3, restoring the ADM1066
to its original configuration.
The topology of the ADM1066 makes this type of operation
possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1
leaves the double-buffered latches open at all times. If Bit 0 is set
to 0, then, when a RAM write occurs across the SMBus, only the
first side of the double-buffered latch is written to. The user
must then write a 1 to Bit 1 of the UPDCFG register. This
generates a pulse to update all the second latches at once.
EEPROM writes occur in a similar way.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If low, then the contents of a page
cannot be erased, even if the command code for page erasure is
programmed across the SMBus. The bitmap for the UPDCFG
register is shown in the AN-698 application note. A flow chart
for download at power-up and subsequent configuration
updates is shown in Figure 35.
Rev. 0 | Page 24 of 32
ADM1066
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH A
LATCH B
EEPROM
FUNCTION
(OV THRESHOLD
ON VP1)
04609-035
POWER-UP
(VCC > 2.5V)
Figure 35. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has its own
dedicated 512-byte EEPROM for storing state definitions,
providing 63 individual states with a 64-bit word each (one state
is reserved). At power-up, the first state is loaded from the SE
EEPROM into the engine itself. When the conditions of this
state are met, the next state is loaded from EEPROM into the
engine, and so on. The loading of each new state takes approximately 10 µs.
To alter a state, the required changes must be made directly to
EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to EEPROM.
INTERNAL REGISTERS
The ADM1066 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADM1066, the first byte
of data is always a register address, which is written to the
address pointer register.
The major differences between the EEPROM and other
registers are
•
An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.
•
Writing to EEPROM is slower than writing to RAM.
•
Writing to the EEPROM should be restricted, because it
has a limited write/cycle life of typically 10,000 write
operations due to the usual EEPROM wear-out
mechanisms.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Pages 0 to 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1066 (the
SFDs, PDOs, and so on). These EEPROM addresses are the
same as the RAM register addresses, prefixed by F8. Page 7 is
reserved. Pages 8 to 15 are for customer use.
Data can be downloaded from EEPROM to RAM in one of the
following ways:
•
At power-up, when Pages 0 to 6 are downloaded.
•
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Pages 0 to 6.
Configuration Registers
SERIAL BUS INTERFACE
These registers provide control and configuration for various
operating parameters of the ADM1066.
The ADM1066 is controlled via the serial system management
bus (SMBus). The ADM1066 is connected to this bus as a slave
device, under the control of a master device. It takes approximately 1 ms after power-up for the ADM1066 to download
from its EEPROM. Therefore, access to the ADM1066 is restricted until the download is completed.
EEPROM
The ADM1066 has two 512-byte cells of nonvolatile, electrically
erasable, programmable read-only memory (EEPROM), from
Register Addresses 0xF800 to 0xFBFF. The EEPROM is used for
permanent storage of data that is not lost when the ADM1066 is
powered down. One EEPROM cell contains the configuration
data of the device; the other contains the state definitions for
the SE. Although referred to as read-only memory, the
EEPROM can be written to as well as read from via the serial
bus in exactly the same way as the other registers.
Identifying the ADM1066 on the SMBus
The ADM1060 has a 7-bit serial bus slave address. The device is
powered up with a default serial bus address. The five MSBs of
the address are set to 01101; the two LSBs are determined by the
logical states of Pins A1 and A0. This allows the connection of
four ADM1066s to one SMBus.
Rev. 0 | Page 25 of 32
ADM1066
The device also has several identification registers (read-only),
which can be read across the SMBus. Table 10 lists these registers
with their values and functions.
All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the
R/W bit is a 0, the master writes to the slave device. If the
R/W bit is a 1, the master reads from the slave device.
Table 10. Identification Register Values and Functions
Name
MANID
Address
0xF4
Value
0x41
REVID
MARK1
MARK2
0xF5
0xF6
0xF7
0x00
0x00
0x00
Function
Manufacturer ID for Analog
Devices
Silicon revision
S/w brand
S/w brand
2.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-tohigh transition when the clock is high might be interpreted
as a stop signal. If the operation is a write operation, the
first data byte after the slave address is a command byte.
This tells the slave device what to expect next. It might be
an instruction telling the slave device to expect a block
write, or it might simply be a register address that tells the
slave where subsequent data is to be written. Because data
can flow in only one direction, as defined by the R/W bit,
sending a command to a slave device during a read
operation is not possible. Before a read operation, it might
be necessary to perform a write operation to tell the slave
what sort of read operation to expect and/or the address
from which data is to be read.
3.
When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the
data line high during the 10th clock pulse to assert a stop
condition. In read mode, the master device releases the
SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as no acknowledge. The master then takes the data
line low during the low period before the tenth clock pulse,
then high during the tenth clock pulse to assert a stop
condition.
General SMBus Timing
Figure 36, Figure 37, and Figure 38 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data-line SDA, while the serial clock-line SCL remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, consisting of a 7-bit
slave address (MSB first) plus a R/W bit. This bit determines the direction of the data transfer, that is, whether
data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse.
1
9
1
9
SCL
0
SDA
1
1
0
1
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
D0
ACK. BY
SLAVE
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
DATA BYTE
D1
D0
D7
ACK. BY
SLAVE
D6
D5
D4
D2
FRAME N
DATA BYTE
Figure 36. General SMBus Write Timing Diagram
Rev. 0 | Page 26 of 32
D3
D1
D0
ACK. BY
SLAVE
STOP
BY
MASTER
04609-036
1.
ADM1066
1
9
1
9
SCL
0
SDA
1
1
0
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
1
D0
ACK. BY
MASTER
FRAME 1
SLAVE ADDRESS
9
1
FRAME 2
DATA BYTE
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
DATA BYTE
D1
D0
D7
D6
D5
D4
ACK. BY
MASTER
D3
D2
D1
D0
NO ACK.
FRAME N
DATA BYTE
STOP
BY
MASTER
04609-037
SDA
(CONTINUED)
Figure 37. General SMBus Read Timing Diagram
tR
tF
t HD; STA
t LO W
SCL
t HI G H
t HD; STA
t HD; DAT
t SU; STA
t SU; STO
t SU; DAT
t BUF
P
S
S
P
04609-038
SDA
Figure 38. Serial Bus Timing Diagram
SMBus Protocols for RAM and EEPROM
Data can be written to and read from both RAM and EEPROM
as single data bytes. Data can be written only to unprogrammed
EEPROM locations. To write new data to a programmed location, it must first be erased. EEPROM erasure cannot be done at
the byte level. The EEPROM is arranged as 32 pages of 32 bytes
each, and an entire page must be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in the diagrams:
S
P
R
W
A
Start
Stop
Read
Write
Acknowledge
A
No acknowledge
The ADM1066 uses the following SMBus write protocols.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
In the ADM1066, the send byte protocol is used for two
purposes:
•
To write a register address to RAM for a subsequent single
byte read from the same address, or a block read or write
starting at that address, as shown in Figure 39.
1
S
2
SLAVE
ADDRESS
W
3
4
5
6
A
REGISTER
ADDRESS
(0x00 TO 0xDF)
A
P
04609-039
The ADM1066 contains volatile registers (RAM) and nonvolatile registers (EEPROM). User RAM occupies address locations
from 0x00 to 0xDF; EEPROM occupies addresses from 0xF800
to 0xFBFF.
Figure 39. Setting a RAM Address for Subsequent Read
Rev. 0 | Page 27 of 32
ADM1066
S
2
SLAVE
ADDRESS
W
3
4
5
6
A
COMMAND
BYTE
(0xFE)
A
P
To write a single byte of data to RAM. In this case, the
command byte is the RAM address from 0x00 to 0xDF and
the only data byte is the actual data, as shown in Figure 41.
1
•
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
6
7 8
DATA A P
2
3
4
5
6
7 8
Figure 42. Setting an EEPROM Address
Note, for page erasure, that because a page consists of
32 bytes, only the three MSBs of the address low byte are
important. The lower five bits of the EEPROM address low
byte specify the addresses within a page and are ignored
during an erase operation.
Write Byte/Word
2.
5
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S
W A
A
A P
ADDRESS
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
As soon as the ADM1066 receives the command byte, page
erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1066 is
accessed before erasure is complete, it responds with a no
acknowledge (NACK).
The master device asserts a start condition on SDA.
4
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of the EEPROM address
from 0xF8 to 0xFB. The only data byte is the low byte of
the EEPROM address, as shown in Figure 42.
1
1.
3
Figure 41. Single Byte Write to RAM
Figure 40. EEPROM Page Erasure
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device, as
follows:
2
RAM
S SLAVE W A
ADDRESS
A
ADDRESS
(0x00 TO 0xDF)
•
To write a single byte of data to EEPROM. In this case, the
command byte is the high byte of the EEPROM address
from 0xF8 to 0xFB. The first data byte is the low byte of the
EEPROM address, and the second data byte is the actual
data, as shown in Figure 43.
1
2
3
4
5
6
7
8
9 10
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S
W A
A
A DATA A P
ADDRESS
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
04609-043
1
•
04609-040
The master sends a command code that tells the slave
device to erase the page. The ADM1066 command code for
a page erasure is 0xFE (1111 1110). Note that, for a page
erasure to take place, the page address has to be given in
the previous write word transaction (see the Write
Byte/Word section). Also, Bit 2 in the UPDCFG register
(Address 0x90) must be set to 1.
In the ADM1066, the write byte/word protocol is used for three
purposes:
04609-041
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before
writing to one or more EEPROM memory locations that
are already programmed, the page or pages containing
those locations must first be erased. EEPROM memory is
erased by writing a command byte.
04609-042
•
Figure 43. Single Byte Write to EEPROM
Block Write
5.
The slave asserts ACK on SDA.
6.
The master sends a data byte.
7.
The slave asserts ACK on SDA.
8.
The master sends a data byte (or asserts a stop condition at
this point).
9.
The slave asserts ACK on SDA.
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1066, a send byte operation sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by
the write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code that tells the slave
device to expect a block write. The ADM1066 command
code for a block write is 0xFC (1111 1100).
10. The master asserts a stop condition on SDA to end the
transaction.
Rev. 0 | Page 28 of 32
ADM1066
The slave asserts ACK on SDA.
6.
The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7.
The slave asserts ACK on SDA.
8.
The master sends N data bytes.
9.
The slave asserts ACK on SDA after each data byte.
In the ADM1066, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 45.
1
2
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
04609-045
5.
Figure 45. Single Byte Read from EEPROM or RAM
Block Read
10. The master asserts a stop condition on SDA to end the
transaction.
2
3
4
5
6
7
8
9
10
S SLAVE
W A COMMAND 0xFC A BYTE A DATA A DATA A DATA A P
COUNT
(BLOCK WRITE)
ADDRESS
1
N
2
04609-044
1
Figure 44. Block Write to EEPROM or RAM
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except
•
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF), to avoid writing to
invalid addresses.
•
If the addresses cross a page boundary, both pages must be
erased before programming.
Note that the ADM1066 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 µs, which would limit the SMBus clock for
repeated or block write operations. The ADM1066 pulls SCL
low and extends the clock pulse when it cannot accept any
more data.
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1066, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as
follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code that tells the slave
device to expect a block read. The ADM1066 command
code for a block read is 0xFD (1111 1101).
5.
The slave asserts ACK on SDA.
6.
The master asserts a repeat start condition on SDA.
7.
The master sends the 7-bit slave address followed by the
read bit (high).
8.
The slave asserts ACK on SDA.
9.
The ADM1066 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1066
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus 1.1 specification.
READ OPERATIONS
The ADM1066 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts no acknowledge on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
10. The master asserts ACK on SDA.
11. The master receives 32 data bytes.
12. The master asserts ACK on SDA after each data byte.
13. The master asserts a stop condition on SDA to end the
transaction.
Rev. 0 | Page 29 of 32
ADM1066
2
3
4
5 6
7
8
9
10
11
12
2.
S SLAVE
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
P
04609-046
13 14
DATA
A
32
Figure 46. Block Read from EEPROM or RAM
C(x) = x8 + x2 + x1 + 1
See the SMBus 1.1 specification for details.
Error Correction
The ADM1066 provides the option of issuing a PEC (packet
error correction) byte after a write to RAM, a write to EEPROM,
a block write to RAM/EEPROM, or a block read from RAM/
EEPROM. This enables the user to verify that the data received
by or sent from the ADM1066 is correct. The PEC byte is an
optional byte sent after that last data byte has been written to or
read from the ADM1066. The protocol is as follows:
1.
A no acknowledge (NACK) is generated after the PEC byte
to signal the end of the read.
An example of a block read with the optional PEC byte is
shown in Figure 47.
1
2
3
4
5 6
7
8
9
10
11
12
S SLAVE
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
The ADM1066 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
Rev. 0 | Page 30 of 32
13 14 15
DATA
32
A PEC A P
Figure 47. Block Read from EEPROM or RAM with PEC
04609-047
1
ADM1066
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
30
PIN 1
INDICATOR
0.50
BSC
5.75
BCS SQ
TOP
VIEW
1.00
0.85
0.80
1
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOTTO M VIEW)
0.50
0.40
0.30
12° MAX
40
21
20
10
11
0.25 MIN
4.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 48. 40-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-40)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00
BSC SQ
37
36
48
1
SEATING
PLANE
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
VIEW A
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
12
25
24
13
0.50
BSC
0.27
0.22
0.17
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 49. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1066ACP
ADM1066ACP-REEL
ADM1066ACP-REEL7
ADM1066ASU
ADM1066ASU-REEL
ADM1066ASU-REEL7
EVAL-ADM1066LFEB
EVAL-ADM1066TQEB
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Description
40-Lead LFCSP
40-Lead LFCSP
40-Lead LFCSP
48-Lead TQFP
48-Lead TQFP
48-Lead TQFP
ADM1066 Evaluation Kit (LFSCP Version)
ADM1066 Evaluation Kit (TQFP Version)
Rev. 0 | Page 31 of 32
Package Option
CP-40
CP-40
CP-40
SU-48
SU-48
SU-48
ADM1066
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04609–0–10/04(0)
Rev. 0 | Page 32 of 32
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