TC74VHC299F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC299F,TC74VHC299FT 8-Bit Pipo Shift Register with Asynchronous Clear The TC74VHC299 is an advanced high speed CMOS 8-BIT PIPO SHIFT REGISTER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA) controlled by the two selection inputs (S0, S1). When one or both enable ( G1 , G2 ) are high, the eight I/O are forced to the high-impedance state; however, sequential operation or clearing of the register is not affected. All inputs are equipped with protection circuits against static discharge. TC74VHC299F TC74VHC299FT Features (Note 1) (Note 2) (Note 3) • High speed: fmax = 160 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • • High noise immunity: VNIH = VNIL = 28% VCC (min) ∼ tpHL Balanced propagation delays: tpLH − • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • Low noise: VOLP = 1.4 V (max) • Pin and function compatible with 74ALS299 Weight SOP20-P-300-1.27A TSSOP20-P-0044-0.65A : 0.22 g (typ.) : 0.08 g (typ.) Note 1: Do not apply a signal to A/QA to H/QH bus terminal when it is in the output mode. Damage may result. Note 2: All floating (high impedance) A/QA to H/QH bus terminals must have their input levels fixed by means of pull up or pull down resistors. Note 3: A parasitic diode is formed between A/QA to H/QH bus and VCC terminals. Therefore bus terminal can not be used to interface 5 V to 3 V systems directly. 1 2007-10-01 TC74VHC299F/FT Pin Assignment IEC Logic Symbol CLR G1 G2 S0 S1 CK S0 1 20 VCC G1 2 19 S1 G2 3 18 SL G/QG 4 17 QH’ E/QE 5 16 H/QH SR A/QA C/QC 6 15 F/QF B/QB A/QA 7 14 D/QD C/QC QA’ 8 13 B/QB D/QD CLR 9 12 CK 11 (2) (3) (1) (19) (12) (11) (7) (13) (6) SR G/QG H/QH (top view) SL R & 0 1 SRG 8 3 EN 13 M 0 3 C4/1→/2← (8) 1, 4D 3, 4D 5, 13 3, 4D 6, 13 Z5 3, 4D 12, 13 2, 4D Z12 QA’ Z6 (14) (5) E/QE F/QF GND 10 (9) (15) (4) (16) (18) (17) QH’ Truth Table Inputs /Outputs Inputs Mode CLR Z Clear Hold Shift Right Shift Left Load Note: Function Select Output Control Outputs Serial A/QA H/QH QA’ QH’ X Z Z L L X X L L L L X X X L L L L X X X QA0 QH0 QA0 QH0 L X H H QGn H QGn L L X L L QGn L QGn L L L H X QBn H QBn H L L L L X QBn L QBn L H X X X X a h a h S1 S0 G1 (Note) G2 (Note) L H H X X L L X L L X L H L H CK SL SR X X L X L L L L L L H L H L H H H H H H H When one or both output controls are high, the eight input/output terminals are in the high-impedance state; however sequential or clearing of the register is not affected. Z: High impedance Qn0: The level of Qn before the indicated steady-state input conditions were established. Qnn: The level of Qn before the most recent active transition indicated by ↓ or ↑. a, h: The level of the steady-state inputs A, H, respectively. X: Don’t care. 2 2007-10-01 TC74VHC299F/FT Timing Chart CK Mode Control Inputs S0 S1 CLR Serial Data Inputs SR Outputs QA’ SL A/QA B/QB C/DC Inputs/ Outputs D/QD E/QE F/QF G/QG H/QH Outputs QH’ CLEAR LOAD SHIFT RIGHT SHIFT LEFT 3 HOLD CLEAR 2007-10-01 TC74VHC299F/FT System Diagram SL QH’ 17 18 CK D R Q 16 H/QH Q 4 G/QG CK D R CK D R Q 15 F/QF Q 5 E/QE Q 14 D/QD Q 6 C/QC Q 13 B/QB Q 7 A/QA CK D R CK D R CK D R CK D R CK D S0 S1 R 1 19 11 SR 12 CK 4 8 9 2 3 QA’ CLR G1 G2 2007-10-01 TC74VHC299F/FT Absolute Maximum Ratings (Note) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7.0 V DC input voltage VIN −0.5 to 7.0 V VIN/OUT −0.5 to VCC + 0.5 V VOUT −0.5 to VCC + 0.5 V Input diode current IIK −20 mA Output diode current IOK ±20 mA DC output current IOUT ±25 mA DC VCC/ground current ICC ±80 mA Power dissipation PD 180 mW Storage temperature Tstg −65 to 150 °C DC bus I/O voltage (A/QA to H/QH’) DC output voltage (QA’ to QH’) Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2.0 to 5.5 V Input voltage VIN 0 to 5.5 V VIN/OUT 0 to VCC V VOUT 0 to VCC V Operating temperature Topr −40 to 85 °C Input rise and fall time dt/dV DC bus I/O voltage (A/QA to H/QH) DC output voltage (QA’ to QH’) Note: 0 to 100 (VCC = 3.3 ± 0.3 V) 0 to 20 (VCC = 5 ± 0.5 V) ns/V The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 5 2007-10-01 TC74VHC299F/FT Electrical Characteristics DC Characteristics Characteristics Test Condition Symbol Min 2.0 1.50 3.0 to 5.5 ― ― VCC × 0.7 ― ― ― ― 3.0 to 5.5 ― ― VCC × 0.3 ― VCC × 0.3 2.0 1.9 2.0 ― 1.9 ― 3.0 2.9 3.0 ― 2.9 ― 4.5 4.4 4.5 ― 4.4 ― IOH = −4 mA 3.0 2.58 ― ― 2.48 ― IOH = −8 mA 4.5 3.94 ― ― 3.80 ― 2.0 ― 0.0 0.1 ― 0.1 3.0 ― 0.0 0.1 ― 0.1 4.5 ― 0.0 0.1 ― 0.1 IOL = 4 mA 3.0 ― ― 0.36 ― 0.44 IOL = 8 mA 4.5 ― ― 0.36 ― 0.44 5.5 ― ― ±0.25 ― ±2.50 μA ― Low-level input voltage VIL ― 2.0 IOH = −50 μA VOH VIN = VIH or VIL IOL = 50 μA VOL VIN = VIH or VIL VIN = VIH or VIL 0.50 Min Unit Max VIH Low-level output voltage VCC (V) Typ. High-level input voltage High-level output voltage Ta = −40 to 85°C Ta = 25°C 1.50 VCC × 0.7 ― Max ― ― V 0.50 V V V 3-state output off-state current IOZ Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 ― ― ±0.1 ― ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 5.5 ― ― 4.0 ― 40.0 μA VOUT = VCC or GND 6 2007-10-01 TC74VHC299F/FT AC Characteristics (input: tr = tf = 3 ns) Characteristics Test Condition Symbol VCC (V) Propagation delay time tpLH (CK-QA’, QH’) tpHL Propagation delay time tpLH (CK-QA to QH) tpHL Max Min Max 15 ― 12.2 17.2 1.0 19.8 50 ― 14.7 20.7 1.0 23.3 15 ― 8.5 10.8 1.0 12.0 50 ― 10.0 12.8 1.0 14.0 15 ― 13.0 19.0 1.0 22.0 50 ― 15.5 22.5 1.0 25.5 15 ― 9.1 11.2 1.0 13.5 50 ― 10.8 13.2 1.0 15.5 15 ― 10.3 14.3 1.0 16.6 50 ― 12.8 17.8 1.0 20.1 15 ― 7.3 9.1 1.0 10.4 50 ― 8.8 11.1 1.0 12.4 15 ― 10.8 17.0 1.0 19.5 50 ― 13.3 20.5 1.0 23.0 15 ― 7.7 10.5 1.0 12.0 50 ― 9.2 12.5 1.0 14.0 15 ― 13.3 16.5 1.0 19.2 50 ― 14.8 19.0 1.0 21.7 15 ― 8.9 9.7 1.0 11.3 50 ― 10.4 11.2 1.0 12.6 3.3 ± 0.3 50 ― 18.0 21.3 1.0 24.3 5.0 ± 0.5 50 ― 11.8 13.2 1.0 15.0 15 65 100 ― 55 ― 50 55 90 ― 50 ― 15 125 160 ― 110 ― 50 115 150 ― 100 ― ― 5.0 ± 0.5 ― 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 tpHL ― ( CLR -QA to QH) Output disable time Typ. 5.0 ± 0.5 Propagation delay time Output enable time Min 3.3 ± 0.3 ( CLR -QA’, QH’) Propagation delay time CL (pF) 3.3 ± 0.3 tpHL 5.0 ± 0.5 tpZL tpZH tpLZ tpHZ 3.3 ± 0.3 RL = 1 kΩ 5.0 ± 0.5 RL = 1 kΩ 3.3 ± 0.3 Maximum clock frequency fmax ― 5.0 ± 0.5 Input capacitance Bus I/O capacitance (A/QA to H/QH) Power dissipation capacitance Note: Ta = −40 to 85°C Ta = 25°C Unit ns ns ns ns ns ns MHz CIN ― ― 4 10 ― ― pF COUT ― ― 8 ― ― ― pF ― 110 ― ― ― pF (Note) CPD CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN + ICC 7 2007-10-01 TC74VHC299F/FT Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Minimum pulse width tw (H) (CK) tw (L) Minimum pulse width ( CLR ) Minimum set-up time (SL, SR) Minimum set-up time (A to H) Minimum set-up time (S0, S1) Minimum hold time (SL, SR) Minimum hold time (A to H) Minimum hold time (S0, S1) Minimum removal time ( CLR ) Test Condition ― tw (L) ― ts ― ts ― ts ― th ― th ― th ― trem ― Ta = 25°C Ta = −40 to 85°C VCC (V) Typ. Limit Limit 3.3 ± 0.3 ― 7.0 8.0 5.0 ± 0.5 ― 7.0 8.0 3.3 ± 0.3 ― 6.0 7.0 5.0 ± 0.5 ― 6.0 7.0 3.3 ± 0.3 ― 8.5 10.0 5.0 ± 0.5 ― 5.0 5.0 3.3 ± 0.3 ― 8.0 9.0 5.0 ± 0.5 ― 4.0 4.0 3.3 ± 0.3 ― 14.5 17.0 5.0 ± 0.5 ― 7.0 8.0 3.3 ± 0.3 ― 1.0 1.0 5.0 ± 0.5 ― 1.0 1.0 3.3 ± 0.3 ― 0.5 0.5 5.0 ± 0.5 ― 1.5 1.5 3.3 ± 0.3 ― 0 0 5.0 ± 0.5 ― 0.5 0.5 3.3 ± 0.3 ― 5.0 6.0 5.0 ± 0.5 ― 4.0 4.0 Unit ns ns ns ns ns ns ns ns ns Noise Characteristics (input: tr = tf = 3 ns) Characteristics Quiet output maximum dynamic Test Condition Symbol Ta = 25°C VCC (V) Typ. Limit Unit VOLP CL = 50 pF 5.0 0.9 1.2 V VOLV CL = 50 pF 5.0 −0.9 −1.2 V Minimum high level dynamic input Voltage VIHD CL = 50 pF 5.0 ― 3.5 V Maximum low high level dynamic input Voltage VILD CL = 50 pF 5.0 ― 1.5 V VOL Quiet output minimum dynamic VOL 8 2007-10-01 TC74VHC299F/FT Input Equivalent Circuit INPUT A/QA to H/QH Bus Terminal Equivalent Circuit I/O 9 2007-10-01 TC74VHC299F/FT Package Dimensions Weight: 0.22 g (typ.) 10 2007-10-01 TC74VHC299F/FT Package Dimensions Weight: 0.08 g (typ.) 11 2007-10-01 TC74VHC299F/FT RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 12 2007-10-01