SPICE Device Model SUM50N03-13LC Vishay Siliconix N-Channel 30-V (D-S) 175°C MOSFET with Sense Terminal CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71918 09-Jun-04 www.vishay.com 1 SPICE Device Model SUM50N03-13LC Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250 µA 1.8 ID(on) VDS = 5 V, VGS = 10 V 434 VGS = 10 V, ID = 25 A 0.010 0.010 VGS = 10 V, ID = 25 A, TJ = 125°C 0.016 0.016 VGS = 10 V, ID = 25 A, TJ = 175°C 0.018 0.018 VGS = 4.5 V, ID = 24 A 0.014 0.014 IS = 50 A, VGS = 0 V 0.90 1.3 2009 1960 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea Forward Voltagea rDS(on) VSD V A Ω V b Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 25 V, f = 1 MHz 367 380 111 180 Total Gate Chargec Qg Gate-Source Chargec Qgs Gate-Drain Chargec Qgd Turn-On Delay Timec td(on) 23 10 tr VDD = 15 V, RL = 0.30 Ω ID ≅ 50 A, VGEN = 10 V, RG = 2.5 Ω 19 93 8 30 10 10 IF = 50,A di/dt = 100 A/µs 29 35 Rise Timec Turn-Off Delay Timec c td(off) Fall Time tf Reverse Recovery Time trr VDS = 15 V, VGS = 10 V, ID = 50 A 34 35 7.6 7.6 5.6 5.6 pF nC ns Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 71918 09-Jun-04 SPICE Device Model SUM50N03-13LC Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71918 09-Jun-04 www.vishay.com 3