AD AD5320BRTZ-REEL1 2.7 v to 5.5 v, 140 î¼a, rail-to-rail output 12-bit dac in an sot-23 Datasheet

2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output
12-Bit DAC in an SOT-23
AD5320
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single 12-bit DAC
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 140 μA @ 5 V
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Reference derived from power supply
Power-on reset to zero volts
Three power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
VDD
GND
AD5320
POWER-ON
RESET
DAC
REGISTER
12-BIT
DAC
OUTPUT
BUFFER
POWER-DOWN
CONTROL LOGIC
VOUT
REGISTER
NETWORK
00934-001
INPUT
CONTROL
LOGIC
REF (+) REF (–)
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
SYNC
SCLK DIN
Figure 1.
GENERAL DESCRIPTION
The AD5320 1 is a single, 12-bit buffered voltage out digital-toanalog converter (DAC) that operates from a single 2.7 V to
5.5 V supply consuming 115 μA at 3 V. Its on-chip precision
output amplifier allows rail-to-rail output swing to be achieved.
The AD5320 utilizes a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™ and digital signal
processing (DSP) interface standards.
The reference for AD5320 is derived from the power supply
inputs and thus gives the widest dynamic output range. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to zero volts and remains there until a
valid write takes place to the device. The part contains a powerdown feature that reduces the current consumption of the
device to 200 nA at 5 V and provides software selectable output
loads while in power-down mode. The part is put into powerdown mode over the serial interface.
The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.
The power consumption is 0.7 mW at 5 V reducing to 1 μW in
power-down mode.
1
The AD5320 is one of a family of pin-compatible DACs. The
AD5300 is the 8-bit version and the AD5310 is the 10-bit
version. The AD5300/AD5310/AD5320 are available in 6-lead
SOT-23 packages and 8-lead MSOP packages.
PRODUCT HIGHLIGHTS
1.
Available in 6-lead SOT-23 and 8-lead MSOP packages.
2.
Low power, single-supply operation. This part operates
from a single 2.7 V to 5.5 V supply and typically consumes
0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for
battery-powered applications.
3.
The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a slew rate of 1 V/μs.
4.
Reference derived from the power supply.
5.
High speed serial interface with clock speeds up to
30 MHz. Designed for very low power consumption. The
interface only powers up during a write cycle.
6.
Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.
Patent pending; protected by U.S. Patent No. 5684481.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD5320
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ................................................................................ 12
Applications....................................................................................... 1
Input Shift Register .................................................................... 12
Functional Block Diagram .............................................................. 1
SYNC Interrupt .......................................................................... 12
General Description ......................................................................... 1
Power-On Reset.......................................................................... 12
Product Highlights ........................................................................... 1
Power-Down Modes .................................................................. 13
Revision History ............................................................................... 2
Microprocessor Interfacing........................................................... 14
Specifications..................................................................................... 3
AD5320 to ADSP-2101/ADSP-2103 Interface ....................... 14
Timing Characteristics ................................................................ 4
AD5320 to 68HC11/68L11 Interface....................................... 14
Absolute Maximum Ratings............................................................ 5
AD5320 to 80C51/80L51 Interface .......................................... 14
ESD Caution.................................................................................. 5
AD5320 to MICROWIRE Interface......................................... 14
Pin Configurations and Function Descriptions ........................... 6
Applications..................................................................................... 15
Terminology ...................................................................................... 7
Using REF19x as a Power Supply for AD5320 ....................... 15
Typical Performance Characteristics ............................................. 8
Bipolar Operation Using the AD5320 ..................................... 15
Theory of Operation ...................................................................... 11
Using AD5320 with an Opto-Isolated Interface .................... 15
D/A Section................................................................................. 11
Power Supply Bypassing and Grounding................................ 16
Resistor String ............................................................................. 11
Outline Dimensions ....................................................................... 17
Output Amplifier........................................................................ 11
Ordering Guide .......................................................................... 17
REVISION HISTORY
11/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Table 4............................................................................ 6
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
Rev. C | Page 2 of 20
AD5320
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE 2
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS 3
Output Voltage Range
Output Voltage Settling Time
Min
5
−0.15
0
8
3
VDD
10
12
1
470
1000
20
0.5
1
50
20
2.5
5
Power-Up Time
2
±16
±1
40
−1.25
±1.25
−20
−5
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
1
Unit
12
Slew Rate
Capacitive Load Stability
LOGIC INPUTS3
Input Current
VINL, Input Low Voltage
VINL, Input Low Voltage
VINH, Input High Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
B Version 1
Typ
Max
Bits
LSB
LSB
mV
% of FSR
% of FSR
μV/°C
ppm of FSR/°C
V
μs
μs
V/μs
pF
pF
nV-s
nV-s
Ω
mA
mA
μs
μs
±1
0.8
0.6
Test Conditions/Comments
See Figure 5
Guaranteed monotonic by design (see Figure 6)
All zeroes loaded to DAC register (see Figure 9)
All ones loaded to DAC register (see Figure 9)
1/4 scale to 3/4 scale change (400 hex to C00 hex)
RL = 2 kΩ, 0 pF < CL < 200 pF (see Figure 19)
RL = 2 kΩ, CL = 500 pF
RL = ∞
RL = 2 kΩ
1 LSB change around major carry (see Figure 22)
VDD = 5 V
VDD = 3 V
Coming out of power-down mode, VDD = 5 V
Coming out of power-down mode, VDD = 3 V
3
μA
V
V
V
V
pF
5.5
V
140
115
250
200
μA
μA
DAC active and excluding load current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
0.2
0.05
1
1
μA
μA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
%
ILOAD = 2 mA, VDD = 5 V
2.4
2.1
2.7
93
Temperature range is as follows: B Version: −40°C to +105°C.
Linearity calculated using a reduced code range of 48 to 4047; output unloaded.
Guaranteed by design and characterization, not production tested.
Rev. C | Page 3 of 20
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
AD5320
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1, 2
t1 3
t2
t3
t4
t5
t6
t7
t8
2
3
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK rising edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 2.
Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
t1
SCLK
t8
t4
t3
t2
t7
SYNC
t5
DIN
DB15
t6
DB0
00934-002
1
Limit at TMIN, TMAX
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
50
33
13
13
22.5
13
0
0
5
5
4.5
4.5
0
0
50
33
Figure 2. Serial Write Operation
Rev. C | Page 4 of 20
AD5320
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ Max)
SOT-23 Package
Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
MSOP Package
Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Ratings
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +105°C
−65°C to +150°C
150°C
(TJ Max − TA)/θJA
240°C/W
215°C
220°C
450 mW
(TJ Max − TA)/θJA
206°C/W
44°C/W
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 5 of 20
AD5320
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5320
SYNC
5
SCLK
TOP VIEW
VDD 3 (Not to Scale) 4 DIN
AD5320
8
GND
DIN
TOP VIEW
NC 3 (Not to Scale) 6 SCLK
5 SYNC
VOUT 4
NC 2
00934-003
GND 2
6
7
NC = NO CONNECT
00934-004
VDD 1
VOUT 1
Figure 4. MSOP Pin Configuration
Figure 3. SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
SOT-23
Pin No.
MSOP
Pin No.
Mnemonic
Description
1
2
3
4
8
1
VOUT
GND
VDD
4
7
DIN
5
6
SCLK
6
5
SYNC
2, 3
NC
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and VDD should be decoupled
to GND.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges
of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high
before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the DAC.
No Connect.
Rev. C | Page 6 of 20
AD5320
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 5.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 6.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (000 hex) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5320 because the output of the DAC cannot go below 0 V
due to a combination of the offset errors in the DAC and output
amplifier. Zero-code error is expressed in mV. A plot of zerocode error vs. temperature can be seen in Figure 9.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (FFF Hex) is loaded to the DAC register. Ideally the output
should be VDD − 1 LSB. Full-scale error is expressed in percent
of full-scale range. A plot of full-scale error vs. temperature can
be seen in Figure 9.
Total Unadjusted Error
Total unadjusted error (TUE) is a measure of the output error
considering all the various errors. A typical TUE vs. code plot
can be seen in Figure 7.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV
seconds and is measured when the digital input code is changed
by 1 LSB at the major carry transition (7FF Hex to 800 Hex); see
Figure 22.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It
is specified in nV seconds and measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Rev. C | Page 7 of 20
AD5320
TYPICAL PERFORMANCE CHARACTERISTICS
16
16
TA = 25°C
12
12
8
0
–4
INL @ 5V
MIN DNL
–4
MIN INL
–8
–12
–12
0
800
1600
2400
CODE
3200
MAX DNL
0
–8
–16
MAX INL
4
00934-008
ERROR (LSBs)
INL @ 3V
4
00934-005
INL ERROR (LSBs)
8
–16
–40
4000
Figure 5. Typical INL Plot
0
40
TEMPERATURE (°C)
80
120
Figure 8. INL Error and DNL Error vs. Temperature
30
1.0
DNL @ 3V
DNL @ 5V
TA = 25°C
VDD = 5V
20
ERROR (mV)
DNL ERROR (LSBs)
0.5
0
10
ZS ERROR
0
FS ERROR
10
–0.5
0
1000
2000
CODE
3000
00934-009
–1.0
00934-006
20
30
–40
4000
Figure 6. Typical DNL Plot
0
40
TEMPERATURE (°C)
120
Figure 9. Zero-Scale Error and Full-Scale Error vs. Temperature
16
2500
TA = 25°C
VDD = 5V
2000
TUE @ 3V
VDD = 3V
FREQUENCY
8
0
TUE @ 5V
1500
1000
–8
–16
0
800
1600
2400
3200
0
50
4000
CODE
Figure 7. Typical Total Unadjusted Error Plot
00934-010
500
00934-007
TUE (LSBs)
80
60
70
80
90 100 110 120 130 140 150 160 170 180 190
IDD (µA)
Figure 10. IDD Histogram with VDD = 3 V and VDD = 5 V
Rev. C | Page 8 of 20
AD5320
3
300
TA = 25°C
VDD = 5V
200
DAC LOADED WITH FFF HEX
IDD (µA)
VOUT (V)
2
150
1
DAC LOADED WITH 000 HEX
0
5
0
–40
15
10
00934-014
00934-011
0
50
0
ISOURCE/SINK (mA)
40
TEMPERATURE °C
80
120
Figure 14. Supply Current vs. Temperature
Figure 11. Source and Sink Current Capability with VDD = 3 V
300
5
DAC LOADED WITH FFF HEX
TA = 25°C
250
4
IDD (µA)
VOUT (V)
200
3
T A = 25°C
150
2
100
1
0
00934-012
0
5
10
0
2.7
15
00934-015
50
DAC LOADED WITH 000 HEX
3.2
3.7
ISOURCE/SINK (mA)
3.7
VDD (V)
4.2
4.7
5
Figure 15. Supply Current vs. Supply Voltage
Figure 12. Source and Sink Current Capability with VDD = 5 V
1.0
500
0.9
400
THREE-STATE
CONDITION
0.8
IDD (µA)
0.6
200
VDD = 5V
0.4
+105°C
0
800
0.2
1600
2400
3200
+25°C
–40°C
00934-016
VDD = 3V
0
0.5
0.3
100
00934-013
IDD (µA)
0.7
300
0.1
4000
CODE
0
2.7
Figure 13. Supply Current vs. Code
3.2
3.7
4.2
VDD (V)
4.7
Figure 16. Power-Down Current vs. Supply Voltage
Rev. C | Page 9 of 20
5.2
AD5320
800
2kΩ LOAD TO VDD
TA = 25°C
VDD
400
CH1
200
VDD = 5V
0
1
2
3
VLOGIC (V)
00934-020
VDD = 3V
0
VOUT
CH2
00934-017
IDD (µA)
600
4
5
CH1 1V, CH 2 1V, TIME BASE = 20µs/DIV
Figure 20. Power-On Reset to 0 V
Figure 17. Supply Current vs. Logic Input Voltage
VDD = 5V
CH2
CH2
CLK
CLK
VOUT
00934-021
VOUT
00934-018
VDD = 5V
FULL-SCALE CODE CHANGE
000 HEX – FFF HEX
TA = 25°C
OUTPUT LOADED WITH
2kΩ AND 200pF TO GND
CH1
CH1
CH1 1V, CH2 5V, TIME BASE = 5µs/DIV
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
Figure 21. Exiting Power-Down (800 Hex Loaded)
Figure 18. Full-Scale Settling Time
2.56
LOADED WITH 2kΩ
AND 200pF TO GND
CH1
CLK
VOUT (V)
2.54
VOUT
2.52
2.50
2.48
00934-022
VDD = 5V
HALF-SCALE CODE CHANGE
400 HEX – C00 HEX
TA = 25°C
OUTPUT LOADED WITH
2kΩ AND 200pF TO GND
00934-019
CH2
CODE CHANGE:
800 HEX TO 7FF HEX
2.46
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
500ns/DIV
Figure 19. Half-Scale Settling Time
Figure 22. Digital-to-Analog Glitch Impulse
Rev. C | Page 10 of 20
AD5320
THEORY OF OPERATION
D/A SECTION
RESISTOR STRING
The AD5320 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Because there is no reference input pin, the
power supply (VDD) acts as the reference. Figure 23 shows a
block diagram of the DAC architecture.
The resistor string section is shown in Figure 24. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
VDD
REF (+)
RESISTOR
STRING
REF (–)
R
VOUT
R
OUTPUT
AMPLIFIER
TO OUTPUT
AMPLIFIER
R
00934-023
DAC REGISTER
GND
Figure 23. DAC Architecture
00934-024
R
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
R
Figure 24. Resistor String
D ⎞
VOUT = VDD × ⎛⎜
⎟
⎝ 4096 ⎠
OUTPUT AMPLIFIER
where D = decimal equivalent of the binary code that is loaded
to the DAC register; it can range from 0 to 4095.
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output that gives an output range of 0 V to VDD. It
is capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 11 and Figure 12. The slew rate is 1 V/μs
with a half-scale settling time of 8 μs with the output unloaded.
Rev. C | Page 11 of 20
AD5320
SERIAL INTERFACE
SYNC INTERRUPT
The AD5320 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI®, QSPITM, and
MICROWIRETM interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
In a normal write sequence, the SYNC line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if SYNC is brought high before the
16th falling edge, then this acts as an interrupt to the write
sequence. The shift register is reset and the write sequence is
seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see Figure 26).
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5320 compatible with high speed
DSPs. On the 16th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in DAC register contents and/or a change in the mode of
operation). At this stage, the SYNC line can be kept low or be
brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 2.4 V
than it does when VIN = 0.8 V, SYNC should be idled low
between write sequences for even lower power operation of the
part. As previously mentioned, SYNC must be brought high
again just before the next write sequence.
POWER-ON RESET
The AD5320 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
zeros and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the
DAC while it is in the process of powering up.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 25). The first two
bits are “don’t cares.” The next two are control bits that control
which mode of operation the part is in (normal mode or any one of
three power-down modes). There is a more complete description of
the various modes in the Power-Down Modes section. The next
twelve bits are the data bits. These are transferred to the DAC
register on the 16th falling edge of SCLK.
DB15 (MSB)
X
X
DB0 (LSB)
PD1 PD0 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
0
1
0
1
NORMAL OPERATION
1kΩ TO GND
100kΩ TO GND
POWER-DOWN MODES
THREE–STATE
00934-025
0
0
1
1
Figure 25. Input Register Contents
SCLK
SYNC
DB15
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16TH FALLING EDGE
DB15
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16TH FALLING EDGE
Figure 26. SYNC Interrupt Facility
Rev. C | Page 12 of 20
00934-028
DIN
AD5320
POWER-DOWN MODES
The AD5320 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB13
and DB12) in the control register. Table 5 shows how the state
of the bits corresponds to the mode of operation of the device.
RESISTOR
STRING DAC
0
1
1
1
0
1
RESISTOR
NETWORK
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
00934-026
DB12
0
VOUT
POWER-DOWN
CIRCUITRY
Table 5. Modes of Operation for the AD5320
DB13
0
AMPLIFIER
Figure 27. Output Stage During Power-Down
When both bits are set to 0, the part works with its normal power
consumption of 140 μA at 5 V. However, for the three power-down
modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not
only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output
impedance of the part is known while the part is in power-down
mode. There are three different options: the output is connected
internally to GND through a 1 kΩ resistor, the output is connected
internally to GND through a 100 kΩ resistor, or it is left opencircuited (three-state). The output stage is illustrated in Figure 27.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit powerdown is typically 2.5 μs for VDD = 5 V and 5 μs for VDD = 3 V
(see Figure 21).
Rev. C | Page 13 of 20
AD5320
MICROPROCESSOR INTERFACING
AD5320 TO ADSP-2101/ADSP-2103 INTERFACE
AD5320 TO 80C51/80L51 INTERFACE
Figure 28 shows a serial interface between the AD5320 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the serial port (SPORT) transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT are
programmed through the SPORT control register and should
be configured as follows: internal clock operation, active low
framing, and 16-bit word length. Transmission is initiated by
writing a word to the Tx register after the SPORT has been
enabled.
Figure 30 shows a serial interface between the AD5320 and the
80C51/80L51 microcontrollers. TXD of the 80C51/80L51 drives
SCLK of the AD5320, while RXD drives the serial data line of
the part. The SYNC signal is again derived from a bit
programmable pin on the port. In this case, port line P3.3 is
used. When data is to be transmitted to the AD5320, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus only eight falling clock edges occur in the transmit cycle.
To load data to the DAC, P3.3 is left low after the first eight bits
are transmitted, and a second write cycle is initiated to transmit
the second byte of data. P3.3 is taken high following the
completion of this cycle. The 80C51/ 80L51 output the serial
data in a format that has the LSB first. The AD5320 requires its
data with the MSB as the first bit received. The 80C51/80L51
transmit routine should consider this.
AD5320*
ADSP-2101/
ADSP-2103*
DT
SCLK
SYNC
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
00934-027
TFS
AD5320*
80C51/80L51*
AD5320 TO 68HC11/68L11 INTERFACE
P3.3
SYNC
Figure 29 shows a serial interface between the AD5320 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5320, while the MOSI output drives
the serial data line of the DAC. The SYNC signal is derived
from a port line (PC7). For correct operation of this interface,
the 68HC11/68L11 should be configured so that the CPOL bit
is a 0 and the CPHA bit is a 1. When data is being transmitted
to the DAC, the SYNC line is taken low (PC7). When the
68HC11/68L11 are configured, data appearing on the MOSI
output is valid on the falling edge of SCK as shown in Figure 29.
TXD
SCLK
RXD
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 30. AD5320 to 80C51/80L51 Interface
AD5320 TO MICROWIRE INTERFACE
Figure 31 shows an interface between the AD5320 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5320 on the rising edge of the SK.
AD5320*
MICROWIRE*
CS
SYNC
SK
SCLK
SO
DIN
AD5320*
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 31. AD5320 to MICROWIRE Interface
PC7
SYNC
SCK
SCLK
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
00934-029
MOSI
Figure 29. AD5320 to 68HC11/68L11 Interface
Rev. C | Page 14 of 20
00934-031
Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes
with only eight falling clock edges occurring in the transmit
cycle. Data is transmitted MSB first. In order to load data to the
AD5320, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC
and PC7 is taken high at the end of this procedure.
00934-030
Figure 28. AD5320 to ADSP-2101/ADSP-2103 Interface
AD5320
APPLICATIONS
R2 = 10kΩ
USING REF19X AS A POWER SUPPLY FOR AD5320
140 μA + (5 V/5 kΩ) = 1.14 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 2.3 ppm (11.5 μV) for the 1.14 mA
current drawn from it. This corresponds to a 0.009 LSB error.
15V
REF195
5V
140µA
VOUT = 0V TO 5V
SYNC
SCLK
AD5320
DIN
00934-032
3-WIRE
SERIAL
INTERFACE
+5V
+5V
R1 = 10kΩ
AD820/
OP295
VDD
10µF
0.1µF
±5V
–5V
VOUT
AD5320
00934-033
Because the supply current required by the AD5320 is
extremely low, an alternative option is to use a REF19x voltage
reference (REF195 for 5 V or REF193 for 3 V) to supply the
required voltage to the part (see Figure 32). This is especially
useful if the power supply is noisy or if the system supply
voltages are at some value other than 5 V or 3 V (such as 15 V).
The REF19x outputs a steady supply voltage for the AD5320. If
the low dropout REF195 is used, the current it needs to supply
to the AD5320 is 140 μA. This is with no load on the output of
the DAC. When the DAC output is loaded, the REF195 also
needs to supply the current to the load. The total current
required (with a 5 kΩ load on the DAC output) is:
3-WIRE SERIAL INTERFACE
Figure 33. Bipolar Operation with the AD5320
USING AD5320 WITH AN OPTO-ISOLATED
INTERFACE
For process control applications in industrial environments, it is
often necessary to use an opto-isolated interface to protect and
isolate the controlling circuitry from any hazardous commonmode voltages that can occur in the area where the DAC is
functioning. Opto-isolators provide isolation in excess of 3 kV.
Because the AD5320 uses a 3-wire serial logic interface, it
requires only three opto-isolators to provide the required
isolation (see Figure 34). The power supply to the part also
needs to be isolated. This is done by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5320.
5V
REGULATOR
Figure 32. REF195 as Power Supply to AD5320
10µF
POWER
0.1µF
BIPOLAR OPERATION USING THE AD5320
VDD
The AD5320 is designed for single-supply operation but a bipolar
output range is also possible using the circuit in Figure 33. The
circuit below gives an output voltage range of ±5 V. Rail-to-rail
operation at the amplifier output is achievable using an AD820 or
an OP295 as the output amplifier.
SCLK
The output voltage for any input code can be calculated as
follows:
SYNC
10kΩ
SCLK
VDD
AD5320
VDD
10kΩ
VOUT
SYNC
VDD
⎡
D ⎞ ⎛ R1 + R2 ⎞
⎛ R2 ⎞ ⎤
VO = ⎢VDD × ⎛⎜
⎟ − VDD × ⎜
⎟⎥
⎟×⎜
R
4096
1
⎝ R1 ⎠ ⎦
⎝
⎠
⎝
⎠
⎣
10kΩ
DIN
GND
where D represents the input code in decimal (0 to 4095).
With VDD = 5 V, R1 = R2 = 10 kΩ:
Figure 34. AD5320 with An Opto-Isolated Interface
⎛ 10 × D ⎞
VO = ⎜
⎟ − 5V
⎝ 4096 ⎠
This is an output voltage range of ±5 V with 000 hex
corresponding to a −5 V output and FFF hex corresponding to
a +5 V output.
Rev. C | Page 15 of 20
00934-034
DATA
AD5320
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to consider
carefully the power supply and ground return layout on the
board. The printed circuit board containing the AD5320 should
have separate analog and digital sections, each having its own
area of the board. If the AD5320 is in a system where other
devices require an AGND to DGND connection, the connection should be made at one point only. This ground point
should be as close as possible to the AD5320.
The power supply to the AD5320 should be bypassed with 10 μF
capacitors and 0.1 μF capacitors. The capacitors should be physically as close as possible to the device with the 0.1 μF capacitors
ideally against the device. The 10 μF capacitors are the tantalum
bead type. It is important that the 0.1 μF capacitors have low
effective series resistance (ESR) and effective series inductance
(ESI), such as common ceramic types of capacitors. The 0.1 μF
capacitors provide a low impedance path to ground for high
frequencies caused by transient currents due to internal logic
switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.
Rev. C | Page 16 of 20
AD5320
OUTLINE DIMENSIONS
2.90 BSC
3.20
3.00
2.80
6
5
4
1
2
3
2.80 BSC
1.60 BSC
PIN 1
INDICATOR
0.95 BSC
0.15 MAX
4
0.65 BSC
1.45 MAX
0.50
0.30
1
5.15
4.90
4.65
5
PIN 1
1.90
BSC
1.30
1.15
0.90
8
3.20
3.00
2.80
0.95
0.85
0.75
0.22
0.08
SEATING
PLANE
10°
4°
0°
1.10 MAX
0.15
0.00
0.60
0.45
0.30
0.38
0.22
COPLANARITY
0.10
0.23
0.08
0.80
0.60
0.40
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178-AB
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 35. 6-Lead Small Outline Transistor Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
Figure 36. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5320BRM
AD5320BRM-REEL
AD5320BRM-REEL7
AD5320BRMZ 1
AD5320BRMZ-REEL1
AD5320BRMZ-REEL71
AD5320BRT-500RL7
AD5320BRT-REEL
AD5320BRT-REEL7
AD5320BRTZ-500RL71
AD5320BRTZ-REEL1
AD5320BRTZ-REEL71
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
Z = Pb-free part.
Rev. C | Page 17 of 20
Branding
D4B
D4B
D4B
D9N
D9N
D9N
D4B
D4B
D4B
D9N
D9N
D9N
Package Option
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RT-6
RT-6
RT-6
RT-6
RT-6
RT-6
AD5320
NOTES
Rev. C | Page 18 of 20
AD5320
NOTES
Rev. C | Page 19 of 20
AD5320
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00934-0-11/05(C)
Rev. C | Page 20 of 20
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