AD AD5312 2.5 v to 5.5 v, 115 ua, parallel interface single voltage-output 8-/10-/12-bit dac Datasheet

a
2.5 V to 5.5 V, 115 ␮A, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330/AD5331/AD5340/AD5341*
FEATURES
AD5330: Single 8-Bit DAC in 20-Lead TSSOP
AD5331: Single 10-Bit DAC in 20-Lead TSSOP
AD5340: Single 12-Bit DAC in 24-Lead TSSOP
AD5341: Single 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 115 ␮A @ 3 V, 140 ␮A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40ⴗC to +105ⴗC
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both
supply rails, while the AD5330, AD5340, and AD5341 allow a
choice of buffered or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin allows the output range to be set at 0 V to VREF
or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5330 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
VREF
POWER-ON
RESET
VDD
AD5330
BUF
INPUT
REGISTER
GAIN
DB
.. 7
DB0
DAC
REGISTER
INTERFACE
LOGIC
8-BIT
DAC
VOUT
BUFFER
CS
WR
RESET
CLR
POWER-DOWN
LOGIC
LDAC
PD
GND
*Protected by U.S. Patent Number 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD5330/AD5331/AD5340/AD5341–SPECIFICATIONS
(VDD = 2.5 V to 5.5 V, VREF = 2 V. RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
Parameter1
Min
B Version2
Typ
Max
Unit
Conditions/Comments
3, 4
DC PERFORMANCE
AD5330
Resolution
Relative Accuracy
Differential Nonlinearity
AD5331
Resolution
Relative Accuracy
Differential Nonlinearity
AD5340/AD5341
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband5
Upper Deadband
Offset Error Drift6
Gain Error Drift6
DC Power Supply Rejection Ratio6
8
± 0.15
± 0.02
±1
± 0.25
Bits
LSB
LSB
Guaranteed Monotonic By Design Over All Codes
10
± 0.5
± 0.05
±4
± 0.5
Bits
LSB
LSB
Guaranteed Monotonic By Design Over All Codes
12
±2
± 0.2
± 0.4
± 0.15
10
10
–12
–5
–60
± 16
±1
±3
±1
60
60
Bits
LSB
LSB
% of FSR
% of FSR
mV
mV
ppm of FSR/°C
ppm of FSR/°C
dB
Guaranteed Monotonic By Design Over All Codes
Lower Deadband Exists Only if Offset Error Is Negative
VDD = 5 V. Upper Deadband Exists Only if VREF = VDD
∆VDD = ± 10%
6
DAC REFERENCE INPUT
VREF Input Range
1
0.25
VREF Input Impedance
Reference Feedthrough
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7
Maximum Output Voltage4, 7
DC Output Impedance
Short Circuit Current
Power-Up Time
LOGIC INPUTS6
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
>10
180
90
–90
V
V
MΩ
kΩ
kΩ
dB
Buffered Reference (AD5330, AD5340, and AD5341)
Unbuffered Reference
Buffered Reference (AD5330, AD5340, and AD5341)
Unbuffered Reference. Gain = 1, Input Impedance = RDAC
Unbuffered Reference. Gain = 2, Input Impedance = RDAC
Frequency = 10 kHz
0.001
VDD–0.001
0.5
25
15
2.5
5
V min
V max
Ω
mA
mA
µs
µs
Rail-to-Rail Operation
±1
µA
V
V
V
V
V
V
pF
0.8
0.6
0.5
2.4
2.1
2.0
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
VDD
VDD
3
2.5
5.5
V
140
115
250
200
µA
µA
0.2
0.08
1
1
µA
µA
VDD = 5 V
VDD = 3 V
Coming Out of Power-Down Mode. VDD = 5 V
Coming Out of Power-Down Mode. VDD = 3 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
DACs active and excluding load currents. Unbuffered
Reference. VIH = VDD, VIL = GND.
IDD increases by 50 µA at VREF > VDD – 100 mV.
In Buffered Mode extra current is (5 + VREF/RDAC) µA,
where RDAC is the resistance of the resistor string.
NOTES
1
See Terminology section.
2
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
3
Linearity is tested using a reduced code range: AD5330 (Code 8 to 255); AD5331 (Code 28 to 1023); AD5340/AD5341 (Code 115 to 4095).
4
DC specifications tested with output unloaded.
5
This corresponds to x codes. x = Deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V REF = VDD and
“Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
–2–
REV. 0
AD5330/AD5331/AD5340/AD5341
(VDD = 2.5 V to 5.5 V. RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX
AC CHARACTERISTICS1 unless otherwise noted.)
2
Parameter
B Version3
Min
Typ
Max
Unit
6
7
8
8
0.7
6
0.5
200
–70
µs
µs
µs
µs
V/µs
nV-s
nV-s
kHz
dB
Output Voltage Settling Time
AD5330
AD5331
AD5340
AD5341
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Multiplying Bandwidth
Total Harmonic Distortion
8
9
10
10
Conditions/Comments
VREF = 2 V. See Figure 20
1/4 Scale to 3/4 Scale Change (40 H to C0 H)
1/4 Scale to 3/4 Scale Change (100 H to 300 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1 LSB Change Around Major Carry
VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3 (V
DD
= 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Condition/Comments
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
WR Pulsewidth
Data, GAIN, BUF, HBEN Setup Time
Data, GAIN, BUF, HBEN Hold Time
Synchronous Mode. WR Falling to LDAC Falling.
Synchronous Mode. LDAC Falling to WR Rising.
Synchronous Mode. WR Rising to LDAC Rising.
Asynchronous Mode. LDAC Rising to WR Rising.
Asynchronous Mode. WR Rising to LDAC Falling.
LDAC Pulsewidth
CLR Pulsewidth
Time Between WR Cycles
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2.
3
See Figure 1.
t2
t1
CS
t 13
t3
WR
t4
DATA,
GAIN,
BUF,
HBEN
t6
t7
t5
t8
1
LDAC
t 10
t9
t 11
LDAC2
t 12
CLR
NOTES:
1 SYNCHRONOUS LDAC UPDATE MODE
2 ASYNCHRONOUS LDAC UPDATE MODE
Figure 1. Parallel Interface Timing Diagram
REV. 0
–3–
AD5330/AD5331/AD5340/AD5341
ABSOLUTE MAXIMUM RATINGS*
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (TJ max – TA)/θJA mW
θJA Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W
θJA Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
θJA Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W
θJC Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Option
AD5330BRU
AD5331BRU
AD5340BRU
AD5341BRU
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
RU-20
RU-20
RU-24
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5330/AD5331/AD5340/AD5341 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD5330/AD5331/AD5340/AD5341
AD5330 FUNCTIONAL BLOCK DIAGRAM
VREF
POWER-ON
RESET
AD5330 PIN CONFIGURATION
VDD
AD5330
BUF
INPUT
REGISTER
GAIN
DB
.. 7
DB0
DAC
REGISTER
INTERFACE
LOGIC
8-BIT
DAC
VOUT
BUFFER
WR
POWER-DOWN
LOGIC
CLR
20
DB7
NC 2
19
DB6
VREF 3
18
DB5
VOUT 4
17
DB4
16
DB3
GND 5
CS
RESET
BUF 1
8-BIT
AD5330
TOP VIEW 15 DB
2
(Not to Scale)
14 DB1
WR 7
CS 6
DB0
GAIN 8
13
CLR 9
12
VDD
LDAC 10
11
PD
NC = NO CONNECT
LDAC
PD
GND
AD5330 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
2
3
4
5
6
7
8
9
10
11
12
BUF
NC
VREF
VOUT
GND
CS
WR
GAIN
CLR
LDAC
PD
VDD
13–20
DB0–DB7
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
No Connect.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
REV. 0
–5–
AD5330/AD5331/AD5340/AD5341
AD5331 FUNCTIONAL BLOCK DIAGRAM
VREF
POWER-ON
RESET
AD5331 PIN CONFIGURATION
VDD
AD5331
BUF
DB9
..
DB0
INPUT
REGISTER
DAC
REGISTER
INTERFACE
LOGIC
DB8 1
20
DB7
DB9
2
19
DB6
VREF
3
18
DB5
VOUT 4
17
DB4
16
DB3
GND 5
10-BIT
DAC
VOUT
BUFFER
CLR
WR
LDAC
RESET
CLR
AD5331
TOP VIEW 15 DB
2
(Not to Scale)
14 DB1
WR 7
CS 6
GAIN 8
CS
10-BIT
13
DB0
9
12
VDD
10
11
PD
POWER-DOWN
LOGIC
LDAC
PD
GND
AD5331 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
2
3
4
5
6
7
8
9
10
11
12
DB8
DB9
VREF
VOUT
GND
CS
WR
GAIN
CLR
LDAC
PD
VDD
13–20
DB0–DB7
Parallel Data Input.
Most Significant Bit of Parallel Data Input.
Unbuffered Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
Active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs.
–6–
REV. 0
AD5330/AD5331/AD5340/AD5341
AD5340 PIN CONFIGURATION
AD5340 FUNCTIONAL BLOCK DIAGRAM
VREF
POWER-ON
RESET
VDD
AD5340
24
DB9
23
DB8
BUF 3
22
DB7
VREF 4
21
DB6
20
DB5
VOUT 5
BUF
INPUT
REGISTER
GAIN
DB.11
.
DB0
DB10 1
DB11 2
DAC
REGISTER
INTERFACE
LOGIC
12-BIT
DAC
VOUT
BUFFER
WR
RESET
AD5340
TOP VIEW 19 DB4
GND 7 (Not to Scale) 18 DB3
NC 6
CS
CLR
12-BIT
POWER-DOWN
LOGIC
LDAC
CS 8
17
DB2
WR 9
16
DB1
GAIN 10
15
DB0
CLR 11
14
VDD
LDAC 12
13
PD
NC = NO CONNECT
PD
GND
AD5340 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DB10
DB11
BUF
VREF
VOUT
NC
GND
CS
WR
GAIN
CLR
LDAC
PD
VDD
15–24
DB0–DB9
Parallel Data Input.
Most Significant Bit of Parallel Data Input.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
No Connect.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
10 Parallel Data Inputs.
REV. 0
–7–
AD5330/AD5331/AD5340/AD5341
AD5341 PIN CONFIGURATION
AD5341 FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
BUF
POWER-ON
RESET
GAIN
DB
.. 7
DB0
HBEN
CS
HIGH BYTE
REGISTER
INTERFACE
LOGIC
AD5341
19 DB6
VREF 3
18 DB5
GND 5
12-BIT
DAC
BUFFER
VOUT
WR
RESET
CLR
20 DB7
BUF 2
VOUT 4
DAC
REGISTER
LOW BYTE
REGISTER
HBEN 1
POWER-DOWN
LOGIC
LDAC
PD
17 DB4
12-BIT
AD5341
16 DB3
TOP VIEW 15 DB
2
(Not to Scale)
14 DB1
WR 7
CS 6
GAIN 8
13 DB0
CLR 9
12 VDD
LDAC 10
11 PD
GND
AD5341 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
HBEN
2
3
4
5
6
7
8
9
10
11
12
BUF
VREF
VOUT
GND
CS
WR
GAIN
CLR
LDAC
PD
VDD
13–20
DB0–DB7
High Byte Enable Pin. This pin is used when writing to the device to determine if data is written
to the high byte register or the low byte register.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
–8–
REV. 0
AD5330/AD5331/AD5340/AD5341
TERMINOLOGY
RELATIVE ACCURACY
GAIN ERROR
AND
OFFSET ERROR
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus Code plot can be seen in Figures
5, 6, and 7.
OUTPUT
VOLTAGE
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus Code plot can be seen in
Figures 8, 9, and 10.
ACTUAL
IDEAL
POSITIVE
OFFSET
DAC CODE
GAIN ERROR
This is a measure of the span error of the DAC (including any
error in the gain of the buffer amplifier). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
expressed as a percentage of the full-scale range. This is illustrated in Figure 2.
Figure 3. Positive Offset Error and Gain Error
GAIN ERROR
AND
OFFSET ERROR
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
OUTPUT
VOLTAGE
If the offset voltage is positive, the output voltage will still be
positive at zero input code. This is shown in Figure 3. Because
the DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer amplifier. Instead, there will
be a code close to zero at which the amplifier output saturates
(amplifier footroom). Below this code there will be a deadband
over which the output voltage will not change. This is illustrated
in Figure 4.
ACTUAL
IDEAL
NEGATIVE
OFFSET
POSITIVE
GAIN ERROR
DEADBAND CODES
AMPLIFIER
FOOTROOM
(~1mV)
NEGATIVE
GAIN
ERROR
OUTPUT
VOLTAGE
DAC CODE
ACTUAL
NEGATIVE
OFFSET
IDEAL
Figure 4. Negative Offset Error and Gain Error
DAC CODE
Figure 2. Gain Error
REV. 0
–9–
AD5330/AD5331/AD5340/AD5341
OFFSET ERROR DRIFT
DIGITAL FEEDTHROUGH
This is a measure of the change in Offset Error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
This is a measure of the change in Gain Error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(CS held high). It is specified in nV secs and is measured with a
full-scale change on the digital input pins, i.e., from all 0s to all
1s and vice versa.
POWER-SUPPLY REJECTION RATIO (PSRR)
MULTIPLYING BANDWIDTH
This indicates how the output of the DAC is affected by changes in
the supply voltage. PSRR is the ratio of the change in VOUT to a
change in VDD for full-scale output of the DAC. It is measured
in dBs. VREF is held at 2 V and VDD is varied ± 10%.
The amplifiers within the DAC have a finite bandwidth. The
Multiplying Bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The Multiplying Bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
GAIN ERROR DRIFT
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC output
to the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.
Major-Code Transition Glitch Energy is the energy of the
impulse injected into the analog output when the DAC changes
state. It is normally specified as the area of the glitch in nV secs
and is measured when the digital code is changed by 1 LSB at
the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00
to 011 . . . 11).
–10–
REV. 0
Typical Performance Characteristics– AD5330/AD5331/AD5340/AD5341
TA = 25ⴗC
VDD = 5V
TA = 25ⴗC
VDD = 5V
INL ERROR – LSBs
0
TA = 25ⴗC
VDD = 5V
8
INL ERROR – LSBs
2
0.5
INL ERROR – LSBs
12
3
1.0
1
0
–1
4
0
–4
–0.5
–8
–2
50
0
100
150
CODE
200
–3
250
Figure 5. AD5330 Typical INL Plot
200
400
600
CODE
800
1000
Figure 6. AD5331 Typical INL Plot
0.3
DNL ERROR – LSBs
0
–0.1
1000
2000
CODE
3000
4000
1.0
TA = 25ⴗC
VDD = 5V
0.4
0.1
0
Figure 7. AD5340 Typical INL Plot
0.6
TA = 25ⴗC
VDD = 5V
0.2
DNL ERROR – LSBs
–12
0
TA = 25ⴗC
VDD = 5V
0.5
DNL ERROR – LSBs
–1.0
0.2
0
–0.2
0
–0.5
–0.4
–0.2
0
50
100
150
CODE
200
–0.6
250
Figure 8. AD5330 Typical DNL Plot
200
400
600
CODE
–1.0
1000
0.75
ERROR – LSBs
0.25
MAX INL
MAX DNL
0.00
MIN DNL
–0.25
MIN INL
–0.25
MIN INL
–0.75
2
3
4
VREF – V
Figure 11. AD5330 INL and DNL
Error vs. V REF
REV. 0
5
–1.00
–40
4000
MAX INL
0
–0.75
3000
0.5
MAX DNL
–0.50
2000
CODE
VDD = 5V
VREF = 2V
0.25
–0.50
1000
1.0
VDD = 5V
VREF = 3V
0.50
0.50
0
Figure 10. AD5340 Typical DNL Plot
1.00
VDD = 5V
TA = 25ⴗC
0.75
–1.00
800
Figure 9. AD5331 Typical DNL Plot
1.00
ERROR – LSBs
0
ERROR – %
–0.3
GAIN ERROR
0.0
MIN DNL
OFFSET ERROR
–0.5
0
40
80
TEMPERATURE – ⴗC
120
Figure 12. AD5330 INL Error and
DNL Error vs. Temperature
–11–
–1.0
–40
0
40
80
TEMPERATURE – ⴗC
120
Figure 13. AD5330 Offset Error
and Gain Error vs. Temperature
AD5330/AD5331/AD5340/AD5341
0.2
300
5
TA = 25ⴗC
TA = 25ⴰC
VREF = 2V
0.1
5V SOURCE
4
VOUT – Volts
3V SOURCE
–0.1
–0.2
–0.3
200
3
IDD – ␮A
ERROR – %
VDD = 5.5V
GAIN ERROR
0
2
150
VDD = 3.6V
100
–0.4
OFFSET ERROR
1
3V SINK
50
5V SINK
–0.5
–0.6
VREF = 2V
250
0
2
1
4
3
VDD – Volts
5
0
6
Figure 14. Offset Error and Gain
Error vs. V DD
0
1
3
4
2
5
SINK/SOURCE CURRENT – mA
6
FULL-SCALE
DAC CODE
Figure 15. V OUT Source and Sink
Current Capability
Figure 16. Supply Current vs. DAC
Code
1800
0.5
300
0
ZERO-SCALE
TA = 25ⴗC
TA = 25ⴗC
TA = 25ⴗC
1600
0.4
1400
1200
0.3
IDD – ␮A
IDD – ␮A
IDD – ␮A
200
VDD = 5V
1000
0.2
800
600
100
400
0.1
200
0
2.5
3.0
3.5
4.0
4.5
VDD – Volts
5.0
0
2.5
5.5
Figure 17. Supply Current vs. Supply
Voltage
3.5
4.0
4.5
VDD – Volts
5.0
CLK
CH1
0
0
5.5
Figure 18. Power-Down Current vs.
Supply Voltage
VDD = 5V
TA = 25ⴗC
CH2
3.0
VDD = 3V
1
2
3
VLOGIC – Volts
4
5
Figure 19. Supply Current vs. Logic
Input Voltage
TA = 25ⴰC
VDD = 5V
VREF = 2V
TA = 25ⴰC
VDD = 5V
VREF = 2V
VDD
CH1
VOUTA
VOUT
PD
VOUTA
CH2
CH2
CH1
CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV
CH1 500mV, CH2 5V, TIME BASE = 1␮s/DIV
Figure 21. Power-On Reset to 0 V
Figure 22. Exiting Power-Down to
Midscale
CH1 1V, CH2 5V, TIME BASE = 5␮s/DIV
Figure 20. Half-Scale Settling (1/4 to
3/4 Scale Code Change)
–12–
REV. 0
AD5330/AD5331/AD5340/AD5341
VDD = 5V
80 90 100 110 120 130 140 150 160 170 180 190 200
–10
–20
–30
–40
–50
–60
0.01
250ns/DIV
IDD – ␮A
Figure 23. IDD Histogram with V DD =
3 V and V DD = 5 V
0
dB
VDD = 3V
FREQUENCY
10
0.917
0.916
0.915
0.914
0.913
0.912
0.911
0.910
0.909
0.908
0.907
0.906
0.905
0.904
0.903
0.1
1
10
100
FREQUENCY – kHz
1k
10k
Figure 25. Multiplying Bandwidth
(Small-Signal Frequency Response)
Figure 24. AD5340 Major-Code Transition Glitch Energy
0.4
FULL-SCALE ERROR – %FSR
VDD = 5V
TA = 25ⴗC
0.2
0
–0.2
0
1
2
3
VREF – Volts
4
5
Figure 26. Full-Scale Error vs. V REF
FUNCTIONAL DESCRIPTION
where:
The AD5330/AD5331/AD5340/AD5341 are single resistor-string
DACs fabricated on a CMOS process with resolutions of 8, 10,
12, and 12 bits, respectively. They are written to using a parallel
interface. They operate from single supplies of 2.5 V to 5.5 V and
the output buffer amplifiers offer rail-to-rail output swing. The
AD5330, AD5340, and AD5341 have a reference input that may
be buffered to draw virtually no current from the reference
source. The reference input of the AD5331 is unbuffered. The
devices have a power-down feature that reduces current consumption to only 80 nA @ 3 V.
D = decimal equivalent of the binary code which is loaded to the
DAC register:
0–255 for AD5330 (8 Bits)
0–1023 for AD5331 (10 Bits)
0–4095 for AD5340/AD5341 (12 Bits)
N = DAC resolution
Gain = Output Amplifier Gain (1 or 2)
VREF
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 27 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
VOUT = VREF ×
REFERENCE
BUFFER
BUF
GAIN
INPUT
REGISTER
D
× Gain
2N
DAC
REGISTER
RESISTOR
STRING
VOUT
OUTPUT
BUFFER AMPLIFIER
Figure 27. Single DAC Channel Architecture
REV. 0
–13–
AD5330/AD5331/AD5340/AD5341
Resistor String
PARALLEL INTERFACE
The resistor string section is shown in Figure 28. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it
is guaranteed monotonic.
The AD5330, AD5331, and AD5340 load their data as a single
8-, 10-, or 12-bit word, while the AD5341 loads data as a low
byte of eight bits and a high byte containing four bits.
VREF
R
TO OUTPUT
AMPLIFIER
Double-buffering is also useful where the DAC data is loaded in
two bytes, as in the AD5341, because it allows the whole data
word to be assembled in parallel before updating the DAC register.
This prevents spurious outputs that could occur if the DAC
register were updated with only the high byte or the low byte.
R
R
Figure 28. Resistor String
DAC Reference Input
There is a reference input pin for the DAC. The reference input
is buffered on the AD5330/AD5340/AD5341 but can be configured as unbuffered also. The reference input of the AD5331 is
unbuffered. The buffered/unbuffered option is controlled by the
BUF pin.
In buffered mode (BUF = 1), the current drawn from an external
reference voltage is virtually zero as the impedance is at least
10 MΩ. The reference input range is 1 V to 5 V with a 5 V supply.
In unbuffered mode (BUF = 0), the user can have a reference
voltage as low as 0.25 V and as high as VDD since there is no
restriction due to headroom and footroom of the reference amplifier. The impedance is still large at typically 180 kΩ for 0–VREF
mode and 90 kΩ for 0–2 VREF mode. If there is an external
buffered reference (e.g., REF192) there is no need to use the
on-chip buffer.
Output Amplifier
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on VREF, GAIN, the load on VOUT, and offset error.
If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to VREF.
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 VREF. However, because of clamping, the maximum output
is limited to VDD – 0.001 V.
The output amplifier is capable of driving a load of 2 kΩ to
GND or VDD, in parallel with 500 pF to GND or VDD. The
source and sink capabilities of the output amplifier can be seen
in Figure 15.
The slew rate is 0.7 V/µs with a half-scale settling time to
± 0.5 LSB (at eight bits) of 6 µs with the output unloaded. See
Figure 20.
The AD5330/AD5331/AD5340/AD5341 DACs all have doublebuffered interfaces consisting of an input register and a DAC
register. DAC data, BUF, and GAIN inputs are written to the input
register under control of the Chip Select (CS) and Write (WR).
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input register
are transferred to it. The gain and buffer control signals are also
double-buffered and are only updated when LDAC is taken low.
R
R
Double-Buffered Interface
These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated
since the last time that LDAC was brought low. Normally,
when LDAC is brought low, the DAC register is filled with the
contents of the input register. In the case of the AD5330/AD5331/
AD5340/AD5341, the part will only update the DAC register if
the input register has been changed since the last time the DAC
register was updated. This removes unnecessary crosstalk.
Clear Input (CLR)
CLR is an active low, asynchronous clear that resets the input and
DAC registers.
Chip Select Input (CS)
CS is an active low input that selects the device.
Write Input (WR)
WR is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising edge
of WR.
Load DAC Input (LDAC)
LDAC transfers data from the input register to the DAC register
(and hence updates the outputs). Use of the LDAC function enables
double-buffering of the DAC data, GAIN, and BUF. There
are two LDAC modes:
Synchronous Mode: In this mode the DAC register is updated
after new data is read in on the rising edge of the WR input.
LDAC can be tied permanently low or pulsed as in Figure 1.
Asynchronous Mode: In this mode the outputs are not updated
at the same time that the input register is written to. When LDAC
goes low, the DAC register is updated with the contents of the
input register.
High-Byte Enable Input (HBEN)
High-Byte Enable is a control input on the AD5341 only that
determines if data is written to the high-byte input register or
the low-byte input register.
–14–
REV. 0
AD5330/AD5331/AD5340/AD5341
The low data byte of the AD5341 consists of data bits 0 to 7 at
data inputs DB0 to DB7, while the high byte consists of data
bits 8 to 11 at data inputs DB0 to DB3 as shown in Figure 29.
DB4 to DB7 are ignored during a high-byte write, but they may
be used for data to set up the reference input as buffered/
unbuffered, and buffer amplifier gain. See Figure 33.
reduced when the DAC is not in use by putting it into powerdown mode, which is selected by taking pin PD low.
When the PD pin is high, the DAC works normally with a
typical power consumption of 140 µA at 5 V (115 µA at 3 V).
In power-down mode, however, the supply current falls to
200 nA at 5 V (80 nA at 3 V) when the DAC is powered-down.
Not only does the supply current drop, but the output stage is
also internally switched from the output of the amplifier making it open-circuit. This has the advantage that the output is
three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to
the output of the DAC amplifier. The output stage is illustrated in Figure 30.
HIGH BYTE
X
X
X
X
DB11 DB10 DB9 DB8
LOW BYTE
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X = UNUSED BIT
Figure 29. Data Format for AD5341
POWER-ON RESET
The AD5330/AD5331/AD5340/AD5341 are provided with a
power-on reset function, so that they power up in a defined state.
The power-on state is:
•
•
•
•
RESISTOR
STRING DAC
AMPLIFIER
VOUT
POWER-DOWN
CIRCUITRY
Normal Operation
Reference Input Unbuffered
0 – VREF Output Range
Output Voltage Set to 0 V
Figure 30. Output Stage During Power-Down
Both input and DAC registers are filled with zeros and remain so
until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
POWER-DOWN MODE
The AD5330/AD5331/AD5340/AD5341 have low power consumption, dissipating only 0.35 mW with a 3 V supply and
0.7 mW with a 5 V supply. Power consumption can be further
The bias generator, the output amplifier, the resistor string,
and all other associated linear circuitry are shut down when
the power-down mode is activated. However, the contents
of the registers are unaffected when in power-down. The time
to exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs
when VDD = 3 V. This is the time from a rising edge on the
PD pin to when the output voltage deviates from its powerdown voltage. See Figure 22.
Table I. AD5330/AD5331/AD5340 Truth Table
CLR
LDAC
CS
WR
Function
1
1
0
1
1
1
1
1
X
1
0
0
1
X
X
0
0
X
X
1
X
0➝1
0➝1
X
No Data Transfer
No Data Transfer
Clear All Registers
Load Input Register
Load Input Register and DAC Register
Update DAC Register
X = don’t care.
Table II. AD5341 Truth Table
CLR
LDAC
CS
WR
HBEN
Function
1
1
0
1
1
1
1
1
1
1
X
1
1
0
0
0
1
X
X
0
0
0
0
X
X
1
X
0➝1
0➝1
0➝1
0➝1
X
X
X
X
0
1
0
1
X
No Data Transfer
No Data Transfer
Clear All Registers
Load Low-Byte Input Register
Load High-Byte Input Register
Load Low-Byte Input Register and DAC Register
Load High-Byte Input Register and DAC Register
Update DAC Register
X = don’t care.
REV. 0
–15–
AD5330/AD5331/AD5340/AD5341
SUGGESTED DATABUS FORMATS
In most applications GAIN and BUF are hard-wired. However,
if more flexibility is required, they can be included in a databus.
This enables you to software program GAIN, giving the option
of doubling the resolution in the lower half of the DAC range.
In a bused system, GAIN and BUF may be treated as data inputs
since they are written to the device during a write operation and
take effect when LDAC is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC
devices can be controlled using common GAIN and BUF lines.
In the case of the AD5330 this means that the databus must be
wider than eight bits. The AD5331 and AD5340 databuses must
be at least 10 and 12 bits wide respectively and are best suited
to a 16-bit databus system.
Examples of data formats for putting GAIN and BUF on a 16bit databus are shown in Figure 31. Note that any unused bits
above the actual DAC data may be used for BUF and GAIN.
DAC devices can be controlled using common GAIN and
BUF lines.
APPLICATIONS INFORMATION
Typical Application Circuits
The AD5330/AD5331/AD5340/AD5341 can be used with a
wide range of reference voltages, especially if the reference inputs
are configured to be unbuffered, in which case the devices offer
full, one-quadrant multiplying capability over a reference range
of 0.25 V to VDD. More typically, these devices may be used with a
fixed, precision reference voltage. Figure 34 shows a typical
setup for the devices when using an external reference connected to
the unbuffered reference inputs. If the reference inputs are unbuffered, the reference input range is from 0.25 V to VDD, but if the
on-chip reference buffers are used, the reference range is reduced.
Suitable references for 5 V operation are the AD780 and REF192.
For 2.5 V operation, a suitable external reference would be the
AD589, a 1.23 V bandgap reference.
VDD = 2.5V TO 5.5V
10␮F
0.1␮F
AD5330
BUF GAIN
X
X
X
X
X
X
VIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AD5331
BUF GAIN
X
X
BUF GAIN X
X
X
X
VDD
EXT
REF
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VREF
VOUT
VOUT
GND
AD5330/AD5331/
AD5340/AD5341
AD5340
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 2.5V
X = UNUSED BIT
Figure 31. GAIN and BUF Data on a 16-Bit Bus
The AD5341 is a 12-bit device that uses byte load, so only four
bits of the high byte are actually used as data. Two of the unused
bits can be used for GAIN and BUF data by connecting them
to the GAIN and BUF inputs; e.g., Bits 6 and 7, as shown in
Figures 32 and 33.
8-BIT
DATA BUS
Figure 34. AD5330/AD5331/AD5340/AD5341 Using
External Reference
Driving VDD From the Reference Voltage
If an output range of zero to VDD is required, the simplest solution is to connect the reference inputs to VDD. As this supply may
not be very accurate, and may be noisy, the devices may be
powered from the reference voltage, for example using a 5 V
reference such as the ADM663 or ADM666, as shown in
Figure 35.
DATA
INPUTS
DB6 DB7
BUF
GND
AD5341
GAIN
LDAC
6V TO 16V
CLR
CS
WR
0.1␮F
10␮F
HBEN
VIN
Figure 32. AD5341 Data Format for Byte Load with GAIN
and BUF Data on 8-Bit Bus
ADM663/ADM666
SENSE
In this case, the low byte is written first in a write operation
with HBEN = 0. Bits 6 and 7 of DAC data will be written into
GAIN and BUF registers but will have no effect. The high byte
is then written. Only the lower four bits of data are written into the
DAC high byte register, so Bits 6 and 7 can be GAIN and BUF
data.
VOUT(2)
VSET GND SHDN 0.1␮F
HIGH BYTE
X
X
DB11 DB10 DB9 DB8
VREF
VOUT
AD5330/AD5331/
AD5340/AD5341
GND
LDAC is used to update the DAC, GAIN and BUF values.
BUF GAIN
VDD
Figure 35. Using an ADM663/ADM666 as Power and Reference to AD5330/AD5331/AD5340/AD5341
LOW BYTE
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X = UNUSED BIT
Figure 33. AD5341 with GAIN and BUF Data on 8-Bit Bus
–16–
REV. 0
AD5330/AD5331/AD5340/AD5341
The 74HC139 is used as a 2- to 4-line decoder to address any
of the DACs in the system. To prevent timing errors, the enable
input should be brought to its inactive state while the coded
address inputs are changing state. Figure 37 shows a diagram of a
typical setup for decoding multiple devices in a system. Once
data has been written sequentially to all DACs in a system, all the
DACs can be updated simultaneously using a common LDAC
line. A common CLR line can also be used to reset all DAC
outputs to zero.
Bipolar Operation Using the AD5330/AD5331/AD5340/AD5341
The AD5330/AD5331/AD5340/AD5341 have been designed
for single supply operation, but bipolar operation is achievable
using the circuit shown in Figure 36. The circuit shown has been
configured to achieve an output voltage range of –5 V < VO <
+5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
VO = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] – R4 × VREF/R3
AD5330/AD5331/
AD5340/AD5341
where:
D is the decimal equivalent of the code loaded to the DAC, N is
DAC resolution and VREF is the reference voltage input.
HBEN*
WR
LDAC
CLR
CS
HBEN
WR
LDAC
CLR
With:
VREF = 2.5 V
R1 = R3 = 10 kΩ
R2 = R4 = 20 kΩ and VDD = 5 V.
VOUT = (10 × D/2N) – 5
AD5330/AD5331/
AD5340/AD5341
VDD
R4
20k⍀
10␮F
EXT
REF
ⴞ5V
VDD
0.1␮F
AD5330/AD5331/
AD5340/AD5341
–5V
1Y1
74HC139
1B
DGND
R1
10k⍀
1Y2
AD5330/AD5331/
AD5340/AD5341
HBEN*
WR
LDAC
CLR
CS
DATA
INPUTS
AD5330/AD5331/
AD5340/AD5341
R2
20k⍀
HBEN*
WR
LDAC
CLR
CS
GND
Figure 36. Bipolar Operation using the AD5330/AD5331/
AD5340/AD5341
DATA
INPUTS
*AD5341 ONLY
Figure 37. Decoding Multiple DAC Devices
Decoding Multiple AD5330/AD5331/AD5340/AD5341
The CS pin on these devices can be used in applications to decode
a number of DACs. In this application, all DACs in the system
receive the same data and WR pulses, but only the CS to one of
the DACs will be active at any one time, so data will only be
written to the DAC whose CS is low. If multiple AD5341s are
being used, a common HBEN line will also be required to
determine if the data is written to the high-byte or low-byte
register of the selected DAC.
REV. 0
1Y0
1A
1Y3
VOUT
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 2.5V
CODED
ADDRESS
DATA
INPUTS
VCC
VREF
VOUT
GND
1G
ENABLE
+5V
R3
10k⍀
VIN
HBEN*
WR
LDAC
CLR
CS
–17–
DATA BUS
VDD = 5V
0.1␮F
DATA
INPUTS
AD5330/AD5331/AD5340/AD5341
Programmable Current Source
Power Supply Bypassing and Grounding
Figure 38 shows the AD5330/AD5331/AD5340/AD5341 used
as the control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor
of 4.7 kΩ in series with the 470 Ω adjustment potentiometer,
which gives an adjustment of about ± 5%. Suitable transistors to
place in the feedback loop of the amplifier include the BC107
and the 2N3904, which enable the current source to operate
from a minimum VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable
amplifiers include the AD820 and the OP295, both having railto-rail operation on their outputs. The current for any digital
input code and resistor value can be calculated as follows:
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5330/AD5331/AD5340/AD5341 is mounted should be
designed so that the analog and digital sections are separated,
and confined to certain areas of the board. If the device is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as closely as possible to the device. The AD5330/AD5331/AD5340/AD5341
should have ample supply bypassing of 10 µF in parallel with
0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors
are the tantalum bead type. The 0.1 µF capacitor should have
low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low
impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
I = G × VREF ×
Where:
D
mA
(2N × R)
G is the gain of the buffer amplifier (1 or 2)
D is the digital equivalent of the digital input code
N is the DAC resolution (8, 10, or 12 bits)
R is the sum of the resistor plus adjustment potentiometer in kΩ
VDD = 5V
0.1␮F
10␮F
VSOURCE
VIN
5V
VDD
EXT
REF
VREF
VOUT
GND
0.1␮F
LOAD
VOUT
AD5330/AD5331/
AD5340/AD5341
AD820/
OP295
AD780/REF192
WITH VDD = 5V
The power supply lines of the device should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run
near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run
at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far
the best, but not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground plane while signal traces are placed on the solder side.
4.7k⍀
GND
470⍀
Figure 38. Programmable Current Source
–18–
REV. 0
AD5330/AD5331/AD5340/AD5341
Table III. Overview of AD53xx Parallel Devices
Part No.
Resolution DNL
VREF Pins
Settling Time
SINGLES
AD5330
AD5331
AD5340
AD5341
8
10
12
12
± 0.25
± 0.5
± 1.0
± 1.0
1
1
1
1
6 µs
7 µs
8 µs
8 µs
DUALS
AD5332
AD5333
AD5342
AD5343
8
10
12
12
± 0.25
± 0.5
± 1.0
± 1.0
2
2
2
1
6 µs
7 µs
8 µs
8 µs
QUADS
AD5334
AD5335
AD5336
AD5344
8
10
10
12
± 0.25
± 0.5
± 0.5
± 1.0
2
2
4
4
6 µs
7 µs
7 µs
8 µs
Additional Pin Functions
BUF
✓
✓
✓
GAIN
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Package
Pins
✓
CLR
✓
✓
✓
✓
TSSOP
TSSOP
TSSOP
TSSOP
20
20
24
20
✓
✓
✓
✓
✓
TSSOP
TSSOP
TSSOP
TSSOP
20
24
28
20
✓
✓
✓
TSSOP
TSSOP
TSSOP
TSSOP
24
24
28
28
HBEN
✓
Table IV. Overview of AD53xx Serial Devices
Part No.
Resolution
No. of DACs
DNL
Interface
Settling Time
Package
Pins
SINGLES
AD5300
AD5310
AD5320
8
10
12
1
1
1
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
4 µs
6 µs
8 µs
SOT-23, MicroSOIC
SOT-23, MicroSOIC
SOT-23, MicroSOIC
6, 8
6, 8
6, 8
AD5301
AD5311
AD5321
8
10
12
1
1
1
± 0.25
± 0.5
± 1.0
2-Wire
2-Wire
2-Wire
6 µs
7 µs
8 µs
SOT-23, MicroSOIC
SOT-23, MicroSOIC
SOT-23, MicroSOIC
6, 8
6, 8
6, 8
DUALS
AD5302
AD5312
AD5322
8
10
12
2
2
2
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
6 µs
7 µs
8 µs
MicroSOIC
MicroSOIC
MicroSOIC
8
8
8
AD5303
AD5313
AD5323
8
10
12
2
2
2
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
6 µs
7 µs
8 µs
TSSOP
TSSOP
TSSOP
16
16
16
QUADS
AD5304
AD5314
AD5324
8
10
12
4
4
4
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
6 µs
7 µs
8 µs
MicroSOIC
MicroSOIC
MicroSOIC
10
10
10
AD5305
AD5315
AD5325
8
10
12
4
4
4
± 0.25
± 0.5
± 1.0
2-Wire
2-Wire
2-Wire
6 µs
7 µs
8 µs
MicroSOIC
MicroSOIC
MicroSOIC
10
10
10
AD5306
AD5316
AD5326
8
10
12
4
4
4
± 0.25
± 0.5
± 1.0
2-Wire
2-Wire
2-Wire
6 µs
7 µs
8 µs
TSSOP
TSSOP
TSSOP
16
16
16
AD5307
AD5317
AD5327
8
10
12
4
4
4
± 0.25
± 0.5
± 1.0
SPI
SPI
SPI
6 µs
7 µs
8 µs
TSSOP
TSSOP
TSSOP
16
16
16
Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html
REV. 0
–19–
AD5330/AD5331/AD5340/AD5341
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3828–2.5–4/00 (rev. 0)
20-Lead Thin Shrink Small Outline Package TSSOP
(RU-20)
0.260 (6.60)
0.252 (6.40)
20
11
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
10
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
24-Lead Thin Shrink Small Outline Package TSSOP
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
12
PIN 1
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
0.006 (0.15)
0.002 (0.05)
–20–
REV. 0
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