ASAHI KASEI [AK4394] AK4394 Advanced Multi-Bit 192kHz 24-Bit DS DAC GENERAL DESCRIPTION The AK4394 is a high performance stereo DAC for the 192kHz sampling mode of DVD-Audio including a 24bit digital filter. The AK4394 introduces the advanced multi-bit system for DS modulator. This new architecture achieves the wider dynamic range, while keeping much the same superior distortion characteristics as conventional Single-Bit way. In the AK4394, the analog outputs are filtered in the analog domain by switched-capacitor filter(SCF) with high tolerance to clock jitter. The analog outputs are full differential output, so the device is suitable for hi-end applications. The digital I/F can correspond to TTL levels, so it is easy to I/F with 3.3V logic IC. FEATURES · 128x Oversampling · Sampling Rate up to 192kHz · 24Bit 8x Digital Filter (Slow-roll-off option) Ripple: ±0.005dB, Attenuation: 75dB · High Tolerance to Clock Jitter · Low Distortion Differential Output · Digital de-emphasis for 32, 44.1, 48 & 96kHz sampling · Soft Mute · THD+N: -100dB · DR, S/N: 120dB · I/F format : MSB justified, 16/20/24bit LSB justified, I2S · Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs Double Speed: 128fs, 192fs, 256fs or 384fs Quad Speed: 128fs or 192fs · Power Supply: 5V±5% · TTL Level Digital I/F · Small Package: 28pin VSOP · Pin Compatible with AK4393 DIF0 LRCK BICK SDATA PDN SMUTE DIF1 DIF2 DVDD DVSS DEM0 DEM1 AVDD AVSS BVSS De-emphasis Control Audio Data Interface VCOM DZFL De-emphasis Soft Mute 8x Interpolator DS Modulator SCF De-emphasis Soft Mute 8x Interpolator DS Modulator SCF AOUTL+ AOUTLAOUTR+ AOUTR- DFS0 DZFR Control Register CSN CCLK CDTI Clock Divider P/S MCLK CKS0 M0081-E-00 CKS1 CKS2 VREFH VREFL 1999/11 -1- ASAHI KASEI [AK4394] n Ordering Guide AK4394VF AKD4394 -40 ~ +85 °C 28pin VSOP (0.65mm pitch) Evaluation Board n Pin Layout DVSS 1 28 CKS2/DZFR DVDD 2 27 CKS1 MCLK 3 26 CKS0/DZFL PDN 4 25 P/S BICK 5 24 VCOM SDATA 6 23 AOUTL+ LRCK 7 22 AOUTL- SMUTE/CSN 8 21 AOUTR+ DFS0 9 20 AOUTR- DEM0/CCLK 10 19 AVSS DEM1/CDTI 11 18 AVDD DIF0 12 17 VREFH DIF1 13 16 VREFL DIF2 14 15 BVSS Top View n Pin Compatibility with AK4393 AK4393 AK4394 108kHz 216kHz slow roll-off filter not available available zero detection not available available 3~5.25V CKS0 CKS2 0 0 0 0 4.75~5.25V DZFL DZFR DFS1 SLOW DZFM DZFE fs (max) DVDD pin #26 (serial mode) pin #28 (serial mode) Control register : 01H D4 Control register : 01H D5 Control register : 01H D6 Control register : 01H D7 M0081-E-00 1999/11 -2- ASAHI KASEI [AK4394] PIN/FUNCTION No. 1 2 3 Pin Name I/O DVSS DVDD MCLK PDN I I BICK I SDATA I Audio Serial Data Input Pin 2’s complement MSB-first data is input on this pin. LRCK SMUTE I I CSN DFS0 I I DEM0 CCLK DEM1 CDTI DIF0 DIF1 DIF2 BVSS VREFL VREFH AVDD AVSS AOUTRAOUTR+ AOUTLAOUTL+ VCOM P/S I I I I I I I I I O O O O O I CKS0 DZFL CKS1 I O I L/R Clock Pin Soft Mute Pin in parallel mode When this pin goes "H", soft mute cycle is initiated. When returning “L”, the output mute releases. Chip Select Pin in serial mode Double Speed Sampling Mode Pin (Internal pull-down pin) “L”: Normal Speed , “H”: Double Speed De-emphasis Enable Pin in parallel mode Control Data Clock Pin in serial mode De-emphasis Enable Pin in parallel mode Control Data Input Pin in serial mode Digital Input Format Pin Digital Input Format Pin Digital Input Format Pin Substrate Ground Pin, 0V Low Level Voltage Reference Input Pin High Level Voltage Reference Input Pin Analog Power Supply Pin, 5.0V Analog Ground Pin, 0V Rch Negative analog output Pin Rch Positive analog output Pin Lch Negative analog output Pin Lch Positive analog output Pin Common Voltage Output Pin, 2.6V Parallel/Serial Select Pin (Internal pull-up pin) “L”: Serial control mode, “H”: Parallel control mode Master Clock Select Pin in parallel mode Lch Zero Input Detect Pin in serial mode Master Clock Select Pin CKS2 I Master Clock Select Pin in parallel mode DZFR O Rch Zero Input Detect Pin in serial mode 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function Digital Ground Pin Digital Power Supply Pin, 5.0V Master Clock Input Pin Power-Down Mode Pin When at “L”, the AK4394 is in power-down mode and is held in reset. The AK4394 should always be reset upon power-up. Audio Serial Data Clock Pin The clock of 64fs or more than is recommended to be input on this pin. Note: All input pins except internal pull-up/down pins should not be left floating. M0081-E-00 1999/11 -3- ASAHI KASEI [AK4394] ABSOLUTE MAXIMUM RATINGS (AVSS, BVSS, DVSS = 0V; Note 1) Parameter Symbol min -0.3 Power Supplies: Analog AVDD -0.3 Digital DVDD | BVSS-DVSS | (Note 2) D GND Input Current , Any pin Except Supplies IIN Input Voltage VIND -0.3 Ambient Operating Temperature Ta -40 Storage Temperature Tstg -65 Notes: 1. All voltages with respect to ground. 2. AVSS, BVSS and DVSS must be connected to the same analog ground plane. max 6.0 6.0 0.3 ±10 DVDD+0.3 85 150 Units V V V mA V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, BVSS, DVSS=0V; Note 1) Parameter Symbol min typ Power Supplies: Analog AVDD 4.75 5.0 (Note 3) Digital DVDD 4.75 5.0 AVDD-0.5 Voltage Reference “H” voltage reference VREFH AVSS (Note 4) “L” voltage reference VREFL 3.0 VREFH-VREFL D VREF Notes: 3. The power up sequence between AVDD and DVDD is not critical. 4. Analog output voltage scales with the voltage of (VREFH-VREFL). AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5. max 5.25 5.25 AVDD AVDD Units V V V V V * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. M0081-E-00 1999/11 -4- ASAHI KASEI [AK4394] ANALOG CHARACTERISTICS (Ta = 25°C; AVDD, DVDD = 5V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz; RL ³ 600W; External circuit: Figure 12; unless otherwise specified) Parameter min typ max Units 24 Bits -100 -53 -97 -51 -97 -51 117 120 117 120 120 -90 -87 - dB dB dB dB dB dB dB dB dB dB dB 0.15 20 ±2.4 0.3 ±2.55 dB ppm/°C Vpp W mA Resolution Dynamic Characteristics (Note 5) THD+N fs=44.1kHz 0dBFS BW=20kHz -60dBFS fs=96kHz 0dBFS BW=40kHz -60dBFS fs=192kHz 0dBFS BW=40kHz -60dBFS Dynamic Range (-60dBFS with A-weighted) (Note 6) (Note 7) S/N (A-weighted (Note 8) (Note 7) Interchannel Isolation (1kHz) 112 112 100 DC Accuracy Interchannel Gain Mismatch Gain Drift Output Voltage Load Resistance Output Current (Note 9) (Note 10) (Note 11) ±2.25 600 3.5 Power Supplies Power Supply Current Normal Operation (PDN = “H”) AVDD DVDD(fs=44.1kHz) DVDD(fs=96kHz) DVDD(fs=192kHz) AVDD + DVDD 60 5 8 12 90 mA mA mA mA mA Power-Down Mode (PDN = “L”) AVDD + DVDD (Note 12) 10 100 µA Power Supply Rejection (Note 13) 50 dB Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode. At 96kHz and 192kHz, measured by ROHDE & SCHWARZ, UPD. Averaging mode. Refer to the eva board manual. 6. 101dB at 16bit data and 116dB at 20bit data. 7. By Figure13. External LPF Circuit Example 2. 8. S/N does not depend on input bit length. 9. The voltage on (VREFH-VREFL) is held +5V externally. 10. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFH-VREFL). AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×(VREFH-VREFL)/5. 11. For AC-load. 1kW for DC-load. 12. In the power-down mode. P/S = DVDD, and all other digital input pins including clock pins (MCLK, BICK and LRCK) are held DVSS. 13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V. M0081-E-00 1999/11 -5- ASAHI KASEI [AK4394] SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF; SLOW = “0”) Parameter Symbol min typ max Units PB 0 24.1 22.05 20.0 - kHz kHz kHz dB dB 1/fs Digital Filter ±0.01dB -6.0dB Passband Stopband Passband Ripple Stopband Attenuation Group Delay (Note 14) (Note 14) (Note 15) SB PR SA GD ± 0.005 75 - 28 - Digital Filter + SCF Frequency Response 0 ~ 20.0kHz dB ± 0.2 Note: 14. The passband and stopband frequencies scale with fs. For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs. 15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal. SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF; SLOW = “0”) Parameter Symbol min (Note 14) PB (Note 14) SB PR SA GD 0 52.5 typ max Units 48.0 43.5 - Digital Filter ±0.01dB -6.0dB Passband Stopband Passband Ripple Stopband Attenuation Group Delay (Note 15) 75 - 28 - kHz kHz kHz dB dB 1/fs - ± 0.3 - dB ± 0.005 Digital Filter + SCF 0 ~ 40.0kHz Frequency Response SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) (Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 192kHz; Quad Speed Mode; DEM = OFF; SLOW = “0”) Parameter symbol min typ max Units PB 0 - 96.0 87.0 - kHz kHz Digital Filter Passband ±0.01dB -6.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 14) (Note 14) SB (Note 15) PR SA GD 105 kHz ± 0.005 75 - 28 - dB dB 1/fs - +0/-1 - dB Digital Filter + SCF Frequency Response 0 ~ 80.0kHz M0081-E-00 1999/11 -6- ASAHI KASEI [AK4394] SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF; SLOW = “1”) Parameter Symbol min typ max Units PB 0 39.2 18.2 8.1 - Digital Filter ±0.04dB -3.0dB Passband Stopband Passband Ripple Stopband Attenuation Group Delay (Note 16) (Note 16) (Note 15) SB PR SA GD 28 - kHz kHz kHz dB dB 1/fs +0/-5 - dB ± 0.005 72 - Digital Filter + SCF Frequency Response 0 ~ 20.0kHz Note: 16. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs. SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF; SLOW = “1”) Parameter Symbol min typ max Units PB 0 85.3 39.6 17.7 - Digital Filter ±0.04dB -3.0dB Passband Stopband Passband Ripple Stopband Attenuation Group Delay (Note 16) (Note 16) (Note 15) SB PR SA GD 72 - 28 - kHz kHz kHz dB dB 1/fs - +0/-4 - dB ± 0.005 Digital Filter + SCF 0 ~ 40.0kHz Frequency Response SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) (Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 192kHz; Quad Speed Mode; DEM = OFF; SLOW = “1”) Parameter Symbol min typ max Units PB 0 171 79.1 35.5 - Digital Filter Passband ±0.04dB -3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 16) (Note 16) (Note 15) SB PR SA GD 72 - 28 - kHz kHz kHz dB dB 1/fs - +0/-5 - dB ± 0.005 Digital Filter + SCF Frequency Response 0 ~ 80.0kHz M0081-E-00 1999/11 -7- ASAHI KASEI [AK4394] DC CHARACTERISTICS (Ta = 25°C; AVDD, DVDD = 4.75~5.25V) Parameter High-Level Input Voltage Low-Level Input Voltage Symbol VIH VIL min 2.2 - typ - max 0.8 Units V V VOH DVDD-0.5 High-Level Output Voltage (Iout = -100mA) VOL Low-Level Output Voltage (Iout = 100mA) Input Leakage Current (Note 17) Iin Note: 17. DFS0, P/S pins have internal pull-down or pull-up devices, nominally 100kW. 0.5 ± 10 V V µA max Units SWITCHING CHARACTERISTICS (Ta = 25°C; AVDD, DVDD = 4.75~5.25V; CL = 20pF) Parameter Master Clock Timing Frequency Duty Cycle LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle Serial Interface Timing BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “” to LRCK Edge LRCK Edge to BICK “” SDATA Hold Time SDATA Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “¯” to CCLK “” CCLK “” to CSN “” Reset Timing PDN Pulse Width Symbol min typ fCLK dCLK 7.7 40 41.472 60 MHz % fsn fsd fsq Duty 30 60 120 45 54 108 216 55 kHz kHz kHz % tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/64fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns tPD 150 ns (Note 18) (Note 19) (Note 19) (Note 20) Notes: 18. When the normal/double/quad speed modes are switched, AK4394 should be reset by PDN pin or RSTN bit. 19. BICK rising edge must not occur at the same time as LRCK edge. 20. The AK4394 can be reset by bringing PDN “L” to “H”. When the states of CKS2-0 or DFS1-0 change, the AK4394 should be reset by PDN pin or RSTN bit. M0081-E-00 1999/11 -8- ASAHI KASEI [AK4394] n Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDATA VIL Audio Interface Timing M0081-E-00 1999/11 -9- ASAHI KASEI [AK4394] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS C1 CDTI tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL WRITE Data Input Timing tPD PDN VIL Power-down Timing M0081-E-00 1999/11 - 10 - ASAHI KASEI [AK4394] OPERATION OVERVIEW n System Clock The external clocks, which are required to operate the AK4394, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. The sampling speed is set by DFS0/1(Table 1). The sampling rate (LRCK), CKS0/1/2 and DFS0/1 determine the frequency of MCLK (Table 2). In parallel mode, since DFS1 is always “0”, the quad speed mode can not be available. All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4394 is in normal operation mode (PD = “H”). If these clocks are not provided, the AK4394 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4394 should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4394 is in power-down mode until MCLK and LRCK are input. DFS1 DFS0 Sampling Rate (fs) 0 0 Normal Speed Mode 30kHz~54kHz 0 1 Double Speed Mode 60kHz~108kHz 1 0 Quad Speed Mode 120kHz~216kHz Default Table 1. Sampling Speed Mode CKS2 CKS1 CKS0 Normal Double Quad 0 0 0 0 256fs 128fs N/A 1 0 0 1 256fs 256fs N/A 2 0 1 0 384fs 192fs N/A 3 0 1 1 384fs 384fs N/A 4 5 6 7 1 1 1 1 0 0 1 1 0 1 0 1 512fs 512fs 768fs 768fs 256fs N/A 384fs N/A 128fs N/A 192fs N/A Default Table 2. System Clocks Note: The master clock at quad speed supports only 128fs or 192fs. LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz MCLK 384fs 512fs 12.2880MHz 16.3840MHz 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz 768fs 24.5760MHz 33.8688MHz 36.8640MHz BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz Table 3. System clock example (Normal Speed Mode) M0081-E-00 1999/11 - 11 - ASAHI KASEI [AK4394] LRCK fs 88.2kHz 96.0kHz MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz 128fs 11.2896MHz 12.2880MHz BICK 64fs 5.6448MHz 6.1440MHz 384fs 33.8688MHz 36.8640MHz Table 4. System clock example (Double Speed Mode) LRCK fs 176.4kHz 192.0kHz MCLK 128fs 192fs 22.5792MHz 33.8688MHz 24.5760MHz 36.8640MHz BICK 64fs 11.2896MHz 12.2880MHz Table 5. System clock example (Quad Speed Mode) n Audio Serial Interface Format Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the DIF0-2 as shown in Table 6. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 Mode 0: 16bit LSB Justified 1: 20bit LSB Justified 2: 24bit MSB Justified 3: I2S Compatible 4: 24bit LSB Justified BICK ³32fs ³40fs ³48fs ³48fs ³48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Table 6. Audio Data Formats LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDATA Mode 0 15 0 14 1 6 5 14 4 15 3 2 16 17 1 0 31 15 0 14 1 6 5 14 4 15 3 16 2 17 1 0 31 15 0 14 1 BICK (64fs) SDATA Mode 0 Don’t care 15 14 0 Don’t care 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing M0081-E-00 1999/11 - 12 - ASAHI KASEI [AK4394] LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1 0 1 BICK (64fs) SDATA Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 19 0 19:MSB, 0:LSB SDATA Mode 4 Don’t care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1,4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDATA 23 22 1 0 Don’t care 23 22 0 1 Don’t care 23 22 0 1 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 BICK (64fs) SDATA 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing M0081-E-00 1999/11 - 13 - ASAHI KASEI [AK4394] n De-emphasis filter A digital de-emphasis filter is available for 32, 44.1, 48 or 96kHz sampling rates (tc = 50/15µs) and is enabled or disabled with the DEM0, DEM1 and DFS0 input pins. In case of quad mode (DFS1 = “1”), the digital de-emphasis filter is always off. DEM1 DEM0 DFS0 Mode 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 44.1kHz OFF 48kHz 32kHz OFF OFF 96kHz OFF Default Table 7. De-emphasis filter control (DFS1 = “0”) M0081-E-00 1999/11 - 14 - ASAHI KASEI [AK4394] n Zero detection The AK4394 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. n Soft mute operation Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -¥ during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission. SM U T E 1024/fs 0dB 1024/fs (1) (3) Attenuation -¥ GD (2) GD AO U T DZF (4) 8192/fs Notes: (1) The output signal is attenuated by -¥ during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. (4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”. Figure 5. Soft mute and zero detection M0081-E-00 1999/11 - 15 - ASAHI KASEI [AK4394] n System Reset The AK4394 should be reset once by bringing PDN = “L” upon power-up. The AK4394 is powered up and the internal timing starts clocking by LRCK “” after exiting reset and power down state by MCLK. The AK4394 is in the power-down mode until MCLK and LRCK are input. n Power-Down The AK4394 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure 6 shows an example of the system timing at the power-down and power-up. PDN Internal State Normal Operation Power-down D/A In (Digital) Normal Operation “0” data GD D/A Out (Analog) (1) GD (2) (3) (3) (1) (4) Clock In Don’t care MCLK, LRCK, BICK DZFL/DZFR External MUTE (6) (5) Mute ON Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”). (5) Please mute the analog output externally if the click noise (3) influences system application. The timing example is shown in this figure. (6) DZF pins are “L” in the power-down mode (PDN = “L”). Figure 6. Power-down/up sequence example M0081-E-00 1999/11 - 16 - ASAHI KASEI [AK4394] n Reset Function When RSTN = ”0”, the AK4394’s digital section is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pins of both channels go to “H”. Figure 7 shows the example of reset by RSTN bit. RSTN bit 3~4/fs (6) 2~3/fs (6) Internal RSTN bit Internal State Normal Operation D/A In (Digital) “0” data (1) D/A Out (Analog) Normal Operation Digital Block Power-down GD GD (2) (3) (3) (1) (4) Clock In Don’t care MCLK,LRCK,BICK 2/fs(5) DZFL/DZFR Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage. (3) Click noise occurs at the edges(“ ¯”) of the internal timing of RSTN bit. This noise is output even if “0” data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”). (5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”. (6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the internal RSTN “1”. Figure 7. Reset sequence example M0081-E-00 1999/11 - 17 - ASAHI KASEI [AK4394] n Mode Control Interface Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4394. For DIF0/1/2, CKS1 and DFS0, the setting of pin and register are “ORed” internally. So, even serial control mode, these functions can be also controlled by pin setting. The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting must be all “L”. Internal registers may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). The AK4394 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The writing of data becomes valid by CSN “”. The clock speed of CCLK is 5MHz(max). The CSN and CCLK must be fixed to “H” when the register does not be accessed. Function Parallel mode Serial mode O X O O X X O O O O O O Double speed Quad speed De-emphasis SMUTE Zero Detection Slow roll-off response Table 8. Function List (O: Available, X: Not available) PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4394 should be reset by PDN = “L”. In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to “01”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 8. Control I/F Timing *The AK4394 does not support the read command and chip address. C1/0 and R/W are fixed to “011” *When the AK4394 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register is inhibited. *For setting the registers, the following sequence is recommended. Control 1 register (1) Writing RSTN = “0” and other bits (D6-D1) to the register at the same time. (2) Writing RSTN = “1” to the register. The other bits are no change. Control 2 register This writing sequence has no limitation like control 1 register. When setting DEM0/1 and SMUTE, RSTN is not needed. M0081-E-00 1999/11 - 18 - ASAHI KASEI [AK4394] n Register Map Addr 00H 01H 02H Register Name Control 1 Control 2 Test D7 D6 D5 D4 D3 D2 D1 D0 0 DZFE GA1 CKS2 DZFM GA0 CKS1 SLOW TEST5 CKS0 DFS1 TEST4 DIF2 DFS0 TEST3 DIF1 DEM1 TEST2 DIF0 DEM0 TEST1 RSTN SMUTE TEST0 Notes: For addresses from 03H to 1FH, data must not be written. When PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the only internal timing is reset and the registers are not initialized to their default values. DIF0-2, CKS1, DFS0 bits are ORed with pins respectively. n Register Definitions Addr 00H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 1 0 CKS2 CKS1 CKS0 DIF2 DIF1 DIF0 RSTN default 0 0 0 0 0 0 0 1 RSTN: Internal timing reset 0: Reset. All registers are not initialized. 1: Normal Operation When the states of CKS2-0 or DFS1-0 change, the AK4394 should be reset by PDN pin or RSTN bit. DIF2-0: Audio data interface modes (see Table 6) Initial: “000”, Mode 0 Register bits are ORed with DIF2-0 pins if P/S = “L”. CKS2-0: Master Clock Frequency Select (see Table 2) Initial: “000”, Mode 0 CKS1 register bit is ORed with CKS1 pin if P/S = “L”. Addr 01H Register Name D7 D6 D5 D4 D3 D2 D1 D0 Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE default 0 0 0 0 0 0 0 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis response (see Table 7) Initial: “00”, 44.1kHz DFS1-0: Sampling speed control (see Table 1) 00: Normal speed 01: Double speed 10: Quad speed Register bit of DFS0 is ORed with DFS0 pin if P/S = “L”. When changing between Normal/Double Speed Mode and Quad Speed Mode, DFS1 bit should be changed after changing MCLK frequency. Some click noise occurs at that time. M0081-E-00 1999/11 - 19 - ASAHI KASEI [AK4394] SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”. DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Addr 02H Register Name Test default D7 D6 D5 D4 D3 D2 D1 D0 GA1 GA0 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 0 0 0 0 0 0 0 0 GA1-0: Output Gain Control 00: 0dB 01: 2.5dB 10: -1dB 11: 1.16dB TEST5-0: Test mode. Do not write any data to D5-0 of 02H. M0081-E-00 1999/11 - 20 - ASAHI KASEI [AK4394] SYSTEM DESIGN Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4394) is available which demonstrates the optimum layout, power supply arrangements and measurement results. Digital Supply 5V 10u 0.1u + 1 DVSS DZFR 28 2 DVDD CKS1 27 Master Clock 3 MCLK DZFL 26 Reset & Power down 4 PDN P/S 25 64fs 5 BICK VCOM 24 24bit Audio Data 6 SDATA AOUTL+ 23 Lch Lch 7 LRCK AOUTL- 22 LPF Mute Rch LPF Rch Mute fs AK4394 8 CSN AOUTR+ 21 Micro- 9 DFS0 AOUTR- 20 controller 10 CCLK AVSS 11 CDTI AVDD 12 DIF0 VREFH 13 DIF1 VREFL 14 DIF2 BVSS Digital Ground 0.1u 19 0.1u 18 10u + 17 0.1u 16 + 10u 10u + Lch Out Rch Out Analog Supply 5V 15 Analog Ground Figure 9. Typical Connection Diagram (Serial mode) Notes: - LRCK = fs, BICK = 64fs. - Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. - AVSS, BVSS and DVSS must be connected to the same analog ground plane. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except pull-down/pull-up pins should not be left floating. M0081-E-00 1999/11 - 21 - ASAHI KASEI [AK4394] Digital Supply 5V 10u 0.1u + 1 DVSS CKS2 28 2 DVDD CKS1 27 Master Clock Select Master Clock 3 MCLK CKS0 26 Reset & Power down 4 PDN P/S 25 64fs 5 BICK VCOM 24 24bit Audio Data 6 SDATA AOUTL+ 23 Lch 7 LRCK AOUTL- 22 LPF 8 SMUTE AOUTR+ 21 9 DFS0 AOUTR- 20 Rch LPF 10 DEM0 AVSS 11 DEM1 AVDD 12 DIF0 VREFH 13 DIF1 VREFL 14 DIF2 BVSS fs Mode setting Digital Ground AK4394 10u + 0.1u 19 0.1u 18 + 10u 17 0.1u 16 + 10u Lch Out Rch Out Analog Supply 5V 15 Analog Ground Figure 10. Typical Connection Diagram (Parallel mode) Notes: - LRCK = fs, BICK = 64fs. - Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. - AVSS, BVSS and DVSS must be connected to the same analog ground plane. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except pull-down/pull-up pins should not be left floating. Digital Ground Analog Ground System Controller 1 DVSS CKS2 28 2 DVDD CKS1 27 3 MCLK CKS0 26 4 PDN P/S 25 5 BICK VCOM 24 6 SDATA AOUTL+ 23 7 LRCK AOUTL- 22 8 SMUTE AOUTR+ 21 9 DFS AOUTR- 20 10 DEM0 AVSS 19 11 DEM1 AVDD 18 12 DIF0 VREFH 17 13 DIF1 VREFR 16 14 DIF2 BVSS 15 AK4394 Figure 11. Ground Layout M0081-E-00 1999/11 - 22 - ASAHI KASEI [AK4394] 1. Grounding and Power Supply Decoupling To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively. AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. If AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as possible. 2. Voltage Reference The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to AVDD and VREFL pin is normally connected to AVSS. VREFH and VREFL should be connected with a 0.1µF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted coupling into the AK4394. 3. Analog Outputs The analog outputs are full differential outputs and 2.4Vpp (typ@VREF=5V) centered around VCOM. The differential outputs are summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 4.8Vpp (typ@VREF=5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal V AOUT is 0V for 000000H(@24bit). The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Figure 12 shows an example of external LPF circuit summing the differential outputs by an op-amp. Figure 13 shows an example of differential outputs and LPF circuit example by three op-amps. AK4394 AOUT- 1k 1k 1k 1n +Vop 3.3n AOUT+ 1k Analog Out 1k 1k 1n -Vop Figure 12. External LPF Circuit Example 1 M0081-E-00 1999/11 - 23 - ASAHI KASEI [AK4394] +15 10n 300 AOUTL- + 300 7 3 2 + 4 10n -15 10u 0.1u 6 NJM5534D + 10u 0.1u 300 220 3 2 620 2 - 4 3 + 7 620 AOUTL+ + 300 300 10n 7 3 + 2 4 Lch 0.1u 6 NJM5534D 0.1u + + 10u 10u 0.1u 300 220 10u 100 6 4.7n NJM5534D 430 + 100 620 10n +10u 4.7n 1 47u 0.1u 430 100 47u 620 + Figure 13. External LPF Circuit Example 2 M0081-E-00 1999/11 - 24 - ASAHI KASEI [AK4394] PACKAGE 28pin VSOP (Unit: mm) *9.8±0.2 1.25±0.2 0.675 28 A 7.6±0.2 *5.6±0.2 15 14 1 +0.1 0.15-0.05 0.65 0.22±0.1 0.1±0.1 0.5±0.2 Detail A 0.10 1.0 Seating Plane NOTE: Dimension "*" does not include mold flash. 0-10° n Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate M0081-E-00 1999/11 - 25 - ASAHI KASEI [AK4394] MARKING AKM AK4394VF XXXBYYYYC XXXXBYYYYC data code identifier XXXB: YYYYC: Lot number (X : Digit number, B : Alpha character ) Assembly date (Y : Digit number C : Alpha character) IMPORTANT NOTICE · These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. · AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. · Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. · AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. · It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. M0081-E-00 1999/11 - 26 -