ATMEL AT26DF081A-SSU 8-megabit 2.7-volt only serial firmware dataflash memory Datasheet

Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
• 70 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
•
•
•
•
•
•
•
•
•
•
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
Optimized Physical Sectoring for Code Shadowing and Code + Data Storage
Applications
– One 32-Kbyte Top Boot Sector
– Two 8-Kbyte Sectors
– One 16-Kbyte Sector
– Fifteen 64-Kbyte Sectors
Individual Sector Protection for Program/Erase Protection
Hardware Controlled Locking of Protected Sectors
Flexible Programming Options
– Byte/Page Program (1 to 256 Bytes)
– Sequential Program Mode Capability
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 7 mA Active Read Current (Typical)
– 11 µA Deep Power-down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 200-mil wide)
8-megabit
2.7-volt Only
Serial Firmware
DataFlash®
Memory
AT26DF081A
Preliminary
1. Description
The AT26DF081A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT26DF081A, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF081A have been optimized to meet the needs of today’s code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the
same overall device density.
3600A–DFLASH–11/05
The AT26DF081A also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments.
Specifically designed for use in 3-volt systems, the AT26DF081A supports read, program, and
erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for
programming and erasing.
2. Pin Descriptions and Pinouts
Table 2-1.
Pin Descriptions
Asserted
State
Type
Low
Input
Symbol
Name and Function
CS
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SCK
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
Input
SI
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
Input
SO
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
WP
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to
section “Protection Commands and Features” on page 14 for more details on protection features
and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware-controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to VCC
whenever possible.
Low
Input
HOLD
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold”
on page 26 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to VCC whenever
possible.
Low
Input
VCC
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
Power
GND
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
Power
2
Output
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
Figure 2-1.
CS
SO
WP
GND
8-SOIC Top View
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
3. Block Diagram
CONTROL AND
PROTECTION LOGIC
CS
SI
SO
SRAM
DATA BUFFER
INTERFACE
CONTROL
AND
LOGIC
ADDRESS LATCH
SCK
I/O BUFFERS
AND LATCHES
WP
Y-DECODER
Y-GATING
X-DECODER
FLASH
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into physical sectors of various sizes, of which each sector can be individually protected from program
and erase operations. The sizes of the physical sectors are optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions. The Figure 4-1 on page 4 illustrates the breakdown of each erase level as well as the
breakdown of each physical sector.
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3600A–DFLASH–11/05
Memory Architecture Diagram
Block Erase Detail
64KB
32KB
Block Erase
Block Erase
(D8h Command) (52h Command)
32KB
(Sector 18)
8KB
(Sector 17)
8KB
(Sector 16)
32KB
64KB
32KB
16KB
(Sector 15)
32KB
64KB
(Sector 14)
64KB
•••
•••
•••
32KB
32KB
64KB
(Sector 0)
64KB
32KB
4
4KB
Block Erase
(20h Command)
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
Block Address
Range
0FFFFFh
0FEFFFh
0FDFFFh
0FCFFFh
0FBFFFh
0FAFFFh
0F9FFFh
0F8FFFh
0F7FFFh
0F6FFFh
0F5FFFh
0F4FFFh
0F3FFFh
0F2FFFh
0F1FFFh
0F0FFFh
0EFFFFh
0EEFFFh
0EDFFFh
0ECFFFh
0EBFFFh
0EAFFFh
0E9FFFh
0E8FFFh
0E7FFFh
0E6FFFh
0E5FFFh
0E4FFFh
0E3FFFh
0E2FFFh
0E1FFFh
0E0FFFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0FF000h
0FE000h
0FD000h
0FC000h
0FB000h
0FA000h
0F9000h
0F8000h
0F7000h
0F6000h
0F5000h
0F4000h
0F3000h
0F2000h
0F1000h
0F0000h
0EF000h
0EE000h
0ED000h
0EC000h
0EB000h
0EA000h
0E9000h
0E8000h
0E7000h
0E6000h
0E5000h
0E4000h
0E3000h
0E2000h
0E1000h
0E0000h
00FFFFh
00EFFFh
00DFFFh
00CFFFh
00BFFFh
00AFFFh
009FFFh
008FFFh
007FFFh
006FFFh
005FFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00F000h
00E000h
00D000h
00C000h
00B000h
00A000h
009000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
•••
Internal Sectoring for
Sector Protection
Function
Page Program Detail
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
Page Address
Range
0FFFFFh
0FFEFFh
0FFDFFh
0FFCFFh
0FFBFFh
0FFAFFh
0FF9FFh
0FF8FFh
0FF7FFh
0FF6FFh
0FF5FFh
0FF4FFh
0FF3FFh
0FF2FFh
0FF1FFh
0FF0FFh
0FEFFFh
0FEEFFh
0FEDFFh
0FECFFh
0FEBFFh
0FEAFFh
0FE9FFh
0FE8FFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0FFF00h
0FFE00h
0FFD00h
0FFC00h
0FFB00h
0FFA00h
0FF900h
0FF800h
0FF700h
0FF600h
0FF500h
0FF400h
0FF300h
0FF200h
0FF100h
0FF000h
0FEF00h
0FEE00h
0FED00h
0FEC00h
0FEB00h
0FEA00h
0FE900h
0FE800h
0017FFh
0016FFh
0015FFh
0014FFh
0013FFh
0012FFh
0011FFh
0010FFh
000FFFh
000EFFh
000DFFh
000CFFh
000BFFh
000AFFh
0009FFh
0008FFh
0007FFh
0006FFh
0005FFh
0004FFh
0003FFh
0002FFh
0001FFh
0000FFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
001700h
001600h
001500h
001400h
001300h
001200h
001100h
001000h
000F00h
000E00h
000D00h
000C00h
000B00h
000A00h
000900h
000800h
000700h
000600h
000500h
000400h
000300h
000200h
000100h
000000h
•••
Figure 4-1.
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
5. Device Operation
The AT26DF081A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT26DF081A via
the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial
Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT26DF081A supports the two most common modes, SPI
modes 0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal
when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always
output on the falling edge of SCK.
Figure 5-1.
SPI Mode 0 and 3
CS
SCK
SI
MSB
SO
LSB
MSB
LSB
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS
pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.
Following the opcode, instruction dependent information such as address and data bytes would
then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with
the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT26DF081A will be ignored by the device and no operation will
be started. The device will continue to ignore any data presented on the SI pin until the start of
the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is
deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing
address bits A23 - A0. Since the upper address limit of the AT26DF081A memory array is
0FFFFFh, address bits A23 - A20 are always ignored by the device.
5
3600A–DFLASH–11/05
Table 6-1.
Command Listing
Command
Opcode
Address Bytes
Dummy Bytes
Data Bytes
Read Commands
Read Array
0Bh
0000 1011
3
1
1+
Read Array (Low Frequency)
03h
0000 0011
3
0
1+
Block Erase (4 Kbytes)
20h
0010 0000
3
0
0
Block Erase (32 Kbytes)
52h
0101 0010
3
0
0
Block Erase (64 Kbytes)
D8h
1101 1000
3
0
0
60h
0110 0000
0
0
0
C7h
1100 0111
0
0
0
02h
0000 0010
3
0
1+
ADh
1010 1101
3, 0(1)
0
1
AFh
1010 1111
3, 0
(1)
0
1
Write Enable
06h
0000 0110
0
0
0
Write Disable
04h
0000 0100
0
0
0
Protect Sector
36h
0011 0110
3
0
0
Unprotect Sector
39h
0011 1001
3
0
0
Read Sector Protection Registers
3Ch
0011 1100
3
0
1+
Read Status Register
05h
0000 0101
0
0
1+
Write Status Register
01h
0000 0001
0
0
1
Read Manufacturer and Device ID
9Fh
1001 1111
0
0
1 to 4
Deep Power-down
B9h
1011 1001
0
0
0
Resume from Deep Power-down
ABh
1010 1011
0
0
0
Program and Erase Commands
Chip Erase
Byte/Page Program (1 to 256 Bytes)
Sequential Program Mode
Protection Commands
Status Register Commands
Miscellaneous Commands
Note:
6
1. Three address bytes are only required for the first operation to designate the address to start programming at. Afterwards,
the internal address counter automatically increments, so subsequent Sequential Program Mode operations only require
clocking in of the opcode and the data byte until the Sequential Program Mode has been exited.
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
7. Read Commands
7.1
Read Array
The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the SCK signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every
clock cycle.
Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode
depends on the maximum SCK frequency that will be used to read data from the device. The
0Bh opcode can be used at any SCK frequency up to the maximum specified by fSCK. The 03h
opcode can be used for lower frequency read operations up to the maximum specified by fRDLF.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate
opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the
three address bytes must be clocked in to specify the starting address location of the first byte to
read within the memory array. If the 0Bh opcode is used, then one don't care byte must also be
clocked in after the three address bytes.
After the three address bytes (and the one don't care byte if using opcode 0Bh) have been
clocked in, additional clock cycles will result in serial data being output on the SO pin. The data
is always output with the MSB of a byte first. When the last byte (0FFFFFh) of the memory array
has been read, the device will continue reading back at the beginning of the array (000000h).
No delays will be incurred when wrapping around from the end of the array to the beginning
of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte
of data be read.
Figure 7-1.
Read Array – 0Bh Opcode
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OPCODE
SI
0
0
0
0
1
ADDRESS BITS A23-A0
0
1
1
MSB
A
A
A
A
A
A
A
DON'T CARE
A
A
MSB
X
X
X
X
X
X
X
X
MSB
DATA BYTE 1
SO
HIGH-IMPEDANCE
D
D
D
D
D
D
MSB
Figure 7-2.
D
D
D
D
MSB
Read Array – 03h Opcode
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE
SI
0
0
0
0
0
ADDRESS BITS A23-A0
0
MSB
1
1
A
A
A
A
A
A
A
A
A
MSB
DATA BYTE 1
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
D
MSB
7
3600A–DFLASH–11/05
8. Program and Erase Commands
8.1
Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of
data to be programmed into previously erased memory locations. An erased memory location is
one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page
Program command can be started, the Write Enable command must have been previously
issued to the device (see “Write Enable” on page 14 command description) to set the Write
Enable Latch (WEL) bit of the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device
followed by the three address bytes denoting the first byte location of the memory array to begin
programming at. After the address bytes have been clocked in, data can then be clocked into the
device and will be stored in an internal buffer.
If the starting memory address denoted by A23 - A0 does not fall on an even 256-byte page
boundary (A7 - A0 are not all 0’s), then special circumstances regarding which memory locations
will be programmed will apply. In this situation, any data that is sent to the device that goes
beyond the end of the page will wrap around back to the beginning of the same page. For example, if the starting address denoted by A23 - A0 is 0000FEh, and three bytes of data are sent to
the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining
bytes in the page (addresses 000001h through 0000FDh) will be unaffected and will not change.
In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes
sent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting address specified by
A23 - A0 and the number of data bytes sent to the device. If less than 256 bytes of data were
sent to the device, then the remaining bytes within the page will not be altered. The programming of the data bytes is internally self-timed and should take place in a time of tPP.
The three address bytes and at least one complete byte of data must be clocked into the device
before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries
(multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by A23 - A0 points to a
memory location within a sector that is in the protected state (see section “Protect Sector” on
page 15), then the Byte/Page Program command will not be executed, and the device will return
to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be
reset back to the logical “0” state if the program cycle aborts due to an incomplete address being
sent, an incomplete byte of data being sent, or because the memory location to be programmed
is protected.
While the device is programming, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled
rather than waiting the tPP time to determine if the data bytes have finished programming. At
some point before the program cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
8
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
The Byte/Page Program mode is the default programming mode after the device powers-up or
resumes from a device reset.
Figure 8-1.
Byte Program
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE
SI
0
0
0
0
0
ADDRESS BITS A23-A0
0
1
0
MSB
A
A
A
A
A
A
A
A
D
MSB
D
D
D
D
D
D
D
MSB
HIGH-IMPEDANCE
SO
Figure 8-2.
A
DATA IN
Page Program
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE
SI
0
0
0
0
0
ADDRESS BITS A23-A0
0
MSB
SO
8.2
1
0
A
MSB
A
A
A
A
A
DATA IN BYTE 1
D
MSB
D
D
D
D
D
D
DATA IN BYTE n
D
D
D
D
D
D
D
D
D
MSB
HIGH-IMPEDANCE
Sequential Program Mode
The Sequential Program Mode improves throughput over the Byte/Page Program command
when the Byte/Page Program command is used to program single bytes only into consecutive
address locations. For example, some systems may be designed to program only a single byte
of information at a time and cannot utilize a buffered Page Program operation due to design
restrictions. In such a case, the system would normally have to perform multiple Byte Program
operations in order to program data into sequential memory locations. This approach can add
considerable system overhead and SPI bus traffic.
The Sequential Programming Mode helps reduce system overhead and bus traffic by incorporating an internal address counter that keeps track of the byte location to program, thereby
eliminating the need to supply an address sequence to the device for every byte to program.
When using the Sequential Program mode, all address locations to be programmed must be in
the erased state. Before the Sequential Program mode can first be entered, the Write Enable
command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
9
3600A–DFLASH–11/05
To start the Sequential Program Mode, the CS pin must first be asserted, and either an opcode
of ADh or AFh must be clocked into the device. For the first program cycle, three address bytes
must be clocked in after the opcode to designate the first byte location to program. After the
address bytes have been clocked in, the byte of data to be programmed can be sent to the
device. Deasserting the CS pin will start the internally self-timed program operation, and the byte
of data will be programmed into the memory location specified by A23 - A0.
After the first byte has been successfully programmed, a second byte can be programmed by
simply reasserting the CS pin, clocking in the ADh or AFh opcode, and then clocking in the next
byte of data. When the CS pin is deasserted, the second byte of data will be programmed into
the next sequential memory location. The process would be repeated for any additional bytes.
There is no need to reissue the Write Enable command once the Sequential Program Mode has
been entered.
When the last desired byte has been programmed into the memory array, the Sequential
Program Mode operation can be terminated by reasserting the CS pin and sending the
Write Disable command to the device to reset the WEL bit in the Status Register back to the
logical “0” state.
If more than one byte of data is ever clocked in during each program cycle, then only the last
byte of data sent on the SI pin will be stored in the internal latches. The programming of each
byte is internally self-timed and should take place in a time of tBP. For each program cycle, a
complete byte of data must be clocked into the device before the CS pin is deasserted, and the
CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation, the byte of data will not be programmed into the memory array,
and the WEL bit in the Status Register will be reset back to the logical “0” state.
If the address initially specified by A23 - A0 points to a memory location within a sector that is in
the protected state, then the Sequential Program Mode command will not be executed, and the
device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will also be reset back to the logical “0” state.
There is no address wrapping when using the Sequential Program Mode. Therefore, when the
last byte (0FFFFFh) of the memory array has been programmed, the device will automatically
exit the Sequential Program mode and reset the WEL bit in the Status Register back to the logical “0” state. In addition, the Sequential Program mode will not automatically skip over protected
sectors; therefore, once the highest unprotected memory location in a programming sequence
has been programmed, the device will automatically exit the Sequential Program mode and
reset the WEL bit in the Status Register. For example, if Sector 1 was protected and Sector 0
was currently being programmed, once the last byte of Sector 0 was programmed, the Sequential Program mode would automatically end. To continue programming with Sector 2, the
Sequential Program mode would have to be restarted by supplying the ADh or AFh opcode, the
three address bytes, and the first byte of Sector 2 to program.
While the device is programming a byte, the Status Register can be read and will indicate that
the device is busy. For faster throughput, it is recommended that the Status Register be polled at
the end of each program cycle rather than waiting the tBP time to determine if the byte has finished programming before starting the next Sequential Program mode cycle.
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
10
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
Figure 8-3.
Sequential Program Mode – Status Register Polling
CS
Status Register Read Seqeuntial Program Mode
Command
Command
Seqeuntial Program Mode
Command
SI
Opcode A23-16
A15-8
A7-0
Data
05h
Opcode
Data
Seqeuntial Program Mode Write Disable
Command
Command
Opcode
05h
Data
04h
05h
First Address to Program
STATUS REGISTER
DATA
STATUS REGISTER
DATA
STATUS REGISTER
DATA
HIGH-IMPEDANCE
SO
Note: Each transition
Figure 8-4.
shown for SI represents one byte (8 bits)
Sequential Program Mode – Waiting Maximum Byte Program Time
CS
tBP
Seqeuntial Program Mode
Command
SI
Opcode A23-16
A15-8
A7-0
Data
tBP
tBP
Seqeuntial Program Mode
Command
Seqeuntial Program Mode
Command
Write Disable
Command
Opcode
Opcode
04h
Data
Data
First Address to Program
HIGH-IMPEDANCE
SO
Note: Each transition
8.3
shown for SI represents one byte (8 bits)
Block Erase
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is
used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h
is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable
command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,
52h or D8h) must be clocked into the device. After the opcode has been clocked in, the three
address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be
clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally selftimed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not
need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11 - A0 will be
ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase,
address bits A14 - A0 will be ignored, and for a 64-Kbyte erase, address bits A15 - A0 will be
ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation and no erase operation will be performed.
11
3600A–DFLASH–11/05
If the address specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Block Erase command will not be executed, and the device will return to
the idle state once the CS pin has been deasserted. In addition, with the larger Block Erase
sizes of 32K and 64 Kbytes, more than one physical sector may be erased (e.g. sectors 18
through 15) at one time. Therefore, in order to erase a larger block that may span more than one
sector, all of the sectors in the span must be in the unprotected state. If one of the physical sectors within the span is in the protected state, then the device will ignore the Block Erase
command and will return to the idle state once the CS pin is deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle
aborts due to an incomplete address being sent or because a memory location within the region
to be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erasing algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the
Status Register.
Figure 8-5.
Block Erase
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
OPCODE
SI
C
C
C
C
C
C
MSB
SO
12
ADDRESS BITS A23-A0
C
C
A
A
A
A
A
A
A
A
A
A
A
A
MSB
HIGH-IMPEDANCE
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
8.4
Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command.
Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in
device functionality when utilizing the two opcodes, so they can be used interchangeably. To
perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.
Since the entire memory array is to be erased, no address bytes need to be clocked into the
device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted,
the device will erase the entire memory array. The erasing of the device is internally self-timed
and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the
CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no
erase will be performed. In addition, if any sector of the memory array is in the protected state,
then the Chip Erase command will not be executed, and the device will return to the idle state
once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to
the logical “0” state if a sector is in the protected state.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erasing algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the
Status Register.
Figure 8-6.
Chip Erase
CS
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
C
C
C
C
C
C
C
C
MSB
SO
HIGH-IMPEDANCE
13
3600A–DFLASH–11/05
9. Protection Commands and Features
9.1
Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector,
Unprotect Sector, or Write Status Register command can be executed. This makes the issuance
of these commands a two step process, thereby reducing the chances of a command being
accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the
issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be set to a logical “1”. The complete opcode must be clocked into the
device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of
the WEL bit will not change.
Figure 9-1.
Write Enable
CS
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
0
0
0
0
0
1
1
0
MSB
SO
9.2
HIGH-IMPEDANCE
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical “0” state. With the WEL bit reset, all program, erase, Protect Sector, Unprotect
Sector, and Write Status Register commands will not be executed. The Write Disable command
is also used to exit the Sequential Program Mode. Other conditions can also cause the WEL bit
to be reset; for more details, refer to the WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the
device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of
the WEL bit will not change.
14
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
Figure 9-2.
Write Disable
CS
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
0
0
0
0
0
1
0
0
MSB
SO
9.3
HIGH-IMPEDANCE
Protect Sector
Every physical sector of the device has a corresponding single-bit Sector Protection Register
that is used to control the software protection of a sector. Upon device power-up or after a
device reset, each Sector Protection Register will default to the logical “1” state indicating that all
sectors are protected and cannot be programmed or erased.
Issuing the Protect Sector command to a particular sector address will set the corresponding
Sector Protection Register to the logical “1” state. The following table outlines the two states of
the Sector Protection Registers.
Table 9-1.
Value
Sector Protection Register Values
Sector Protection Status
0
Sector is unprotected and can be programmed and erased.
1
Sector is protected and cannot be programmed or erased. This is the default state.
Before the Protect Sector command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Protect
Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into
the device followed by three address bytes designating any address within the sector to be
locked. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector addressed by
A23 - A0 will be set to the logical “1” state, and the sector itself will then be protected from
program and erase operations. In addition, the WEL bit in the Status Register will be reset back
to the logical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation, the state of the Sector Protection Register will be
unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector
Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status Register (please refer to the Status Register description
for more details). If the Sector Protection Registers are locked, then any attempts to issue the
Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted.
15
3600A–DFLASH–11/05
Figure 9-3.
Protect Sector
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
OPCODE
SI
0
0
1
1
0
ADDRESS BITS A23-A0
1
1
0
MSB
SO
9.4
A
A
A
A
A
A
A
A
A
A
A
A
MSB
HIGH-IMPEDANCE
Unprotect Sector
Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector Protection Register to the logical “0” state (see Table 9-1 for Sector Protection
Register values). Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector.
Before the Unprotect Sector command can be issued, the Write Enable command must have
been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the
Unprotect Sector command, the CS pin must first be asserted and the opcode of 39h must be
clocked into the device. After the opcode has been clocked in, the three address bytes designating any address within the sector to be unlocked must be clocked in. Any additional data clocked
into the device after the address bytes will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the sector addressed by A23 - A0 will be reset to the
logical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Status
Register will be reset back to the logical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation, the state of the Sector Protection Register will be
unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection
Registers Locked) bit of the Status Register (please refer to the Status Register description for
more details). If the Sector Protection Registers are locked, then any attempts to issue the
Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status
Register back to a logical “0” and return to the idle state once the CS pin has been deasserted.
Figure 9-4.
Unprotect Sector
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
OPCODE
SI
0
0
1
1
1
ADDRESS BITS A23-A0
0
MSB
SO
16
0
1
A
A
A
A
A
A
A
A
A
A
A
A
MSB
HIGH-IMPEDANCE
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
9.5
Read Sector Protection Registers
The Sector Protection Registers can be read to determine the current software protection status
of each sector. Reading the Sector Protection Registers, however, will not determine the status
of the WP pin.
To read the Sector Protection Register for a particular sector, the CS pin must first be asserted
and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address
bytes designating any address within the sector must be clocked in. After the last address byte
has been clocked in, the device will begin outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote
the value of the appropriate Sector Protection Register.
Table 9-2.
Read Sector Protection Register – Output Data
Output Data
Sector Protection Register Value
00h
Sector Protection Register value is 0 (sector is unprotected).
FFh
Sector Protection Register value is 1 (sector is protected).
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
In addition to reading the individual Sector Protection Registers, the Software Protection Status
(SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are
software protected (refer to the “Status Register Commands” on page 19 for more details).
Figure 9-5.
Read Sector Protection Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE
SI
0
0
1
1
1
ADDRESS BITS A23-A0
1
MSB
0
0
A
A
A
A
A
A
A
A
A
MSB
DATA BYTE
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
D
MSB
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3600A–DFLASH–11/05
9.6
Protected States and the Write Protect (WP) Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection
Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism
of the device. For hardware locking to be active, two conditions must be met-the WP pin must be
asserted and the SPRL bit must be in the logical “1” state.
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit
itself is also locked. Therefore, sectors that are protected will be locked in the protected state,
and sectors that are unprotected will be locked in the unprotected state. These states cannot be
changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and
Write Status Register commands will be ignored. In order to modify the protection status of a
sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be
reset back to the logical “0” state.
If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”,
the only way to reset the bit back to the logical “0” state is to power-cycle or reset the device.
This allows a system to power-up with all sectors software protected but not hardware locked.
Therefore, sectors can be unprotected and protected as needed and then hardware locked at a
later time by simply setting the SPRL bit in the Status Register.
When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit
in the Status Register can still be set to a logical “1” to lock the Sector Protection Registers. This
provides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector commands from being processed.
Tables 9-3 and 9-4 detail the various protection and locking states of the device.
Table 9-3.
Software Protection
WP
Sector Protection Register
n(1)
Sector
n(1)
0
Unprotected
1
Protected
X
(Don't Care)
Note:
1. “n” represents a sector number
Table 9-4.
18
Hardware and Software Locking
WP
SPRL
0
0
0
1
1
0
1
1
Locking
Hardware
Locked
Software
Locked
SPRL
Sector Protection Registers
Can be modified from 0 to 1
Unlocked and modifiable using
the Protect and Unprotect Sector
commands
Locked
Locked in current state. Protect
and Unprotect Sector commands
will be ignored.
Can be modified from 0 to 1
Unlocked and modifiable using the
Protect and Unprotect Sector
commands
Can be modified from 1 to 0
Locked in current state. Protect and
Unprotect Sector commands will be
ignored.
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
10. Status Register Commands
10.1
Read Status Register
The Status Register can be read to determine the device's ready/busy status, as well as the status of many other functions such as Hardware Locking and Software Protection. The Status
Register can be read at any time, including during an internally self-timed program or erase
operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be
clocked into the device. After the last bit of the opcode has been clocked in, the device will begin
outputting Status Register data on the SO pin during every subsequent clock cycle. After the last
bit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself starting
again with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. The
data in the Status Register is constantly being updated, so each repeating sequence will output
new data.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin
into a high-impedance state. The CS pin can be deasserted at any time and does not require
that a full byte of data be read.
Table 10-1.
Bit
Status Register Format
(1)
7
6
5
4
3:2
1
0
Notes:
Name
SPRL
SPM
EPE
WPP
SWP
WEL
RDY/BSY
Sector Protection Registers Locked
Sequential Program Mode Status
Erase/Program Error
Write Protect (WP) Pin Status
Software Protection Status
Write Enable Latch Status
Ready/Busy Status
Type(2)
Description
0
Sector Protection Registers are unlocked (default).
1
Sector Protection Registers are locked.
0
Byte/Page Programming Mode (default).
1
Sequential Programming Mode entered.
0
Erase or program operation was successful (default).
1
Erase or program error detected.
0
WP is asserted.
1
WP is deasserted.
00
All sectors are software unprotected.
01
Some sectors are software protected. Read Sector
Protection Registers.
10
Reserved for future use.
11
All sectors are software protected (default).
0
Device is not write enabled (default).
1
Device is write enabled.
0
Device is ready.
1
Device is busy with an internal operation.
R/W
R
R
R
R
R
R
1. Bit 7 of the Status Register is the only bit that can be user modified.
2. R/W = Readable and writable
R = Readable only
19
3600A–DFLASH–11/05
10.1.1
SPRL Bit
The SPRL bit is used to control whether the Sector Protection Registers can be modified or not.
When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect Sector and Unprotect Sector commands (the device will ignore
these commands). Any sectors that are presently protected will remain protected, and any sectors that are presently unprotected will remain unprotected.
When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and
can be modified (the Protect Sector and Unprotect Sector commands will be processed as normal). The SPRL bit defaults to the logical “0” state after a power-up or a device reset.
The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin
is asserted, then the SPRL bit may only be changed from a logical “0” (Sector Protection Registers are unlocked) to a logical “1” (Sector Protection Registers are locked). In order to reset the
SPRL bit back to a logical “0” using the Write Status Register command, the WP pin will have to
first be deasserted.
The SPRL bit is the only bit of the Status Register than can be user modified via the Write Status
Register command.
10.1.2
SPM Bit
The SPM bit indicates whether the device is in the Byte/Page Program mode or the Sequential
Program Mode. The default state after power-up or device reset is the Byte/Page Program
mode.
10.1.3
EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully or
not. If at least one byte during the erase or program operation did not erase or program properly,
then the EPE bit will be set to the logical “1” state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an attempt to erase or program a protected region
or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updated
after every erase and program operation.
10.1.4
WPP Bit
The WPP bit can be read to determine if the WP pin has been asserted or not.
10.1.5
SWP Bits
The SWP bits provide feedback on the software protection status for the device. There are three
possible combinations of the SWP bits that indicate whether none, some, or all of the sectors
have been protected using the Protect Sector command. If the SWP bits indicate that some of
the sectors have been protected, then the individual Sector Protection Registers can be read
with the Read Sector Protection Registers command to determine which sectors are in fact
protected.
20
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
10.1.6
WEL Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is
in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect
Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a
device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automatically under the following conditions:
• Write Disable operation completes successfully
• Write Status Register operation completes successfully or aborts
• Protect Sector operation completes successfully or aborts
• Unprotect Sector operation completes successfully or aborts
• Byte/Page Program operation completes successfully or aborts
• Sequential Program Mode reaches highest unprotected memory location
• Sequential Program Mode reaches the end of the memory array
• Sequential Program Mode aborts
• Block Erase operation completes successfully or aborts
• Chip Erase operation completes successfully or aborts
• Hold condition aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts
due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is
deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire
opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command must have been clocked into the device.
10.1.7
RDY/BSY Bit
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program
or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase
cycle, new Status Register data must be continually clocked out of the device until the state of
the RDY/BSY bit changes from a logical “1” to a logical “0”.
Figure 10-1. Read Status Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
OPCODE
SI
0
0
0
0
0
1
0
1
MSB
STATUS REGISTER DATA
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
STATUS REGISTER DATA
D
MSB
D
D
D
D
D
D
D
D
D
MSB
21
3600A–DFLASH–11/05
10.2
Write Status Register
The Write Status Register command is used to modify the SPRL bit of the Status Register.
Before the Write Status Register command can be issued, the Write Enable command must
have been previously issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register command, the CS pin must first be asserted and the opcode
of 01h must be clocked into the device. After the opcode has been clocked in, one byte of data
comprised of the SPRL bit value and seven don't care bits must be clocked in. Any additional
data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the SPRL
bit in the Status Register will be modified, and the WEL bit in the Status Register will be reset
back to a logical “0”. The complete one byte of data must be clocked into the device before the
CS pin is deasserted; otherwise, the device will abort the operation, the state of the SPRL bit will
not change, and the WEL bit in the Status Register will be reset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made
to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register
command will be ignored, and the WEL bit in the Status Register will be reset back to the logical
“0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
Figure 10-2. Write Status Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
OPCODE
SI
0
0
0
0
0
STATUS REGISTER IN
0
MSB
SO
22
0
1
D
X
X
X
X
X
X
X
MSB
HIGH-IMPEDANCE
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
11. Other Commands and Functions
11.1
Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically query
and identify the device while it is in system. The identification method and the command opcode
comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI
Compatible Serial Interface Memory Devices”. The type of information that can be read from the
device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh
must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte
that will be output will be the Manufacturer ID followed by two bytes of Device ID information.
The fourth byte output will be the Extended Device Information String Length, which will be 00h
indicating that no Extended Device Information follows. After the Extended Device Information
String Length byte is output, the SO pin will go into a high-impedance state; therefore, additional
clock cycles will have no affect on the SO pin and no data will be output. As indicated in the
JEDEC standard, reading the Extended Device Information String Length and any subsequent
data is optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put
the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not
require that a full byte of data be read.
Table 11-1.
Manufacturer and Device ID Information
Byte No.
Table 11-2.
Data Type
Value
1
Manufacturer ID
1Fh
2
Device ID (Part 1)
45h
3
Device ID (Part 2)
01h
4
Extended Device Information String Length
00h
Manufacturer and Device ID Details
Data Type
Bit 7
Bit 6
Bit 5
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
Hex
Value
Details
JEDEC Assigned Code
Manufacturer ID
0
0
0
1
1
Family Code
1
1
0
0
MLC Code
0
1
0
0001 1111 (1Fh for Atmel)
45h
Family Code:
Density Code:
010 (AT26DFxxx series)
00101 (8-Mbit)
01h
MLC Code:
000 (1-bit/cell technology)
Product Version: 00001 (First major revision)
Product Version Code
Device ID (Part 2)
0
JEDEC Code:
Density Code
Device ID (Part 1)
0
1Fh
0
0
0
0
0
1
23
3600A–DFLASH–11/05
Figure 11-1. Read Manufacturer and Device ID
CS
0
6
7
8
14 15 16
22 23 24
30 31 32
38
SCK
OPCODE
SI
SO
9Fh
HIGH-IMPEDANCE
Note: Each transition
11.2
1Fh
45h
01h
00h
MANUFACTURER ID
DEVICE ID
BYTE 1
DEVICE ID
BYTE 2
EXTENDED
DEVICE
INFORMATION
STRING LENGTH
shown for SI and SO represents one byte (8 bits)
Deep Power-down
During normal operation, the device will be placed in the standby mode to consume less power
as long as the CS pin remains deasserted and no internal operation is in progress. The Deep
Power-down command offers the ability to place the device into an even lower power consumption state called the Deep Power-down mode.
When the device is in the Deep Power-down mode, all commands including the Read Status
Register command will be ignored with the exception of the Resume from Deep Power-down
command. Since all commands will be ignored, the mode can be used as an extra protection
mechanism against program and erase operations.
Entering the Deep Power-down mode is accomplished by simply asserting the CS pin, clocking
in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the
device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the
Deep Power-down mode within the maximum time of tEDPD.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must
be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort
the operation and return to the standby mode once the CS pin is deasserted. In addition, the
device will default to the standby mode after a power-cycle or a device reset.
The Deep Power-down command will be ignored if an internally self-timed operation such as a
program or erase cycle is in progress. The Deep Power-down command must be reissued after
the internally self-timed operation has been completed in order for the device to enter the Deep
Power-down mode.
24
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
Figure 11-2. Deep Power-down
CS
tEDPD
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
1
0
1
1
1
0
0
1
MSB
SO
HIGH-IMPEDANCE
Active Current
ICC
Standby Mode Current
11.3
Deep Power-Down Mode Current
Resume from Deep Power-down
In order exit the Deep Power-down mode and resume normal device operation, the Resume
from Deep Power-down command must be issued. The Resume from Deep Power-down command is the only command that the device will recognize while in the Deep Power-down mode.
To resume from the Deep Power-down mode, the CS pin must first be asserted and opcode of
ABh must be clocked into the device. Any additional data clocked into the device after the
opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Powerdown mode within the maximum time of tRDPD and return to the standby mode. After the device
has returned to the standby mode, normal command operations such as Read Array can be
resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not
deasserted on an even byte boundary (multiples of eight bits), then the device will abort the
operation and return to the Deep Power-down mode.
Figure 11-3. Resume from Deep Power-down
CS
tRDPD
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
1
0
1
0
1
0
1
1
MSB
SO
HIGH-IMPEDANCE
Active Current
ICC
Deep Power-Down Mode Current
Standby Mode Current
25
3600A–DFLASH–11/05
11.4
Hold
The HOLD pin is used to pause the serial communication with the device without having to stop
or reset the clock sequence. The Hold mode, however, does not have an affect on any internally
self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in
progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue
until it is finished.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated
simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during
the SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK low
pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are
asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin
and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while
in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted
during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the
Hold mode won't end until the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may
have been started will be aborted, and the device will reset the WEL bit in the Status Register
back to the logical “0” state.
Figure 11-4. Hold Mode
CS
SCK
HOLD
Hold
26
Hold
Hold
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
12. Electrical Specifications
12.1
Absolute Maximum Ratings*
Temperature under Bias ............................... -55° C to +125° C
*NOTICE:
Storage Temperature .................................... -65° C to +150° C
All Input Voltages
(including NC Pins)
with Respect to Ground .....................................-0.6V to +4.1V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.5V
12.2
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT26DF081A
Operating Temperature (Case)
Ind.
-40° C to 85° C
VCC Power Supply
12.3
2.7V to 3.6V
DC Characteristics
Symbol
Parameter
Condition
ISB
Standby Current
IDPD
Deep Power-down Current
ICC1
Active Current, Read Operation
Min
Typ
Max
Units
CS, WP, HOLD = VCC,
all inputs at CMOS levels
25
35
µA
CS, WP, HOLD = VCC,
all inputs at CMOS levels
11
15
µA
f = 70 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max
12
16
f = 66 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max
11
15
f = 50 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max
10
14
f = 33 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max
8
12
f = 20 MHz; IOUT = 0 mA;
CS = VIL, VCC = Max
7
10
mA
ICC2
Active Current, Program Operation
CS = VCC, VCC = Max
12
18
mA
ICC3
Active Current, Erase Operation
CS = VCC, VCC = Max
14
20
mA
ILI
Input Leakage Current
VIN = CMOS levels
1
µA
ILO
Output Leakage Current
VOUT = CMOS levels
1
µA
VIL
Input Low Voltage
0.3 x VCC
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6 mA; VCC = Min
VOH
Output High Voltage
IOH = -100 µA
0.7 x VCC
V
0.4
VCC - 0.2V
V
V
27
3600A–DFLASH–11/05
12.4
AC Characteristics
Symbol
Parameter
fSCK
Max
Units
Serial Clock (SCK) Frequency
70
MHz
fRDLF
SCK Frequency for Read Array (Low Frequency - 03h opcode)
33
MHz
tSCKH
SCK High Time
6.4
ns
SCK Low Time
6.4
ns
SCK Rise Time, Peak-to-Peak (Slew Rate)
0.1
V/ns
tSCKF(1)
SCK Fall Time, Peak-to-Peak (Slew Rate)
0.1
V/ns
tCSH
Chip Select High Time
50
ns
tCSLS
Chip Select Low Setup Time (relative to SCK)
5
ns
tCSLH
Chip Select Low Hold Time (relative to SCK)
5
ns
tCSHS
Chip Select High Setup Time (relative to SCK)
5
ns
tCSHH
Chip Select High Hold Time (relative to SCK)
5
ns
tDS
Data In Setup Time
2
ns
tDH
Data In Hold Time
3
ns
tDIS(1)
Output Disable Time
6
ns
tV(2)
Output Valid Time
6
ns
tOH
Output Hold Time
0
ns
tHLS
HOLD Low Setup Time (relative to SCK)
5
ns
tHLH
HOLD Low Hold Time (relative to SCK)
5
ns
tHHS
HOLD High Setup Time (relative to SCK)
5
ns
HOLD High Hold Time (relative to SCK)
5
ns
tSCKL
tSCKR
(1)
tHHH
Min
(1)
HOLD Low to Output High-Z
6
ns
tHHQX(1)
HOLD High to Output Low-Z
6
ns
tHLQZ
tWPS
(1)(3)
Write Protect Setup Time
20
ns
(1)(3)
Write Protect Hold Time
100
ns
tWPH
tSECP
(1)
Sector Protect Time (from Chip Select High)
20
ns
tSECUP(1)
Sector Unprotect Time (from Chip Select High)
20
ns
tEDPD(1)
Chip Select High to Deep Power-down
3
µs
Chip Select High to Standby Mode
3
µs
tRDPD
Notes:
(1)
1. Not 100% tested (value guaranteed by design and characterization).
2. 15 pF load at 70 MHz, 30 pF load at 66 MHz.
3. Only applicable as a constraint for the Write Status Register command when SPRL = 1
28
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
12.5
Program and Erase Characteristics
Symbol
Parameter
tPP
Page Program Time (256 Bytes)
tBP
Byte Program Time
tBLKE
Units
1.5
3.0
ms
µs
0.05
0.2
32 Kbytes
0.35
0.6
64 Kbytes
0.7
1.0
10
14
sec
200
ns
Write Status Register Time
Note:
1. Not 100% tested (value guaranteed by design and characterization).
12.6
Power-up Conditions
Parameter
Min
Minimum VCC to Chip Select Low Time
Max
50
Power-on Reset Voltage
sec
Units
µs
Power-up Device Delay Before Program or Erase Allowed
12.7
Max
4 Kbytes
Chip Erase Time
(1)
Typ
6
Block Erase Time
tCHPE
tWRSR
Min
1.5
10
ms
2.5
V
Input Test Waveforms and Measurement Levels
AC
DRIVING
LEVELS
2.4V
1.5V
0.45V
AC
MEASUREMENT
LEVEL
tR, tF < 2 ns (10% to 90%)
12.8
Output Test Load
DEVICE
UNDER
TEST
30 pF
29
3600A–DFLASH–11/05
13. Waveforms
Figure 13-1. Serial Input Timing
tCSH
CS
tCSLH
tSCKL
tCSLS
tSCKH
tCSHH
tCSHS
SCK
tDS
SI
SO
tDH
MSB
LSB
MSB
HIGH-IMPEDANCE
Figure 13-2. Serial Output Timing
CS
tSCKH
tSCKL
tDIS
SCK
SI
tOH
tV
tV
SO
Figure 13-3. HOLD Timing – Serial Input
CS
SCK
tHHH
tHLS
tHLH
tHHS
HOLD
SI
SO
30
HIGH-IMPEDANCE
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
Figure 13-4. HOLD Timing – Serial Output
CS
SCK
tHHH
tHLS
tHLH
tHHS
HOLD
SI
tHLQZ
tHHQX
SO
Figure 13-5. WP Timing for Write Status Register Command When SPRL = 1
CS
tWPH
tWPS
WP
SCK
SI
0
MSB OF
WRITE STATUS REGISTER
OPCODE
SO
0
0
X
MSB
LSB OF
WRITE STATUS REGISTER
DATA BYTE
MSB OF
NEXT OPCODE
HIGH-IMPEDANCE
31
3600A–DFLASH–11/05
14. Ordering Information
14.1
Green Package Options (Pb/Halide-free/RoHS Compliant)
fSCK (MHz)
Ordering Code
Package
AT26DF081A-SSU
8S1
AT26DF081A-SU
8S2
70
Operation Range
Industrial
(-40° C to 85° C)
Package Type
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2
8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
32
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
15. Packaging Information
15.1
8S1 – EIAJ SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
SYMBOL
MIN
NOM
MAX
A1
0.10
–
0.25
NOTE
D
SIDE VIEW
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
C
33
3600A–DFLASH–11/05
15.2
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
NOM
MAX
NOTE
A
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
∅
0°
8°
e
Notes: 1.
2.
3.
4.
5.
MIN
1.27 BSC
2, 3
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
R
34
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
C
AT26DF081A [Preliminary]
3600A–DFLASH–11/05
AT26DF081A [Preliminary]
16. Revision History
Version No./Release Date
History
Revision A – November 2005
•
Initial Release
35
3600A–DFLASH–11/05
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