ETC ADC-207MM 7- bit 20mhz cmos flash a/d converter Datasheet

®
ADC-207
®
7-Bit, 20MHz, CMOS
Flash A/D Converters
IN N O VA T IO N a n d E X C E L L E N C E
FEATURES
•
•
•
•
•
•
•
•
•
7-bit flash A/D converter
20MHz sampling rate
Low power (250mW)
Single +5V supply
1.2 micron CMOS technology
7-bit latched 3-state output with overflow bit
Surface-mount versions
High-reliability version
No missing codes
GENERAL DESCRIPTION
The ADC-207 has 128 comparators which are auto-balanced
on every conversion to cancel out any offsets due to
temperature and/or dynamic effects. The resistor ladder has a
midpoint tap for use with an external voltage source to improve
integral linearity beyond 7 bits. The ADC-207 also provides the
user with 3-state outputs for easy interfacing to other
components.
The ADC-207 is the industry’s first 7-bit flash converter using an
advanced high-speed VLSI 1.2 micron CMOS process. This
process offers some very distinctive advantages over other
processes, making the ADC-207 unique. The smaller
geometrics of the process achieve high speed, better linearity
and superior temperature performance.
Since the ADC-207 is a CMOS device, it also has very low
power consumption (250mW). The device draws power from
a single +5V supply and is conservatively rated for 20MHz
operation. The ADC-207 allows using sampling apertures as
small as 12ns, making it more closely approach an ideal
sampler. The small sampling apertures also let the device
operate at greater than 20MHz.
∅2
INPUT/OUTPUT
CONNECTIONS
∅2
∅1
∅1
ANALOG INPUT 4
There are six models of the ADC-207 covering two operating
temperature ranges, 0 to +70°C and –55 to +125°C. Two highreliability "QL" models are also available.
CLOCK
GENERATOR
1 CLOCK INPUT
R/2
D Q
+REFERENCE 6
+5V SUPPLY 18
+VDD
R
10 OVERFLOW
D
G
DIP
PINS
FUNCTION
LCC
PINS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLOCK INPUT
DIGITAL GROUND
–REFERENCE
ANALOG INPUT
MIDPOINT
+REFERENCE
ANALOG GROUND
CS1
CS2
OVERFLOW
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7 (LSB)
+5V SUPPLY
1
4
5
6
7
8
9
11
12
13
14
16
17
19
20
21
23
24
G Q
D Q
DIGITAL GROUND 2
R
D
G Q
ANALOG GROUND 7
D Q
128-TO-7
ENCODER
R/2
12 BIT 2
G
D Q
RANGE MIDPOINT 5
11 BIT 1 (MSB)
G
13 BIT 3
D
G
R/2
G Q
D Q
14 BIT 4
G
R
D Q
D
R
15 BIT 5
G
G Q
D Q
D
G
G Q
D Q
–REFERENCE 3
G
CS1 8
16 BIT 6
17 BIT 7 (LSB)
CS2 9
Figure 1. ADC-207 Functional Block Diagram (DIP Pinout)
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) • Tel: (508) 339-3000 Fax: (508) 339-6356 • For immediate assistance (800) 233-2765
®
®
ADC-207
ABSOLUTE MAXIMUM RATINGS
PHYSICAL/ENVIRONMENTAL
PARAMETERS
Power Supply Voltage (+VDD)
Digital Inputs
Analog Input
Reference Inputs
Digital Outputs
(short circuit protected to ground)
Lead Temperature (10 sec. max.)
LIMITS
UNITS
–0.5 to +7
–0.5 to +5.5
–0.5 to (+VDD +0.5)
–0.5 to +VDD
–0.5 to +5.5
Volts
Volts
Volts
Volts
Volts
+300
°C
PARAMETERS
Input Type
Input Range (dc-20MHz)
Input Impedance
Input Capacitance (Full Range)
TYP.
MAX.
UNITS
Single-ended, non-isolated
0
—
+5
—
1000
—
—
10
—
Volts
Ohms
pF
+3.2
—
—
—
—
—
±1
±1
—
+0.8
±5
±5
Volts
Volts
microamps
microamps
12
225
—
330
—
—
ns
Ohms
—
—
—
+70
+125
+150
°C
°C
°C
18-pin ceramic DIP
24-pin ceramic LCC
3. Clock Pulse Width – To improve performance at Nyquist
bandwidths, the clock duty cycle can be adjusted so that the
low portion of the clock pulse is 12ns wide. The smaller
aperture allows the ADC-207 to closely resemble an ideal
sampler. See Figure 4.
20
25
—
MHz
—
—
—
—
—
–40
3
1.5
8
50
—
—
—
—
—
dB
%
degrees
ns
ps
0
–55
—
—
—
—
—
—
±0.8
±0.8
±0.3
±0.4
±0.02
+70
+125
±1
±1
±0.6
±0.6
—
°C
°C
LSB
LSB
LSB
LSB
%FSR/%Vs
7
Straight binary
—
—
Bits
4. At sampling rates less than 100kHz, there may be some
degradation in offset and differential nonlinearity.
Performance may be improved by increasing the clock duty
cycle (decreasing the time spent in the sample mode).
CAUTION
Since the ADC-207 is a CMOS device, normal precautions
against static electricity should be taken. Use ground straps,
grounded mats, etc. The Absolute Maximum Ratings of the
device MUST NOT BE EXCEEDED as irrevocable damage to
the ADC-207 will occur.
DIGITAL OUTPUTS
Data Coding
Data Output Resolution
Logic Levels
Logic "1"
Logic "0" (at 1.6mA)
Logic Loading "1"
Logic Loading "0"
Output Data Valid Delay
(From Rising Edge)
0
–55
–65
2. Reference Ladder – Adjusting the voltage at +REFERENCE
adjusts the gain of the ADC-207. Adjusting the voltage at –
REFERENCE adjusts the offset or zero of the ADC-207.
The midpoint pin is usually bypassed to ground through a
0.1µF capacitor, although it can be tied to a precision
voltage halfway between +REFERENCE and
–REFERENCE. This would improve integral linearity
beyond 7 bits.
PERFORMANCE
Conversion Rate ➀
Harmonic Distortion ➁
(8MHz 2nd Order Harmonic)
Differential Gain ➂
Differential Phase ➂
Aperture Delay
Aperture Jitter
No Missing Codes
LC/MC grade
LM/MM grade
Integral Linearity ➃
Over Temperature Range
Differential Nonlinearity
Over Temperature Range
Power Supply Rejection
UNITS
1. Input Buffer Amplifier – Since the ADC-207 has a switched
capacitor type input, the input impedance of the 207 is
dependent on the clock frequency. At relatively slow
conversion rates, a general purpose type input buffer can be
used; at high conversion rates DATEL recommends either
the HA-5033 or Elantec 2003. See Figure 2 for typical
connections.
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Sample Pulse Width
(During Sampling Portion of Clock)
Reference Ladder Resistance
MAX.
TECHNICAL NOTES
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V,
–REFERENCE = ground, unless noted)
MIN.
TYP.
Operating Temp. Range, Case:
LC/MC Versions
MM/LM/QL Versions
Storage Temp. Range
Package Type
DIP
LCC
FUNCTIONAL SPECIFICATIONS
ANALOG INPUT
MIN.
+2.4
—
–4
+4
+4.5
—
—
—
—
+0.4
—
—
Volts
Volts
mA
mA
—
15
25
ns
+5V
20MHz
CLOCK
+15
+5V
+
0.1µF
1
2
12
POWER REQUIREMENTS
+3.0
—
—
+5.0
+50
250
+5.5
+70
385
3
11
5
HA-5033
Power Supply Range (+VDD)
Power Supply Current
Power Dissipation
4.7µF
+
0.01µF
47µF
10 Ω
4
CLOCK
B7
–REFERENCE
B6
VIN
B5
MID
B4
+REFERENCE
B3
ANALOG GND
B2
CS1
B1
CS2
OF
5
Volts
mA
mW
10
6
0.1µF
Footnotes:
➀ At full power input and chip selects enabled.
➁ At 4MHz input and 20MHz clock.
➂ For 10-step, 40 IRE NTSC ramp test.
➃ Adjustable using reference ladder midpoint tap. See ADC-207 Operation.
+
17
16
15
8
9
0.1µF
18
B7 (LSB)
B6
B5
14
7
47µF
+VDD
DIGITAL GND
13
12
B4
B3
B2
11
B1 (MSB)
10
OF
–15
Figure 2. Typical Connections for Using the ADC-207
2
®
®
ADC-207
OUTPUT CODING
(+REFERENCE = +5.12V, –REFERENCE = ground, MIDPOINT = no connection)
NOTE:
TIMING DIAGRAM
The reference should be held to ±0.1% accuracy or
better. Do not use the +5V power supply as a
reference input without precision regulation and high
frequency decoupling.
∅2
∅1
AUTO
ZERO
CLOCK
Values shown here are for a +5.12V reference. Scale other
references proportionally. Calibration equipment should test for
code changes at the midpoints between these center values
shown in Table 1. For example, at the half-scale major carry,
set the input to 2.54V and adjust the reference until the code
flickers equally between 63 and 64. Note also that the
weighting for the comparator resistor network leaves the first
and last thresholds within 1/2LSB of the end points to adjust
the code transition to the proper midpoint values.
SAMPLE
N
∅1
∅2
∅1
∅2
AUTO
ZERO
SAMPLE
N+1
AUTO
ZERO
SAMPLE
N+2
OUTPUT
DATA
N DATA
25ns max.
N+1 DATA
25ns max.
Table 1. ADC-207 Output Coding
Analog Input
(Center Value)
Code
Overflow
0.00V
+0.04V
+1.28V
+2.52V
+2.56V
+2.60V
+3.84V
+5.08V
+5.12V
Zero
+1LSB
+1/4FS
+1/2FS – 1LSB
+1/2FS
+1/2FS + 1LSB
+3/4FS
+FS
Overflow
0
0
0
0
0
0
0
0
1
1
2
MSB
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
3
0
0
0
1
0
0
0
1
1
4
5
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
6
0
0
0
1
0
0
0
1
1
7
LSB
Decimal
Hexadecimal
(Incl. 0V)
0
1
0
1
0
1
0
1
1
0
1
32
63
64
65
96
127
255*
00
01
20
3F
40
41
60
7F
FF
*Note that the overflow code does not clear the data bits.
ADC-207 OPERATION
The ADC-207 uses a switched capacitor scheme in which
there is an auto-zero phase and a sampling phase. See
Figure 1 and Timing Diagram. The ADC-207 uses a single
clock input. When the clock is at a high state (logic 1), the
ADC-207 is in the auto-zero phase (Ø1). When the clock is at
a low state (logic 0), the ADC-207 is in the sampling phase
(Ø2). During phase 1, the 128 comparator outputs are shorted
to their inputs through CMOS switches. This serves the
purpose of bringing the inputs and outputs to the transition
levels of the respective comparators. The inputs to the
comparators are also connected to 128 sampling capacitors.
The other end of the 128 capacitors are also shorted to 128
taps of a resistor ladder, via CMOS switches. Therefore, during
phase 1 the sampling capacitors are charged to the differential
voltage between a resistor tap and its respective comparator
transition voltage.
Continuous conversion requires one cycle/sample (one positive
pulse and one negative pulse). The 3-state buffer has two
enable lines, CS1 and CS2. Table 2 shows the truth table for
chip select signals. CS1 has the function of enabling/disabling
bits 1 through 7. CS2 has the function of enabling/disabling
bits 1 through 7 and the overflow bit. Also, a full-scale input
produces all ones, including the overflow bit at the output. The
ADC-207 has an adjustable resistor ladder string. The top end,
idle point, and bottom end are brought out for use with
applications circuits.
These pins are called +REFERENCE, MIDPOINT and
–REFERENCE, respectively. In typical operation
+REFERENCE is tied to +5V, –REFERENCE is tied to ground,
and MIDPOINT is bypassed to ground. Such a configuration
results in a 0 to +5V input voltage range. The MIDPOINT pin
can also be tied to a +2.5V source to further improve integral
linearity. This is usually not necessary unless better than 7-bit
linearity is needed.
This eliminates offset differences between comparators and
yields better temperature performance. During phase 2 (Ø2) the
input voltage is applied to the 128 capacitors, via CMOS
switches. This forces the comparators to trip either high or low.
Since the comparators during phase 1 were sitting at their
transition point, they can trip very quickly to the correct state.
Also during phase 2, the outputs of the comparators are loaded
into internal latches which in turn feed a128-to-7 encoder. When
going back into phase 1, the output of the encoder is loaded into
an output latch. This latch then feeds the 3-state output buffer.
Table 2. Chip Select Truth Table
This means that the ADC-207 is of pipeline design. To do a
single conversion, the ADC-207 requires a positive pulse
followed by a negative pulse followed by a positive pulse.
CS1
CS2
Bits 1-7
0
1
0
1
0
0
1
1
3-State Mode
3-State Mode
Data Outputed
3-State Mode
NOTE: Reduce the sample time (sample pulse)
3
Overflow Bit
3-State Mode
3-State Mode
Data Outputed
Data Outputed
®
®
ADC-207
9
8
13
12
11
CLOCK OUT
CLOCK IN
4
20k
6
1
5
2
3
0.01µF
10pF
GROUND
+5 VOLTS
to 12ns to improve performance above
20MHz. Such a configuration will closely
resemble an ideal sampler.
Figure 3. Optional Pulse Shaping Circuit
USING TWO ADC-207’S FOR 8-BIT RESOLUTION
BEAT FREQUENCY AND ENVELOPE TESTS
Two ADC-207’s (A and B) are cascadable for applications
requiring 8-bit resolution. The device A provides a typical 7-bit
output. The OVERFLOW signal of device A turns off device A
and turns on the device B. The OVERFLOW signal of device A
is also used as MSB for 8-bit operation. The device B provides
the other seven bits from the input signal. Figure 4 shows the
circuit connections for the application.
Figure 5 shows an actual ADC-207 plot of the Beat Frequency
Test. This test uses a 20MHz clock input to the ADC-207 with
a 20.002MHz full-scale sine wave input. Although the
converter would not normally be used in this mode because
the input frequency violates Nyquist criteria for full recovery of
signal information, the test is an excellent demonstration of the
ADC-207’s high-frequency performance.
OVERFLOW
+5V
18
+5.12
REFERENCE
IN
10
TURN
BIT 1 (MSB)
6
8
4
OPTIONAL
MIDSCALE
ADJUST
1
9
+VDD
+REFERENCE
OF
B1
CS1
B2
B3
ANALOG INPUT
B4
CLOCK
B5
B6
CS2
B7
3
DIG GND
–REFERENCE
10
11
12
13
14
15
16
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
17
BIT8 (LSB)
2
ANALOG GROUND
CLOCK IN
The effect of the 2kHz frequency difference between the input
and the clock is that the output will be a 2kHz sinusoidal digital
data array which "walks" along the actual input at the 2kHz
beat note frequency. Any inability to follow the 20.002MHz
input will be immediately obvious by plotting the digital data
array. Further arithmetic analysis may be done on the data
array to determine spectral purity, harmonic distortion, etc.
This test is an excellent indication of:
1. Full power input bandwidth of all 128 comparators.
(Any gain loss would show as signal distortion.)
2. Phase response linearity vs. instantaneous signal
magnitude. (Phase problems would show as
improper codes.)
7
3. Comparator slew rate limiting.
7
ANALOG GROUND
ANALOG IN
6
8
1
4
9
+5V
18
3
+REFERENCE
OF
B1
CS1
CLOCK
B2
11
12
13
B3
ANALOG INPUT
B4
CS2
B5
+VDD
10
B6
B7
14
15
16
17
2
–REFERENCE
DIG GND
REFERENCE
GROUND
NOTE: The output data bit numbering is offset
by a bit to the device B’s output.
Figure 4. Using Two ADC-207’s for 8-Bit Operation
Figure 6 shows an actual ADC-207 plot of the Envelope Test.
This test is a variation of the previous test but uses a
10.002MHz sinewave input to give two overlapping cycles
when the data is reconstructed by a D/A converter output to an
oscilloscope. The scope is triggered by the 20MHz clock used
by the A/D. Any asymmetry between positive and negative
portions of the signal will be very obvious. This test is an
excellent indication of slew rate capability. At the peaks of the
envelope, consecutive samples swing completely through the
input voltage range.
®
®
ADC-207
120
120
110
110
100
100
90
90
80
OUTPUT
CODES
80
70
OUTPUT
CODES
60
70
60
50
50
40
40
30
30
20
20
10
10
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
NUMBER OF SAMPLES(X103 )
NUMBER OF SAMPLES (X103 )
Figure 6. 10MHz Envelope Test
Figure 5. Beat Frequency Test at 20MHz
FFT TEST
This test actually produces an amplitude versus frequency graph (Figure 7) which indicates harmonic distortion and signal-to-noise
ratio. The theoretical rms signal-to-noise ration for a 7-bit converter is +43.8dB.
4MHz4MHz
FUNDAMENTAL
FUNDAMENTAL
SAMPLE
PULSE
= 25ns
SAMPLE
PULSE
WIDTH = 25ns
70
70
69.2
69.2
65
65
60
60
55
55
50
50
AMPLITUDE (dB)
45
45
40
40
35
35
30
30
25
25
20
20
15
15
10
10
5
27.3
00
–5
–5
–10
–10
00
11
22
33
44
55
66
FREQUENCY (MHz)
Figure 7. FFT Test Using the ADC-207
77
88
99
10
10
®
®
ADC-207
MECHANICAL DIMENSIONS INCHES (MM)
24-Pin Ceramic LCC
18-Pin Ceramic DIP
+0.010
0.400 –0.005
+0.25
(10.16 –0.13 )
0.960 MAX.
(24.38 MAX.)
16
10
18
+0.010
0.400 –0.005
24
+0.25
1
DATEL
ADC-207MC
(10.16 –0.13 )
0.220 / 0.310
(5.59 / 7.87)
10
4
1
9
TOP VIEW
PIN 1
IDENTIFIER
0.090 MAX.
(2.29 MAX.)
0.015 / 0.060
(0.38/1.52)
0.200 MAX.
(5.1 MAX.)
0.020 ±0.005
(0.51 ±0.13)
0.008 / 0.015
(0.20 / 0.38)
0.014 / 0.023
(0.35 / 0.58)
0.100 TYP.
(2.540)
PIN 1
INDEX
0.290 / 0.320
(7.36 / 8.13)
SEATING
PLANE
0.035
(0.889)
0.050
(1.270)
TYP.
0.250 ±0.005
(6.35 ±0.13)
0.250 ±0.005
(6.35 ±0.13)
ORDERING INFORMATION
MODEL
TEMP. RANGE
PACKAGE
ADC-207MC
ADC-207MM
ADC-207MM-QL
0 to +70°C
–55 to +125°C
–55 to +125°C
18-pin DIP
18-pin DIP
18-pin DIP
ADC-207LC
ADC-207LM
ADC-207LM-QL
0 to +70°C
–55 to +125°C
–55 to +125°C
24-pin CLCC
24-pin CLCC
24-pin CLCC
ACCESSORIES
ADC-B207/208
®
®
IN N O VA T IO N a n d E X C E L L E N C E
Evaluation Board for DIP Version
(without ADC-207)
ISO 9001
R
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: (508) 339-3000 (800) 233-2765
Fax: (508) 339-6356
Internet: www.datel.com E-mail:[email protected]
Data Sheet Fax Back: (508) 261-2857
E
G
I
S
T
E
R
E
D
DS-0038C
12/04
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01
DATEL GmbH München, Germany Tel: 89-544334-0
DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein
do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.
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