ANALOGDEVICES fAX-ON-DEMAND HOTLINE
,.
- Page
HI
ANALOG
DEVICES
AC'97 SoundM~
Codec
AD1881
AC '97 2.1 FEATURES
Variable Sample Rate
True Line-level Output
AC '97 FEATURES
Fully Compliant AC '97 Analog 1/0 Component
48-lead lQFP Pacl(age
Multibit !,d Converter Architecture for Improved
SIN Ratio greater than 90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-level Stereo Inputs for Connection
from LINE, CD, VIDEO and AUX
Two Analog Line-level Mono Inputs for Speal(erphone
and PC BEEP
Mono MIC Input Switchable from Two External
Sources
High Quality CD Input with Ground Sense
Stereo Line-level Output
Mono Output for Speal<erphone or Internal Speal<er
Power Management Support
OBS
ENHANCED FEATURES
Mobile low Power Mixer Mode
Digital Audio Mixer Mode
DSP 16-Bit Serial Port Format, Slot 16 Mode
Supports
All Required WHQl Sample Rates
Full Duplex Variable 7 kHz to 48 I<Hz Sampling
Rate
with 1 Hz Resolution
PhatTM Stereo 3D Stereo Enhancement
Split Power Supplies
(3.3 V Digital/5 V AnalogI
Extended
6-Bit Master Volume Control
Audio Amp Power-Down
Signal
OLE
FUNCTIONAL
BLOCK
DIAGRAM
CSO CS1 CHAIN_IN CHAIN_CLK
AD1881
MIC1
MIC2
LlNEJN
TE
EAPD
AUX
CD
VIDEO
RESET
PHONE_IN
SYNC
MONO_OIlT
BIT_CLK
LNLVL_OIlT _L
SDATA_OUT
LlNE.-OIlT_L
SDATA.JN
LINE_OIlT_R
LNLVL_OIlT _R
=
=
G GAIN
A ATTENUATE
PC_BEEP
=
=
M MIlTE
MV MASTER
VOWME
XTALO
XTALI
Sound.1\1AX is a registered tradenmrk and PHAT is a trademark of An.~log De\iec, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility
is assumed by Analog Devices for its
use, nor for any infringements
of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062.9106.
U.S.A.
Tel: 781/329.4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
!1:!Analog Devices, Inc., 1999
- Page
ANALOGDEVICES fAX-ON-DEMAND HOTLINE
11
AD1881-SPECIFICATIONS
STANDARD
TEST CONDITIONS
Temperature
Digital Supply (VDD)
Analog Supply (Vce)
Sample Rate (Fs)
Input Signal
ANALOG
UNLESS OTHERWISE
25
3.3/5.0
5.0
48
1008
°C
V
V
kHz
Hz
NOTED
DAC Test Canditians
Calibrated
-3 dB Attenuation Relative to Full-Scale
Input 0 dB
10 ill Output Load
ADC Test CanditianS
Calibrated
0 dB Gain
Input -3.0 dB Relative to Full-Scale
INPUT
OBS
MiD
Parameter
Input Voltage (RMS Values Assume Sine Wave Input)
liNE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP
MIC with +20 dB Gain (M20
MIC with 0 dB Gain (M20
=1)
=0)
Input Impedance*
Input Capacitance*
MASTER VOLUME
Step Size (0 dB to -94.5 dB); liNE_OUf_I..,
Output Attenuation Range Span*
Step Size (0 dB to -46.5 dB); MONO_OUf
Output Attenuation Range Span*
Mute Attenuation of 0 dB Fundamental*
PROGRAMMABLE
I
I
OLE
I
Min
Parameter
Typ
Max
I
liNE_OUf_R
[ts
1
2.83
0.1
0.283
Vnns
Vp-p
Vnns
Vp-p
1
2.83
20
5
7.5
Vnns
Vp-p
ill
pF
Typ
Max
Units
80
dB
dB
dB
dB
dB
Typ
1.5
22.5
Max
Units
Typ
Max
TE
1.5
-94.5
1.5
-46.5
GAIN AMPUFIER-ADC
Parameter
MiD
Step Size (0 dB to 22.5 dB)
PGA Gain Range Span
ANALOG MIXER-INPUT
Parameter
dB
dB
GAINJAMPUFlERSJA TTENUA TORS
Min
I
Units
I
Signal-to-Noise
Ratio (SNR)
CD to IlNE_OUf
90
Other to IlNE- Ouf
Step Size (+ 12 dB to -34.5 dB): (All Steps Tested)
MIC, IlNE_IN, Aux, CD, VIDEO, PHONE_IN, DAC
Input Gain/Attenuation Range: MIC, IlNE, Aux, CD, VIDEO, PHONE_IN, DAC
Step Size (0 dB to -45 dB): (All Steps Tested) PC_BEEP
Input Gain/Attenuation Range: PC_BEEP
I
90
dB
dB
1.5
46.5
3.0
45
dB
dB
dB
dB
*Guarnnteed, not tested.
Specificationssubject to change without notia::.
-2-
REV. 0
ANALOGDEVICESfAX-ON-DEHAND
HOTLINE
- Page
12
AD1881
DIGITAL DECIMATION AND INTERPOLATION
Parameter
FILTERS*
Min
0
Passband
Passband Ripple
Transition Band
Stopband
0.4 x Fs
0.6 x Fs
Stopband Rejection
Group Delay
Group Delay Variation
ANALOG-
0.4 XFs
:to.09
0.6 x Fs
Hz
dB
Hz
00
Hz
dB
sec
Min
(THD)
Range (-60 dB Input THD+N
Referenced
DIGITAL- TO-ANALOG CONVERTERS
Parameter
85
to Full Scale, A-Weighted)
.Max
Units
0.02
-74
Bits
%
dB
Min
LNLVL_Our
Dynamic Range (-60 dB Input THD+ N Referenced to Full Scale, A-Weighted)
Signal-to-Intennodulation Distortion* (CCIF Method)
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crossta1k* (Input 1..,Zero R, Measure R_Our; Input R, Zero 1..,
Measure L_OUI)
Total Audible Out-of-Band Energy (Measured from 0.6 x Fs to 20 kHz)*
ANALOG OUTPUT
Parameter
85
dB
dB
87
85
I
OLE
Resolution
Total Hannonic Distortion (THD) LINE_Our,
-100
-90
-90
-85
:t1O
:to.5
:t5
.Max
0.02
-74
90
85
:t1O
-40
I
Typ
.Max
500
10
15
2.2
100
2.4
2.2
V REF_OUT
5
Minus Unmuted
Midscale
DAC Output)
*Gu..."'ntccd,not tested
Specificationssubject to change without notice.
-3-
:ts
Units
Bits
%
dB
dB
dB
%
dB
dB
IdB
1
2.83
2.0
dB
dB
%
dB
mV
TE
Typ
16
:to.5
-80
Min
Full-Scale Output Voltage
(LINE_Our, LNLVL_OUI)
Output Impedance*
External Load Impedance*
Output Capacitance*
External Load Capacitance
VREF
VREF_Our Current Drive
Mute Click (Muted Output
Typ
16
OBS
Distortion
/lS
CONVERTERS
Signal-to-Intennodulation Distortion* (CCIF Method)
ADC Crossta1k*
line Inputs (Input 1..,Ground R, Read R; Input R, Ground 1..,Read L)
LINE_IN to Other
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
REV. 0
Units
12/Fs
0.0
Over Passband
TO-DIGITAL
Resolution
Total Hannonic
.Max
-74
Parameter
Dynamic
Typ
Units
Vrms
Vp-p
11
!ill.
pF
pF
V
V
mA
mV
ANALOGDEVICESfAX-ON-DE"ANDHOTLINE
- Page
13
AD1881
STATIC DIGITAL SPECIFI CATIONS
Parameter
l\1in
Typ
Max
0.1 x DVDD
10
10
V
V
V
V
flA
flA
Max
Units
5.25
5.25/3.6
V
V
mW
mW
mA
mA
mA
dB
0.65 x DVDD
High Level Input Voltage (VIH): Digital Inputs
Low Level Input Voltage (VII..)
High Level Output Voltage (Vo, IoH = -0.5 mA
Low Level Output Voltage (V00, IoL = +0.5 mA
Input Leakage CuITent
Output Leakage Current
0.35 x DVDD
0.9 x DVDD
-10
-10
Units
POWER SUPPLY
Parameter
l\1in
Power Supply Range - Analog
4.75
4.75/3.0
OBS
Power Supply Range - Digital (5/3.3 V)
Power Dissipation - 5 V / 5 V
Power Dissipation - 5 V / 3.3 V
Analog Supply Current
-
520
330
40
63
40
40
5V
Digital Supply CUITent - 5 V
Digital Supply CuITent - 3.3 V
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICA TIONS*
Parameter
Input Clock Frequency
Recommended Clock Duty Cycle
POWER-DOWN
MODE
Typ
OLE
l\1in
45
Parameter
Set Bits
DVDD (3.3 V)
Typ
ADC
DAC
ADC and DAC
ADC + DAC + Mixer (Analog CD On)
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Analog CD Only (AC-link On)
Analog CD Only (AC-link Off)
Standby
PRO
PRI
PRl, PRO
LPMIX, PRl, PRO
PR2
PR2, PRO
PR2, PRI
PR2, PRl, PRO
LPMIX, PRS, PRI, PRO
LPMIX, PRI, PRO
PRS,PR4,P43,PR2,PRl,PRO
31
31
6
6
35
31
31
6
6
0
0
TE
Typ
24.576
50
Max
Units
55
MHz
%
AVDD (5 V)
Typ
Units
26
24
18
10
16
10
8
2
10
10
0.13
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*Guarnntccd, not tested.
Specifications subject to change without notice.
-4-
REV.
0
ANALOGDEVICESFAX-ON-DEHAND
HOTLINE
- Page
1~
AD1881
TIMING PARAMETERS
Paratneter
(GUARANTEED
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
OVER OPERATING
Delay
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter!
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge ofBIT_CLK
Hold from Falling Edge of BIT - CLK
BIT_CLKRise
Time
BIT_CLKFall
Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_Our
Rise Time
SDATA_Our
Fall TIme
End of Slot 2 to BIT_CLK,
SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OlIT)
Rising Edge of RESET to HI-Z Delay (ATE Test Mode)
Propagation Delay
OBS
NOTES
'Output jitter is directly dependent on crystal input jitter.
Specifications subject to eh3Ilge WitilOut notice.
REV.
TEMPERATURE
RANGE)
Symbol
.MiD
tRST_LOW
tRST2CLK
tSC_HIGH
tSc_LOW
tSC2CUZ
50
19.5
162.8
12.288
81.4
36.62
36.62
tCLK_LOW
OLE
0
-5-
-~
tRISEDOUT
5
5
2
2
2
2
2
2
2
2
0
15
Units
TIS
80
tCLKJIIGH
tFM.LDOUT
tS2_PDO
tSETUP2RST
toFF
Max
833
tCLK_PDRIOD
tSC]ERIOD
tSETUP
tHoLD
tRISECUZ
tFM.LCUZ
tRISESC
tFM.LSC
tRISEDN
tFM.LDN
Typ
40.69
40.69
48.0
20.8
4
4
4
4
4
4
4
4
750
44.76
44.76
10
10
10
10
10
10
10
10
10
fJS
TIS
fJS
TIS
l\1Hz
TIS
ps
TIS
TIS
kHz
fJS
liS
liS
ns
ns
ns
ns
ns
ns
ns
ns
ms
TIS
TIS
TIS
TE
25
15
-
ANALOGDEVICESfAX-ON-DEHAND
HOTLINE
Page
15
AD1881
""'"
.. tRST.LOW ~*4-
~12CLJ(
--i
~
BIT CLK
1
tRI~
1-
-J ~LK
SYNC~
tRlS~
1-
-J 1- tFALlSYNC
1-
-j ~;ALLDIN
1-
-j
flJ1JU1f
BILCLK
Figure 1. Cold Reset
SDATA
IN ~
tRI~
SDATA
OUT~
~S~
SYNC JtSVNC.I-UGH-{tRS12CLK1
BIT.CLK
n..rIJlJl.f
Figure 2. Warm Reset
~OUT
Figure 5. Signal Rise and Fall Time
OBS
tcuc.LOW
SYNC
BIT_CLK
:::g-
LOW
SYNC
tSVNC_HGH
tsVNC_PERlOO
Figure
BIT.CLK
SYNC
,~
3. Clock
Tl-
Timing
f
tg
OLE
BIT.CLK
SDATA_OUT
SDATA.IN
~
tS2_POOWN
TE
NOTE: BIT.CLK NOT TO SCALE
Figure 6. AC Link Low Power Mode Timing
RESET
L
SDATA.OUT
SDATA_OUT
SDATA_IN,
BIT _CLK
HI-Z
tHoLD
Figure 4. Data Setup and Hold
Figure 7. A TE Test Mode
-6-
REV. 0
ANALOGDEVICES fAX-ON-DEHAND HOTLINE
- Page
16
AD1881
ABSOLUTE
MAXIMUM
ORDERING
RATINGS*
Paratneter
Power Supplies
Digital (VDD)
Analog (Vcc)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Min
-0.3
-0.3
-0.3
-0.3
0
-65
Max
Units
6.0
6.0
:t10.0
Vcc+ 0.3
Voo + 0.3
+70
+150
V
V
mA
V
V
°C
°C
Model
Temperature
Range
Package
Description
Package
Option*
AD188I]ST
O°C to +70°C
48-Lead LQFP
ST-48
*ST
=Thin
Quad Ftatpaek.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
T1\"WJ= TCI\SE- (PD x 800
TCI\SE= Case Temperature in °C
Po = Power Dissipation in W
8Ci\ = Thermal Resistance (Case-to-Ambient)
8JA Thermal Resistance (Junction-to-Ambient)
8Jc Thermal Resistance (Junction-to-Case)
*Strcsscs greater than those listed under Absolute M'1Xinmrn R.~tings may cause
perm.ment d."UI1ageto the device. This is a stress rating only; fimction.~l operation
of tl1e device at tl1ese or any other conditions above tl10se indicated in the
operation.~lsectionoftl1is specification isnotirnplied. Exposurcto absolu te maximum
rating conditions for extended periods may affect device reliability.
=
=
OBS
Package
8lA
8lC
8CA
LQFP
76.2°CIW
17°CIW
59.2°CIW
OLE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Aldl0ugh dle AD1881 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic
discharges. TIlerefore, proper ESD
precautions are recommended
to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
48-Lead LQFP
ii,
~
~
a:.
~,
0
0
~ 'Ii
iI:
~
5
~
I,
5
5
0
0
;1.' '" 0'
~
I
I 8 t;
<3~3~:i
~
o"Hjo!:1~
148l14711461145
~141l~I38U37
1441143
DVDD1
~ UNE_OUT_R
351 UNE_OUT_L
XTL IN
;;1 CX3D
XTL_OUT
~
DVSS1
SDATA_OUT
[I
~
AD1881
TOP VIEW
(No!to Scale)
BIT_CLK
DVSS2 12:
FILT_R
~
~
~
$DATA_IN C!:
DVDD2 C!:
EJ
PC_BEEP fi2
251 AVDD1
131114111511161171118111911201121122
z la:
;;><><
24
t;~~ ~,~~~~~a~:d
!!!!I!
d13 :i~~
if
s:!:
::J::J
REV.
0
=NO
AFIL T2
AFILT1
VREFOUT
VREF
261 AVSS1
SYNC~
RESET@
NC
CONNECT
GUIDE
8'
-7-
TE
RNRLOGDEVICES fRX-ON-DEHRND HOTLINE
- Page 17
AD1881
PIN FUNCTION
DESCRIPTIONS
Digital I/O
Pin Name
LQFP
110
Description
XTL_IN
XTL- OUI'
SDATA_OUI'
BIT_CLK
SDATA_IN
SYNC
RESET
2
3
5
6
8
10
11
I
Crystal (or Clock) Input, 24.576 MHz.
Crystal Output.
AC-Unk Serial Data Output, ADl881 Input Stream.
AC-Unk Bit Clock. 12.288 MHz Serial Data Clock. Daisy Chain Output Clock.
AC-Unk Serial Data Input. AD1881 Output Stream.
AC-Unk Frame Sample Sync 48 kHz Fixed Rate.
AC-Unk Reset. AD1881 Master H/W Reset.
o
I
O/I*
o
I
I
*Input if eonfigured as a slave device.
Daisy
Chain
Connections
Pin Name
LQFP
CSO
CSI
EAPD
CHAIN_IN
CHAIN_CLK
45
46
Type
I
I
47
48
I
I/O
OBS
o
Description
Daisy Chain Codec Select LSB, ADC/DAC Right Bit Streams.
Daisy Chain Codec Select MSB, ADC/DAC Left Bit Streams.
External Amp Power-Down Control Signal, Default 1..0, Active HI
Daisy Chain Data Input for Data from Slave Codecs SDATA_IN.
24.576 MHz Buffered Clock Input/Output for Slave Codecs.
OLE
Analog I/O
These signals connect
the AD1881
Pin Name
LQFP
110
Description
PC_BEEP
PHONE_IN
AlJX_L
AU}CR
VIDEO_L
VIDEO_R
CD_L
CD_GND_REF
CD_R
MICI
MIC2
UNE_IN_L
UNE_IN_R
UNE- OUI' _L
UNE- OUI' _R
MONO_OUI'
LNLVL_OUI'_L
LNLVL_OUI'_R
12
13
14
15
16
17
18
19
20
21
22
23
24
35
36
37
39
41
I
I
I
I
I
I
I
I
I
I
I
I
I
PC Beep. PC Speaker Beep Passthrough.
Phone. From Telephony Subsystem Speakerphone or Handset.
Auxiliary Input Left Olannel.
Auxiliary Input Right Olannel.
Video Audio Left Channel.
Video Audio Right Olannel.
CD Audio Left Channel.
CD Audio Analog Ground Reference for Differential CD Input.
CD Audio Right Channel.
Microphone 1. Desktop Microphone Input.
Microphone 2. Second Microphone Input.
Une In Left Channel.
Une In Right Channel.
Une Out Left Channel.
Une Out Right Channel.
Monaural Output to Telephony Subsystem Speakerphone.
Une-Level Output Left Olannel.
Une-Level Output Right Channel.
component
o
o
o
o
o
to analog sources and sinks, including
microphones
and speakers.
TE
Filter/Reference
These signals are connected to resistors, capacitors, or specific voltages.
110
Pin Name
LQFP
Description
VREF
VREF o UI'
AFILTI
AFILT2
FILT_R
FILT_L
RX3D
CX3D
27
28
29
30
31
32
33
34
o
o
o
o
o
o
o
I
Voltage Reference Filter.
Voltage Reference Output 5 mA Drive (Intended for MIC Bias).
Antialiasing Filter Capacitor-ADC Right Olannel.
Antialiasing Filter Capacitor-ADC Left Olannel.
AC-Coupling Filter Capacitor-ADC
Right Olannel.
AC-Coupling Filter Capacitor-ADC
Left Olannel.
3D Phat Stereo Enhancement-capacitor.
3D Phat Stereo Enhancement-capacitor.
-8-
REV. 0
ANALOGDEVICESfAX-ON-DEMAND
HOTLINE
- Page
18
AD1881
Power
and GnJUnd Signals
Pin Name
LQFP
DVDDI
DV SSl
DV SS2
DVDD2
AVDDI
AVSS1
AVDD2
AVSS2
Description
1
4
7
9
25
26
38
42
Type
I
I
I
I
I
I
I
I
Pin Name
LQFP
Type
Description
NC
NC
NC
40
43
44
Digital VDD-5.0
Digital GND
Digital GND
Digital VDD-5.0
Analog VDD-5.0
Analog GND
Analog VDD-5.0
Analog GND
V/3.3 V
V/3.3 V
V
V
No Connects
OBS
MlC1
MlCl
~
rs
OdIll2Odll
OLE
I
M2<I0x0EI
Ox'"'
UNE.JN
No Connect
No Connect
No Connect
AUX
CD
...............
L.5IRS~
LSI4)
RS(4)
LS(3)
PHONEJN
1
~
E
GAoXOC
-
I'
PHM
UNE OUTJ.
~
>-
-M Oxo:l ~A Oxo:l
... LMV
=;=
M Ox06
A Ox06
MMV
~
o
1:1
=MO"12 !=
"x 0,,",
AO,02
)4
MM
-
RMV
-
~~
RS(S)
SOX1A
/11
..
II~LA lI~cv lI~v
1M OxOEIiMOxIOIiMo"'IIM
IMCM IILM
-.- , J
IICM
o"sIIM
°"41
IIVM
I
I
-
~
~
~P
-<9-<!14"" ""0-
OxOA
§
AOxOA
l6-lilT
~~M
,;..AID
OXIC
ROO
1M
1&-liIT
,... AID
G
-@---<~)--o
-
..
~
....
IT~_. ~
0'7A
-<
~~~
~
7C;:-<
DAMO".
LOV
IS.liIT
OM
,;..CWA
~
ROV
OM
I--
~
'S.BIT
'
,;..CWA
'
VOLUME
,
OSCILLATORS
XTL_OUT
Figure 8. Block Diagram Register Map
LPBK available in test mode only. (Needs modification)
-9-
T
XTL_'N
SYNC
lilT_CLK
SDATA_OUT
SDATA_'N
A.ATTENUATE
M..'UTE
I
-<
Ox'"' :J-<
.-- ~
GAIN
MY - MASTER
RESET>
L.L
DAM0".
-
-
PCV
REV. 0
~
POP
'1
22
LNLVL_OUT_R
PCM
GMOxlC
Ox,",
~
:
T
~E
~ADCRATE
I
~ --dr~ - -0
~~
~
lI~vv I SRI
IIAM
III
M~J~
2!
~
I:'-II::."'II:,:."'II:,::"II~"'I
-~-"'~
=::::;
MOxOC
LNLVL_OUT_L
LS(5)
~~-R
-
PC_liEEP
LS(I)
RS(I)
:::~(7) ~
STEREO "X (L)
MONO"X
UNE OUTJI
S
LS(2) ~
VIDEO
MONO_OUT
RS(3)
AD1881
I
NALOGDEVICESfAX-ON-DEMAND
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19
AD1881
PRODUCT OVERVIEW
The ADI881 is the flISt audio Codec to meet the Audio Codec
'972.0 and 2.1 Extensions. In addition, the AD 1881 SoundMAX
Codec is designed to meet all requirements of the Audio Codec
'97, Componenr Specijia2rion, Revision 1.03, I{;)1996, Intel Corporation, found at www.lmd.com. The ADI881 also includes
some other Codec enhanced features such as communicating
to three Codecs on the same link, a DSP serial port mode,
modem sample rates and filtering, and built-in Phat Stereo 3D
enhancement.
The AD 1881 is an analog front end for high performance PC
audio, modem, or DSP applications. The AC '97 architecture
derIDes a 2-chip audio solution comprising a digital audio
controller, plus a high quality analog component that includes
Digital-to-Analog Converters (DACs), Analog-tO-Digital Converters (ADCs), mixer and I/O.
OBS
The main architectural features of the AD 1881 are the high
quality analog mixer section, two channels of~ ADC conversion, two channels of~ DAC conversion and Data Direct
Scrambling (D2S) rate generators. The AD1881's left channel
ADC and DAC are compatible for modem applications supporting
irrational sample rates and modem filtering requirements.
Analog-to-Digital Signal Path
The selector sends left and right channel information to the
programmable gain amplifier (PGA). The PGA following the
selector allows independent gain control for each channel entering the ADC from 0 dB to +22.5 dB in 1.5 dB steps. Each
channel of the ADC is independent, and can process left and
right channel data at different sample rates.
S3II1ple Rates and D2S
The AD 1881 default mode sets the Codec to operate at 48 kHz
sample rates. The converter pairs may process left and right
channel data at different sample rates. The ADI881 sample rate
generator allows the Codec to instantaneously change and process sample rates from 7 kHz to 48 kHz with a resolution of
I Hz. The in-band integrated noise and distortion arrifacts
introduced by rate conversions are below --90 dB. The ADl881
uses a 4-bit D/A structure and Data Directed Scrambling (D2S)
to enhance noise immunity on motherboards and in PC enclosures, and to suppress idle tones below the device's quantization
noise floor. The nzs process pushes noise and distortion artifacts caused by errors in the multibit DAC to frequencies beyond the auditory response of the human ear and then filters
them.
OLE
Digital-to-Analog Signal Path
The analog output of the DAC may be gained or attenuated
from +12 dB to -34.5 dB in 1.5 dB steps, and summed with any
of the analog input signals. The summed analog signal enters
the Master Volume stage where each channel of the mixer output maybe attenuated from 0 dB to -94.5 dB in 1.5 dB steps or
muted.
FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD 1881 and is
intended as a general introduction to the capabilities of the
device. Detailed reference information may be found in the
descriptions of the Indexed Control Registers.
Analog Inputs
The Codec contains a stereo pair of~ ADCs. Inputs to the
ADC may be selected from the following analog signals: telephony (PHONE_IN), mono microphone (MICI or MIC2),
stereo line (UNE_IN), auxiliary line input (AUX), stereo CD
ROM (CD), stereo audio from a video source (VIDEO) and
post-mixed stereo or mono line output CUNE_OUT).
TE
Analog Mixing
PHONE_IN, MICI or MIC2, UNE_IN, AUX, CD and
VIDEO can be mixed in the analog domain with the stereo
output from the DACs. Each channel of the stereo analog inputs may be independently gained or attenuated from + 12 dB to
-34.5 dB in 1.5 dB steps. The summing path for the mono
inputs (PHONE_IN, MICI, and MIC2 to UNE_OUT) duplicates mono channel data on both the left and right UNE_OUT.
Additionally, the PC attention signal (PC_BEEP) may be mixed
with the line output. A switch allows the output of the DACs to
bypass the Phat Stereo 3D enhancement.
Digital Audio Mode
The ADI881 is designed with a Digital Audio Mode (DAM)
that allows mixing of all analog inputs independent of the DAC
output signal path. Mixed analog input signals may be sent to
the ADCs for processing by the controller or the host, and may
be used during simultaneous capture and playback at different
sample rates.
line-Level Outputs
The ADl88l offers a ttue line-level output for notebook docking station and home theater applications. The line-level output
does not change with master volume settings.
Host-Based Echo Cancellation Support
The AD188l supports time correlated I/O data format by presenting MIC data on the left channel of the ADC and the mono
summation of left and right output on the right channel. The
ADC is splittable; left and right ADC data can be sampled at
different rates.
Power Management Modes
The ADl88l is designed to meet ACPI power consumption
requirements through flexible power management control of an
internal resources.
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ANALOGDEVICESfAX-ON-DEMAND
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211
AD1881
Indexed
Control
Registers
Reg
N IJ1tt
Name
Dl5
Dl4
DB
Dl2
Dll
DIO
D9
D8
D7
D6
D5
D4
D3
D2
DI
DO
Defuult
OOh
Reset
X
SE'1
SID
SE2
SEI
SEO
ID9
IDS
1m
ID6
ID5
IDI
ID3
IDl
IDI
IIX)
OIOOh
02h
Master Volwne
MM
X
VIIIV5 L'vlV'l IJv\V 3 L'v1V2 IJv\V I L'AVO X
X
RMV5 RMV'1 RlvlV3 R.'\fV2 R.'\fVI R.'\fVO 8000h
01h
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
06h
II/laster Volume .'\'iono
lvL'V11\'iX
X
X
X
X
X
X
X
X
X
lvL'VlV lvL'VlV lvL'VlV lvL'VlV lvL'VlV 8000h
2
I
0
,1
2
08h
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
OAh
PC Beep Volwne
PCM
X
X
X
X
X
X
X
X
X
X
PCV3
PCV2 PCVI
PHV3 PHV2 PHVI
OBS
X
X
X
X
X
X
X
PCVO X
X
X
8000h
PHVO 8008h
OCh
Phone In Volume
PRM
X
X
X
X
X
X
X
X
X
X
PRYI
OEh
WC Volume
MCM
X
X
X
X
X
X
X
X
M20
X
MCV'1 MCV3 MCV2 MCVl MCVO 8008h
IOh
Line In Volwne
L'\f
X
X
lLV'1
lLV3
lLV2
lLVI
lLVO
X
X
X
RLV1 RLV3 RLV2 RLVI
RLVO 8808h
LeV,!
LCV3 LeV2
LeVI
LeVO X
X
X
RCV'1 RCV3 RCV2 RCVI
RCVO 8808h
12h
CD Volume
CVM
X
X
Hh
Video Volume
VM
X
X
16h
Aux Volume
AM
X
X
18h
PCMOutVol
OM
X
X
IAh
Record Select
X
X
X
ICh
Record Gain
1M
X
X
IEh
OLE
LVV'1 LVV3 LVV2 LVVI
LVVO X
X
X
RVV'1 RVV3 RVV2 RVVI RVVO 8808h
LAV'1 LAV3 LAV2 LAVI
LAVO X
X
X
RAV'1 RAV3 RAV2 RAVI RAVO 8808h
lDV'1
lDV3
lDV2
lDVI
lDVO X
X
X
ROV'1 ROV3 ROV2 ROVI ROVO 8808h
X
X
LS2
LSI
LSO
X
X
X
X
X
LIM3
LIM2
LL'VlJ LL'VlO X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MIX
MS
LPBK X
X
X
X
X
X
X
X
X
X
X
X
PRI
PR3
PRZ
PRI
PRO
X
X
X
X
Reserved
X
X
X
20h
General Purpose
POP
X
3D
2211
3D Control
X
X
X
26h
Power-Down CntrVStat
EAPD
X
PRS
28h
Extended Audio ID
ill I
IIX)
X
X
X
X
X
X
X
X
X
X
2Ah
Extended Audio Stat/Crrl
X
X
X
X
X
X
X
X
X
X
X
X
2Ch!
PCM DAC Rate (SRI)
SRI5
SRH
SRJ3
SRI2
SRI I
SRI 0
SR9
SRS
SR7
SR6
SRS
PCM ADC Rate (SRI))
SRI5
SRB
SRJ3
SRI2
SRJJ
SRJO
SR9
SR8
SR7
SR6
3-111
Reserved
X
X
X
X
X
X
X
X
X
..
..
..
..
..
..
..
..
..
..
72h
Reserved
X
X
X
X
X
X
X
7111
Serial Configuration
SLOT
16
REG
REG
REG
Ml
0
DRQ
EX
DLR
M2
Q2
DAC
Z
LPW
X
X
DAM
DMS
DLSR X
X
RS2
RSI
RSO
OOOOh
TE
RING RL'V12 RL'vlJ RL'VlO 8000h
X
X
X
X
X
X
X
X
X
O{)OOh
DP3
DP2
DPI
DPO
OOOOh
REF
M--'L
DAC
ADC
OOOXh
X
X
X
VRA
OOOlh
X
X
X
VRA
OOO{)h
SRI
SR3
SR2
SRI
SRI)
BB80h
SRS
SRI
SR3
SR2
SRI
SRO
BB80h
X
X
X
X
X
X
X
X
..
..
..
..
..
..
..
..
..
X
X
X
X
X
X
X
X
X
X
DLR
DLR
X
X
X
X
X
QI
QO
DRRQ DRRQ DRRQ 7XOXh
2
I
0
ALSR MOD
EX
SRXI
OD7
SRXS X
X
DRSR X
ARSR
(HO,U,
S6
S5
S3
S2
SO
'IH'U,
(7Ah)*
32hl
(7811)*
76h
lwsc. Control Bits
m
7Ch
Vendor IDI
F7
F6
F5
F'1
F3
F2
FI
FO
S7
7Eh
Vendor IDl
T7
T6
T5
T1
T3
T2
TI
TO
REV7 REV6 REV5 REV1 REV3 REV2 REVI
KOTES
All registers not shown and bits containing an X are asswned to be reserved.
Odd register addresses are aliased to the neXt lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*Indicates Aliased register for AD1819, ADI819A backward compatibility.
REV. 0
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REVO 53-10h
- Page 21
RNRLOGDEVICES fRX-ON-DEMRND HOTLINE
AD1881
Reset
(Index OOh)
Reg
Nmn Name
015
014
013
D12
Dll
OOh
X
SE4
sm
sm
SEl SEO 1D9 IDS 1D7 1D6 IDS 1D4 103
Reset
010
09
D8
D7
D6
D5
03
04
D2
Dl
DO
Detauh
1D2
IDI
IDa
040Oh
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except
74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo
Enhancement.
ID[9:0]
Identify Capability. The ID decodes the capabilities of ADlSSI based on the following:
1
Function
ADl881 *
Bit
=
I
I
0
0
0
0
1
0
0
0
0
0
Dedicated MIC PCM In Channel
Modem line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
IS-Bit DAC Resolution
20-Bit DAC Resolution
IS-Bit ADC Resolution
20-Bit ADC Resolution
100
IDI
ID2
ID3
ID4
ID5
ID6
ID7
IDS
ID9
OBS
OLE
'1l1e AD1881 contains none of the option...t features identified by these bits.
SE[4:0]
Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Master Volume Registers (Index 02h)
Reg
Num
Name
DlS
014
013
OZh
Master
Volume
MM
X
LMVS LMV4 LMV3 LMVZ LMVI
OlZ
011
010
09
08
04
03
TE
OZ
01
07
06
OS
LMVO X
X
RMVS RMV4 RMV3 RMVZ RMVI
00
Oetaul1:
RMVO 8000h
RMV[5:0]
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of -94.5 dB.
IMV[5:0]
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of -94.5 dB.
MM
Master Volume Mute. When this bit is set to "1," the channel is muted.
Master
Reg
Num
06h
Volume
. . . xMVO
MM
xMV5
0
0
0
1
00 0000
01 1111
11 1111
Function
0 dB Attenuation
-46.5 dB Attenuation
-94.5 dB Attenuation
-CO dB Attenuation
xx XXXX
Mono (Index 06h)
Name
OlS
Master VoIUtne
MODO
MMMX
014 013 01Z 011 010 09
X
X
X
X
X
08
07
06
OS
04
03
OZ
01
DO
X
X
X
X
MMV4 MMV3 MMVZ MMVI MMVO 8000h
Default
MMV[4:0]
Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of -46.5 dB.
MMM
Mono Master Volume Mute. When this bit is set to "1," the channel is muted.
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ANALOGDEVICESfAK-ON-DEHAND
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AD1881
PC Beep Register
Reg
Nwn
NBD1e
OAh
PC_BEEP
(Index OAh)
015
Vohu:ne PCM
014
013
012
011
010
09
08
X
X
X
X
X
X
X
06
07
05
04
03
02
01
DO
DefaulT
X
PCV3
PCV2
PCVI
PCVO
X
8000h
PCV[3:0]
PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output
from 0 dB to a maximum attenuation of --45 dB. The PC Beep is routed to Left and Right line outputs even when
the RESET pin is asserted. This is so that Power on Self-Test (POST) codes can be heard by the user in case of a
hardware problem with the Pc.
PCM
PC Beep Mute. When this bit is set to "1," the channel is muted.
PCV3
0
0000
0 dB
0
1
1111
xxxx
--45 dB Attenuation
-00 dB Attenuation
OBS
Phone
Volume
Reg
Nwn
NlUDe
OCh
Phone
(Index OCh)
Vohu:ne
Function
Attenuation
OLE
015
014
013
012
011
010
09
08
PHM
X
X
X
X
X
X
X
07
06
OS
04
03
02
01
DO
OefBu1
X
PHV4 PHV3 PHYZ PHVI PHVO 8008h
TE
Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
Phone Mute. When this bit is set to "1," the channel is muted.
PHV[4:0]
PHM
MIC Volume
. . . PCVO
PCM
(Index OEh)
Reg
Nwn
N BIDe
015
014
013
012
011
010
09
08
07
06
OEh
Mic Volume
MCM
X
X
X
X
X
X
X
X
MIO X
OS
04
03
MCV4
MCV3
02
01
00
OetBuIt
MCYZ
MCVI
MCVO
800Sh
MCV[4:0]
MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
M20
Microphone 20 dB Gain Block
= Disabled;
0
1
MCM
= Enabled;
Gain
Gain
=0 dB.
= 20
dB.
MIC Mute. When this bit is set to "I," the channel is muted.
lineIn Volume
(Index
IOh)
Reg
Nwn
Nmne
015
014
013
012
10h
Une InVolwne
LM
X
X
LLV4 LLV3 LLV2 LLVI LLVO
011
010
09
08
07
06
05
04
03
02
01
DO
OeCau1
X
X
X
RLV4
RLV3
RLV2
RLVI
RLVO
8808h
RLV[4:0]
Right line In Volume. Allows setting the line In right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
ILV[4:0]
line In Volume Left. Allows setting the line In left channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
line In Mute. When this bit is set to "1," the channel is muted.
1M
REV. 0
-13-
- Page
ANALOGDEVICES fAX-ON-DEHAND HOTLINE
23
AD1881
CD Volume
Reg
Nwn
12h
(Index
12b)
DIS
NBDlC
CD Volwne CVM
DI4
D13
D12
Dl1
DIO
D9
D8
X
X
LCV4 LCV3 LCV2 LCVl LCVO
D7
D6
D5
D4
D3
D2
DI
DO
Def'ault
X
X
X
RCV4
RCV3
RCV2
RCVI
RCVO
880Sh
RCV[4:0]
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
LCV [4:0]
Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
CD Volume Mute. When this bit is set to "1," the channel is muted.
CVM
Video Volume
(Index
I4h)
OBS
Reg
Nwn
Natne
D15
DI4
D13
D12
14h
Video
VM
X
X
LVV4 LVV3 LVV1 LVVI LVVO
Volwne
RW[ 4:0]
DI0
D9
08
07
06
05
04
03
02
01
00
Default
X
X
X
RVV4
RVV3
RVV1
RVVI
RVVO
880Sh
OLE
Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
Video Mute. When this bit is set to "1," the channel is muted.
LW [4:0]
VM
AUXVolume
DI1
(Index
I6b)
Reg
Nwn
Name
16h
AWl Vol1UDe AM
DI5
DI4
D13
D1Z
DI1
DI0
X
X
LAV4 LAV3
09
LAVZ LAVI
D8
07
D6
05
D4
03
LAVO
X
X
X
RAV4
RAV3
TE
DZ
DI
DO
Default
RAV2
RAVI
RAVO
880Sh
RAV[4:0]
Right Aux. Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
IAV[4:0]
Left Aux. Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
Aux. Mute. When this bit is set to "1," the channel is muted.
AM
PCM Out Volume
(Index
ISh)
Reg
Nwn
Natne
DI5
DI4
D13
DIZ
ISh
PCM Out
Volume
OM
X
X
LOV4 LOV3
Dll
DID
D9
LOVZ LOVI
D8
D7
D6
D5
D4
D3
DZ
DI
DO
Default
LOVO
X
X
X
ROV4
ROV3
ROV2
ROVI
ROVO
880Sh
ROV[4:0]
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
LOV[4:0]
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is + 12 dB to -34.5 dB. The default value is 0 dB, mute enabled.
OM
PCM Out Volume Mute. When this bit is set to "1," the channel is muted.
Volume
Table (Index OCh to I8h)
... xO
MM
x4
0
0
0
1
00000
01000
11111
xxxxx
Function
+12 dB Gain
0 dB Gain
-34.5 dB Gain
-00 dB Gain
-14-
REV. 0
ANALOGDEVICES fAX-ON-DEMAND HOTLINE
- Page
2~
AD1881
Record
Select Control
Reg
Num
NaJDe
IAh
Record
Select
Register
(Index
lAb)
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
DO
Default;
X
X
X
X
X
LS2
LSI
LSO
X
X
X
X
X
RS2
RSI
RSO
OOOOh
RS[2:0]
Right Record Select
LS[2:0]
Left Record Select.
Used to select the record source independently for right and left. See table for legend.
The default value is OOOOh,which corresponds to MIC in.
RS2. .. RSO
RightRecord Source
0
1
2
3
4
5
6
7
MIC
CD_R
VIDEO_R
AlDCR
llNE_IN_R
Stereo Mix (R)
Mono Mix
PHONE_IN
LS2. .. LSO
Left RecordSource
0
1
2
3
4
5
6
7
MlC
CD_L
VIDEO_L
AUX_L
llNE_IN_L
Stereo Mix (1.)
Mono Mix
PHONE_IN
OBS
OLE
Record
Gain (Index
TE
ICh)
Reg
Nmn
Name
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
00
lCh
Record Gain
1M
X
X
X
LIM3
LIM2
LIMI
LIMO
X
X
X
X
RIM3
RIM2
RIMI
RIMO 8000h
efault
RlM[3:0]
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is OdB to +22.5 dB.
llM[3:0]
Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.
Input Mute.
1M
0
1
REV. 0
= Unmuted,
=Muted
or -00
dB gain.
. . . xIMO
1M
xIM3
0
0
I
II II
0000
+22.5 dB Gain
0 dB Gain
xxxxx
-00
-15-
Function
dB Gain
ANALOGDEVICESfAX-ON-DEMAND
HOTLINE
- Page 25
AD1881
General
Purpose
Register
Reg NBlDe
NUID
ZOh
General
Purpose
(Index 20h)
D8
D15
D14
D13
DU
Dl1
Dl0
D9
POP
X
3D
X
X
X
MIX MS
D7
D6
LPBK X
D5
D4
D3
DZ
Dl
DO
Default
X
X
X
X
X
X
OOOOh
Note: This register should be read before writing to generate a mask for only the bites) that need to be changed. The function default value is OOOOhwhich is all off.
LPBK
Loopback Control. ADC/DAC Digital Loopback Mode
MIC Select
0 = MIC!.
1 = MIC2.
MS
OBS
MIX
Mono Output Select
0
1
=Mix.
= MIe.
3D
3D Fhat Stereo Enhancement
0 Fhat Stereo is off.
1 = Fhat Stereo is on.
POP
PCM Output Path and Mute. The POP bit controls the optional PCM out 3D bypass path (the pre- and post-3D
PCM out paths are mutually exclusive).
0 pre-3D.
1 post-3D.
=
OLE
=
=
3D Control Register (Index 22h)
TE
Reg
NUID NBlDe
D15
D14
DU
D1Z
Dl1
Dl0
D9
D8
D7
D6
D5
D4
D3
DZ
Dl
DO
Default
ZZh*
X
X
X
X
X
X
X
X
X
X
X
X
DP3
DPZ
DPI
DPO
OOOOh
3D
DP[2:0]
Control
Depth Control. Sets 3D "Depth" Phat Stereo enhancement according to table below.
DP3
.
.
.
DPO
Depth
0000
0001
0%
6.67%
1110
1111
93.33%
100%
-16-
REV. 0
ANALOGDEVICES FAX-ON-DEMANDHOTLINE
- Page
26
AD1881
Ready Register
Subsection
Reg
Num
Nwne
26h
Power-Down
(Index 26h)
CntrllStat
D15
D14
DB
D12
D11
DID
D9
D8
D7
D6
D5
D4
D3
D2
Dl
DO
Default
EAPD
X
PR5
PR4
PR3
PR2
PRI
PRO
X
X
X
X
REF
ANL
DAC
ADC
N/A
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the
AD1881 subsections. If the bit is a one, then that subsection is "reacfy." Ready is derIDed as the subsection able to perfonn in its
nominal state.
ADC
ADC section ready to transmit data.
DAC
DAC section ready to accept data.
ANL
Analog gainuators, attenuators, and mixers ready.
OBS
REF
Voltage References, VREF and VREFOlIT up to nominal level.
PR[5:0]
AD1881 Power-Down Modes. The first three bits are to be used individually rather than in combination with each
other. The last bit PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be
powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until
the reference is up.
OLE
PRS has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can
be either up or down, but all power-up sequences must be allowed to run to completion before PRS and PR4 are
both set.
In multiple-codec systems, the master codec's PRS and PR4 bits control the slave codec. PRS is also effective in
the slave codec if the master's PRS bit is clear, but the PR4 bit has no effect except to enable or disable PRS.
External Audio Amp Power Down. Available when programmed as an AC '97 codec.
0 =Pin 47 set to LO state (default).
1 Pin 47 set to HI state.
EAPD
=
Power- Down State
ADC Power-Down
DAC Power-Down
ADC and DAC Power-Down
Mixer Power-Down
ADC + Mixer Power-Down
DAC + Mixer Power-Down
ADC + DAC + Mixer Power-Down
Standby
Extended
Audio ID Register
Reg
Num
Nwne
28h
Extended
Audio ID
Pili
PR4
PRJ
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
TE
PRZ
PRI
PRO
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
(Index 28h)
D15
D14
DB
D12
D11
DID
D9
D8
D7
D6
D5
D4
D3
D2
Dl
DO
Default
IDI
IDO
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
N/A
Note: The Extended Audio ID is a read only register.
VRA
Variable Rate Audio. VRA = 1 enables Variable Rate Audio.
ID[I:0]
IDl, IDO is a 2-bit field that indicates the codec configuration: Primary is 00; Secondary is 01, 10, or 11.
REV. 0
-17-
-~--
ANALOGDEVICES fAX-ON-DEHAND HOTLINE
- Page27
AD1881
Extended
Audio Status
and Control
Register
(Index
2Ab)
Reg
Num
Name
D15
D14
D13
D1Z
Dll
D10
D9
D8
D7
D6
D5
D4
D3
DZ
D1
DO
Default
lAh
ExteDdedAudio StlClrI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
Da
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio
features.
VRA
Variable Rate Audio. VRA
signaling.
= I enables Variable Rate Audio mode
(sample rate control registers and SLOTREQ
PCM DAC Rate Register (Index 2Ch)
Reg
Num
Name
ZCh/(7Ah)
PCM DAC Rate SR1S SRl4
DI5
DI4
DB
DlZ
OBS
011
SRl3 SR1l SRn
010
09
08
07
06
05
04
03
02
DI
DO
Default
SR10 SR9 SR8 SR7 SR6 SRS SR4 SR3 SRZ SRI SRO BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ab must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48k.
OLE
Writing to this register allows programming of the sampling frequency from 7 kHz (lB58h) to 48 kHz (BB80h) in
I Hz increments. Programming a value outside of the range 7040 Hz (I b80h) to 48000 Hz (bb80h) causes the
codec to saturate to 48 kHz if a rate greater than 48 kHz is programmed or to 7 kHz if a rate less than 7 kHz is
programmed. For all rates, if the value written to the register is supported, that value will be echoed back when
read, otherwise the closest rate supported is returned.
SR[15:0]
PCM ADC Rate Register (Index 32h)
Reg
Hum
Name
015
014
DB
32h1(78h) PCM ADC Rate SKIS SR14 SRB
Dl2
011
SRI2 SRn
DID
09
08
07
D6
D5
04
TE
03
02
DI
DO
Default
SRIO SR9 SR8 SR7 SR6 SRS SR4 SR3 SR2 SRI SRO BB80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48k.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7 kHz (lB58h) to 48 kHz (BB80h) in
I Hz increments. Programming a value outside of the range 7040 Hz (lb80h) to 48000 Hz (bb80h) causes the
codec to saturate to 48 kHz if a rate greater than 48 kHz is programmed, or to 7 kHz if a rate less than 7 kHz is
programmed. For all rates, if the value written to the register is supported, that value will be echoed back when
read, otherwise the closest rate supported is returned.
Serial Configuration
(Index 74h)
Rex
Num
N.....8
74h
Serial
SLOT REGMZ
16
Configuration
D15
DI4
D13
DlZ
Dll
DIU
D9
D8
D7
REGMI REGMO DRQEN DLRQZ DLRQl DLRQO X
D6
D5
D4
D3
D
Dl
DO
X
X
X
X
DRRQZ DRRQl DRRQO X
D..fttult
Note: This register is not reset when the reset register (register OOh)is written.
DRRQO
Master Codec DAC right request.
DRRQI
Slave I Codec DAC right request.
DRRQ2
Slave 2 Codec DAC right request.
DLRQO
Master Codec DAC left request.
DLRQI
Slave I Codec DAC left request.
DLRQ2
DRQEN
Slave 2 Codec DAC left request.
Enable DAC request bits in status address and data slot.
REGMO
Master Codec register mask.
REGMI
Slave I Codec register mask.
REGM2
SLOT I 6
Slave 2 Codec register mask.
Enable 16-bit slots.
-18-
REV. 0
ANALOGDEVICES fAX-ON-DEHAND HOTLINE
- Page ~B
AD1881
DRQEN and DxRQx are retained only for compatibility with the AD 1819. New controller designs should use the VRA bit in register
2Ah and the request bits in the status address slot instead.
If your system uses only a single ADI88I,
you can ignore the register mask and the slave lIslave 2 request bits. If you write to this
register, write ones to all of the register mask bits. The DxRQx bits are read-only.
The Codec asserts the DxRQx bit when the corresponding DAC channel can accept data in the next frame. These bits are snapshots
of the Codec state taken when the current frame began (effectively, on the rising edge of SYNC), but they also take notice of DAC
samples sent in the current frame.
If you set the DRQEN bit, the ADI881 will fIll all; otherwise, unused AC link status address and data slots with the contents of
register 74h. That makes it somewhat simpler to access the information because you don't need to continually issue AC link read
commands to obtain the register contents.
Also, the DAC requests are reflected in Slot 1, bits (11 . . . 6).
SLOT 16 makes all AC link
slots 16 bits in length, formatted into 16 slots.
OBS
i\1iscellaneous
Control
Bits (Index 76h)
Reg
Num
Nmne
015
014
013 012
011
010
76h
MiseControl llits
OAC
Z
(PMl
X
X
OMS
OI5R X
OAM
09
08
07
06
ALSR
MOO
EN
SRXI0 SRXS
07
07
04
03
02
01
00
Oefauh
X
X
ORSR
X
ARSR
OOOOh
05
OLE
ARSR
ADC right sample generator select
0 = SROSelected (32h)
1 = SRI Selected (2Ch).
DRSR
DAC right sample generator select
0 = SROSelected (32h)
1 = SRI Selected (2Ch).
SRX8D7
TE
Multiply
SRI rate by 8/7.
SRXIOD7
Multiply
SRI rate by 10/7. SRXIOD7
MODEN
Modem filter enable (left channel only).
ALSR
ADC left sample generator select
0 = SRO Selected (32h)
1 = SRI Selected (2Ch).
DLSR
DAC left sample generator select
0 = SROSelected (32h)
1 = SRI Selected (2Ch).
DMS
Digital Mono Select.
0 = Mixer
1 = Left DAC and Right DAc.
DAM
Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output.
and SRXSD7 are mutually exclusive; SRX1OD7 has priority if both are set.
Change only when DACs are powered down.
LPMIX
Low Power Mixer. Keeps CD to UNE_Our
DACZ
Zero fIll (vs. repeat)
Sample
ifDAC
is starved-for
alive for notebook
applications.
data.
Rate 0 (Index 78h)
Reg
Nwn Nmne
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
00
Oefaul
78h SatnpleRae 0 SRO15 SRO14 SRO13 SRO12 SROll SROI0 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SROI SROO BB80H
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48k.
SRO[I5:0]
REV. 0
Writing to this register allows the user to program the sampling frequency from 7 kHz (IB58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable
results.
-19-
ANALOGDEVICESfAX-ON-DEHAND
HOTLINE
-
Page
29
AD1881
Sample
Reg
Num
7Ah
Rate I (Index 7Ah)
Name
D15
D14
D13
DIZ
Dll
D9
DI0
Smnple Rate I SR11S SRll4 SR113 SR112 SKIll
SRllO SRI9
D8
D7
D6
DS
D4
D3
DZ
Dl
SRI8
SRI7
SRI6
SRIS
SRI4
SRB
SRU
SR11 SRIO 8880h
DO
Default
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample
rates are reset to 48k.
SRI [15:0]
Writing to this register allows the user to program the sampling frequency from 7 kHz (IB58h) to 48 kHz (BBSOh)
in I Hertz increments. Programming a value greater than 4S kHz or less than 7 kHz may cause unpredictable
results.
Vendor ID Registers (Index 7Ch-7Eh)
OBS
Reg
Nun>
7Ch
Name
Vendor
IDI
DlS
D14
D13
D12
Dll
DI0
D9
D8
D7
D6
DS
D4
D3
DZ
01
00
Default
F7
F6
FS
F4
F3
F2
FI
FO
S7
86
85
84
83
8Z
SI
SO
4144h
OLE
S[7:0]
This register is ASCII encoded
to "A."
F[7:0]
This register is ASCII encoded
to "D."
Reg
Name
Nun>
7Eh
DI5
Vendor 102 T7
014
DB
012
011
010
09
08
07
06
05
04
03
02
T6
TS
T4
T3
T2
TI
TO
REV7
REV6
REVS
REV4
REV3
REV2
T[7:0]
This register is ASCII encoded to "S."
REV [7:0]
Revision Register field contains the revision number.
These bits are read-only and should be verified before accessing vendor defmed features.
AD1819/AD1819A/ADl881USER-VISIBLE
- Supports
3.3 V digital VDD
DIFFERENCES
(as well as 5 V).
Register Differences
-
01
00
Oefuul
TE
REVI
REVO S3K..Xh
Reserved register bits always yield zero when read.
- Writes to odd registers have no effect, instead of writing preceding even register. Reads of odd registers always retum zero instead
of value of preceding even register.
- Writing ones to bits 5 or 13 ofregister 02h no longer forces bits 4:0 or 12:S to ones.
- Registers 04h and OSh are now reserved.
- It is no longer required that the mixer not be powered down in order to power up the DACs, and the mixer can be powered down
without also powering down the DACs.
- Aliases 2Ch (7Ah) and 32h (7Sh) have been added with AC '97 2.0 behavior.
- Registers 2Sh and 2Ah have been added; writing a zero to the LSB of register 2Ah resets registers 2Ch (7Ah) and 32h (7Sh).
- Register 76h default value is 0404h instead of OOOOh;DAM, DMS and LPMIX bits have been added.
- LSB of register 7Eh is 40h instead of 00h-o3h.
Analog Differences
- CD to LINE_Our path noninverting instead of inverting.
- Mixer feed through when powered off eliminated.
-20-
REV. 0
ANALOGDEVICESfAX-ON-DEMAND
HOTLINE
- Page 38
AD1881
APPLICATIONS
CIRCUITS
The AD1881 has been designed to require a minimum amount of external circuitry. The recommended applications circuits are
shown in Figures 9 and 10. Reference designs for the AD1881 are available and may be obtained by contacting your local Analog
Devices' sales representative or authorized distributor. Example shell programs for establishing a communications path between the
ADl881 and an ADSP-21xx are also available.
+5AVoo
+J.JDVoo
10p,F ,-
D
1.J7kJl
-, 10p,F
~
1 ODnF
DVOD1
uunn
OBS
D
D
D
D
D
D
D
D
DC>
DD-
DVOD2
DVSS1
~n~:~J~
II-
O.JJp,F
-If
O.JJ~
IIO.JJp,F
-If
RESET
SDATA_OUT
OLE
O.JJ~
!
O.JJ~
-II
O.JJ~
f
O.JJp,F
-I
O.JJ~
I
O.JJ~
--I"
O.JJ~
I~
O.JJp,F
-I"
O.JJp,F
SDATA_IN
DIGITAL GROUND
Figure 9. Recommended
One Codec Application
Circuit
AD1881
2.21kJl-
~
t o
=10mVRM~
(mean)
200Hz
8
DIGITAL
CONTROLLER
BIT_CLK
BOOZ
-
~
TE
O.JJ~
MIC
INPUT
'
5
AD1881
O.JJp,F
< FREQUENCY
RESPONSE
< 5kHz
@ -JdB
NOTES:
-MA Y NEED TO OPTIMIZE TO SUIT MICROPHONE
"SELECT
MIC1 AND MAX GAIN 20dB +12dB for 10mV
RMS MICROPHONE
OUTPUT.
Figure
REV. 0
DVSS2
~I
10. Microphone
-21-
~--
Input
ANALOGDEVICES FAX-ON-DEMAND HOTLINE
- Page
31
AD1881
OUTLINE
Dimensions
DIMENSIONS
shown in inches and (rnrn).
48-Lead Thin Plastic Quad Aatpack
(ST-48)
(LQFP)
D.D63 (1.6D) MAX
D.D3D (D'75).t..
D.D18(D.45)T"~
~
""
""
l?r
~
c!..
to
....
M
U
D.D57 (1.45)
D.D53 (1.35)
liP
SEATING
PLANE
OBS
D.DD6(D.15)
1'J':;1;
D.DD2(D.D5)-J~){D"
DO-7°*
.
MIN
~~
D.D19 (D.5)
BSC
D.DD7(D.18)
D.DD4(D.D9)
-..11.
D.D11 (D.27)
D.DD6 (D.17)
OLE
TE
~
vi
::i
~
(;)
~
z
iC
c..
-22-
REV.
0