TB62D612FTG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62D612FTG
24-Channel Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage Operation
The TB62D612FTG is a constant-current driver designed for LED and LED
display lighting.
The TB62D612FTG incorporates twenty-four channels of seven-bit PWM
dimming controllers and constant-current drivers. Twenty-four constant-current
drivers are divided into three blocks, each consisting of three drivers, and the
output current of each can be independently adjusted by the relevant external
resistor.
The TB62D612FTG is controlled using the SDA and SCLK input signals, and
capable of high-speed data transfers.
The TB62D612FTG can be set address with ID terminal. (Up to 64 address)
High-speed processing is capable by applying Bi-CMOS process.
The TB62D612FTG operates with a supply voltage of 3.3 V or 5 V.
P-WQFN36-0606-0.50-001
Weight: 0.083 g ( typ.)
1． Features
•
Power supply voltages: VCC = 3.3 V/5 V
•
Output drive capability and output count: 80 mA (max)× 24 channels
•
Constant-current output range: 5 to 40 mA
•
Voltage applied to constant-current output terminals: 0.4 V(min) (IOUT = 5 to 40 mA)
•
Designed for common-anode LEDs
•
The input interface is controlled by the SDA and SCLK signal lines
•
Thermal shutdown (TSD)
•
Logical Input signal voltage level: 3.3-V and 5-V CMOS interfaces (Schmitt trigger input)
•
Maximum output voltage: 28 V
•
Incorporating PWM control circuitry: Provides seven-bit PWM control.
•
Driver identification: Up to 64 drivers can be controlled individually.
•
Operating temperature range: Topr = −40 to 85 °C
•
Package: P-WQFN36-0606-0.50-001
•
Constant-current accuracy
Output Voltage
Current Accuracy
Between Channels
Current Accuracy
Between ICs
Output Current
0.4 V
±3.0%
±6.0%
15 mA
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TB62D612FTG
19 Rext-G
20 Rext-B
21 GND
22 ID0
23 ID1
24 ID2
25 Vcc
26 SDA
27 SCLK
2．Pin Assignment (top view)
28
18
Rext-R
/OUTR0 29
17
/OUTB7
30
16
/OUTG7
/OUTB0 31
15
/OUTR7
14
/OUTB6
/OUTG1 33
13
/OUTG6
34
12
/OUTR6
/OUTR2 35
11
/OUTB5
/OUTG2 36
10
/OUTG5
3
4
5
/OUTG3
/OUTB3
PGND
/OUTR5 9
2
/OUTR3
/OUTB4
1
/OUTB2
/OUTB1
8
TOP VIEW
/OUTR1 32
/OUTG4 7
/OUTG0
/OUTR4 6
RESET
3．Block Diagram
ID0 ID1 ID2
Rext-R
Vcc
Adress
Configration
RESET
SDA
SCLK
GND
Logic
Processing
CLK
Generation
Data
Buffer
PWM(7bit)
ConstantCurrent Driver
/OUTR0
PWM(7bit)
ConstantCurrent Driver
/OUTR7
PWM(7bit)
ConstantCurrent Driver
PWM(7bit)
ConstantCurrent Driver
PWM(7bit)
ConstantCurrent Driver
TSD
PWM(7bit)
Rext-G
2
ConstantCurrent Driver
/OUTG0
/OUTG7
/OUTB0
/OUTB7
Rext-B
PGND
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TB62D612FTG
4．Terminal Description
Pin No
Symbol
Function
1
/OUTB2
Constant-current output terminal (Open-collector type)
2
/OUTR3
Constant-current output terminal (Open-collector type)
3
/OUTG3
Constant-current output terminal (Open-collector type)
4
/OUTB3
5
PGND
6
/OUTR4
Constant-current output terminal (Open-collector type)
7
/OUTG4
Constant-current output terminal (Open-collector type)
8
/OUTB4
Constant-current output terminal (Open-collector type)
9
/OUTR5
Constant-current output terminal (Open-collector type)
10
/OUTG5
Constant-current output terminal (Open-collector type)
11
/OUTB5
Constant-current output terminal (Open-collector type)
12
/OUTR6
Constant-current output terminal (Open-collector type)
13
/OUTG6
Constant-current output terminal (Open-collector type)
14
/OUTB6
Constant-current output terminal (Open-collector type)
15
/OUTR7
Constant-current output terminal (Open-collector type)
16
/OUTG7
Constant-current output terminal (Open-collector type)
17
/OUTB7
Constant-current output terminal (Open-collector type)
18
Rext-R
External resistor pin for output current configuration (/OUTR0 to /OUTR7)
19
Rext-G
External resistor pin for output current configuration (/OUTG0 to /OUTG7)
20
Rext-B
21
GND
22
ID0
ID configuration pin (Note 1)
23
ID1
ID configuration pin (Note 1)
24
ID2
ID configuration pin (Note 1)
25
Vcc
Power supply terminal
26
SDA
Serial data input terminal
27
SCLK
Serial clock input terminal
28
RESET
Reset signal input. (Setting this pin High resets internal data.) (Note 1)
29
/OUTR0
Constant-current output terminal (Open-collector type)
30
/OUTG0
Constant-current output terminal (Open-collector type)
31
/OUTB0
Constant-current output terminal (Open-collector type)
32
/OUTR1
Constant-current output terminal (Open-collector type)
33
/OUTG1
Constant-current output terminal (Open-collector type)
34
/OUTB1
Constant-current output terminal (Open-collector type)
35
/OUTR2
Constant-current output terminal (Open-collector type)
36
/OUTG2
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Power Ground pin
External resistor pin for output current configuration (/OUTB0 to /OUTB7)
Ground pin
Note 1: After the reset is released, it should be ensured that IDs (slave addresses) are properly configured.
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TB62D612FTG
5．Equivalent Circuits for Inputs and Outputs
RESET Terminals
SDA and SCLK Terminals
Vcc
Vcc
SDA
SCLK
RESET
GND
GND
Constant-Current Output Terminals
ID0, ID1, and ID2 Terminals
Vcc
/OUTR0 to /OUTR7
/OUTG0 to /OUTG7
/OUTB0 to /OUTB7
ID0
ID1
ID2
Comparison
↓
PGND
GND
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TB62D612FTG
6．Programming the TB62D612FTG
The TB62D612FTG can be programmed by the SDA and SCLK signals.
The TB62D612FTG should be programmed using one of the following formats: (1) Serial Packet Format in Normal Programming
Mode or (3) Serial Packet Format in Special Mode.
(1) Serial Packet Format in Normal programming Mode
【Typical】
Start Command
[11111111]
Sub-address
(Channel select)
8 bits
Slave address
8 bits
Data byte
(PWM configuration)
8 bits
Period Command
[10000001]
・Normal programming Mode should be set as the following flow.
“Start Command” Æ “Slave address” Æ “Sub-address” Æ “Data byte” Æ “Period Command”
As for example of data input, refer to Page8.
・Input data from SDA signal is written to the shift register at the rising edge of SCLK every 8 bit.
This data is transferred at the falling edge of the eighth CLK. So, at the eighth CLK, data should be inputted to the falling edge.
Block diagram of data setting part
Data is transferred at
the falling edge of the
eighth SCLK.
8ビット
8 bit
counter
カウンタ
ＯＵＴ
R0
8bit
ＯＵＴ
G0
8bit
ＯＵＴ
B0
8bit
Data
Byte
ＯＵＴ
R1
ＯＵＴ
B6
8bit
ＯＵＴ
R7
ＯＵＴ
G7
ＯＵＴ
B7
8bit
8bit
8bit
8bit
Terminal command
終了コマンド
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
Data
ﾃﾞｰﾀﾊﾞｲﾄ
Byte
R0
R0
Data
ﾃﾞｰﾀﾊﾞｲﾄ
Byte
G0
G0
Data
ﾃﾞｰﾀﾊﾞｲﾄ
Byte
B0
B0
Data
ﾃﾞｰﾀﾊﾞｲﾄ
Byte
R1
R1
Data
ﾃﾞｰﾀﾊﾞｲﾄ
Byte
B6
Data
ﾃﾞｰﾀﾊﾞｲﾄ
Byte
R7
R7
Data
ﾃﾞｰﾀﾊﾞｲﾄ
Byte
G7
G7
Data
ﾃﾞｰﾀﾊﾞｲﾄ
Byte
B7
B7
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
サブアドレス
Sub
Address
8bit
Slave
Address
スレーブアドレス
8bit
SDA
8ビットシフトレジスタ
8bit
shift-resister
Shift-register
SCLK
Data is written to the shift register at the
rising edge of the SCLK.
In case of period command
Data is transferred at
the falling edge of the
eighth SCLK.
SDA
SCLK
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TB62D612FTG
(2) Data Settings
a) Slave Addresses
Input voltages and logic states of the ID0, ID1 and ID2 pins are determined as follows.
(High order bit = 0. Low order bit = 0 (Except of all selection))
Vcc =”11”, 2/3Vcc =”10”, 1/3Vcc = "01”, GND =”00”
Slave Addresses
ID2
ID1
ID0
00000000
GND
GND
GND
00000010
GND
GND
1/3Vcc
00000100
GND
GND
2/3Vcc
00000110
GND
GND
Vcc
00001000
GND
1/3Vcc
GND
00001010
GND
1/3Vcc
1/3Vcc
00001100
GND
1/3Vcc
2/3Vcc
00001110
GND
1/3Vcc
Vcc
00010000
GND
2/3Vcc
GND
00010010
GND
2/3Vcc
1/3Vcc
00010100
GND
2/3Vcc
2/3Vcc
00010110
GND
2/3Vcc
Vcc
00011000
GND
Vcc
GND
00011010
GND
Vcc
1/3Vcc
00011100
GND
Vcc
2/3Vcc
00011110
GND
Vcc
Vcc
00100000
1/3Vcc
GND
GND
00100010
1/3Vcc
GND
1/3Vcc
00100100
1/3Vcc
GND
2/3Vcc
00100110
1/3Vcc
GND
Vcc
00101000
1/3Vcc
1/3Vcc
GND
00101010
1/3Vcc
1/3Vcc
1/3Vcc
00101100
1/3Vcc
1/3Vcc
2/3Vcc
00101110
1/3Vcc
1/3Vcc
Vcc
00110000
1/3Vcc
2/3Vcc
GND
00110010
1/3Vcc
2/3Vcc
1/3Vcc
00110100
1/3Vcc
2/3Vcc
2/3Vcc
00110110
1/3Vcc
2/3Vcc
Vcc
00111000
1/3Vcc
Vcc
GND
00111010
1/3Vcc
Vcc
1/3Vcc
00111100
1/3Vcc
Vcc
2/3Vcc
00111110
1/3Vcc
Vcc
Vcc
01000000
2/3Vcc
GND
GND
01000010
2/3Vcc
GND
1/3Vcc
01000100
2/3Vcc
GND
2/3Vcc
01000110
2/3Vcc
GND
Vcc
01001000
2/3Vcc
1/3Vcc
GND
01001010
2/3Vcc
1/3Vcc
1/3Vcc
01001100
2/3Vcc
1/3Vcc
2/3Vcc
01001110
2/3Vcc
1/3Vcc
Vcc
01010000
2/3Vcc
2/3Vcc
GND
01010010
2/3Vcc
2/3Vcc
1/3Vcc
01010100
2/3Vcc
2/3Vcc
2/3Vcc
01010110
2/3Vcc
2/3Vcc
Vcc
01011000
2/3Vcc
Vcc
GND
01011010
2/3Vcc
Vcc
1/3Vcc
01011100
2/3Vcc
Vcc
2/3Vcc
01011110
2/3Vcc
Vcc
Vcc
01100000
Vcc
GND
GND
01100010
Vcc
GND
1/3Vcc
01100100
Vcc
GND
2/3Vcc
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TB62D612FTG
01100110
01101000
01101010
01101100
01101110
01110000
01110010
01110100
01110110
01111000
01111010
01111100
01111110
0XXXXXX1
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
GND
1/3Vcc
1/3Vcc
1/3Vcc
1/3Vcc
2/3Vcc
2/3Vcc
2/3Vcc
2/3Vcc
Vcc
Vcc
Vcc
Vcc
All Select
Vcc
GND
1/3Vcc
2/3Vcc
Vcc
GND
1/3Vcc
2/3Vcc
Vcc
GND
1/3Vcc
2/3Vcc
Vcc
b) Sub-Addresses
Output channel set / All channels set / Special mode set
In output channel set, a channel which defines PWM configuration is selected. In all channels set, PWM is configured for all
channels. Special mode sets this mode according to the description in page 8.
7bit
6bit
5bit
4bit
3bit
2bit
1bit
0bit
Ch set
0
0
0
0
0
0
1
0
/OUTR0
0
0
0
0
0
1
0
0
/OUTG0
0
0
0
0
0
1
1
0
/OUTB0
0
0
0
0
1
0
0
0
/OUTR1
0
0
0
0
1
0
1
0
/OUTG1
0
0
0
0
1
1
0
0
/OUTB1
0
0
0
0
1
1
1
0
/OUTR2
0
0
0
1
0
0
0
0
/OUTG2
0
0
0
1
0
0
1
0
/OUTB2
0
0
0
1
0
1
0
0
/OUTR3
0
0
0
1
0
1
1
0
/OUTG3
0
0
0
1
1
0
0
0
/OUTB3
0
0
0
1
1
0
1
0
/OUTR4
0
0
0
1
1
1
0
0
/OUTG4
0
0
0
1
1
1
1
0
/OUTB4
0
0
1
0
0
0
0
0
/OUTR5
0
0
1
0
0
0
1
0
/OUTG5
0
0
1
0
0
1
0
0
/OUTB5
0
0
1
0
0
1
1
0
/OUTR6
0
0
1
0
1
0
0
0
/OUTG6
0
0
1
0
1
0
1
0
/OUTB6
0
0
1
0
1
1
0
0
/OUTR7
0
0
1
0
1
1
1
0
/OUTG7
0
0
1
1
0
0
0
0
/OUTB7
0
1
0
0
0
0
0
0
All channel select
0
1
1
0
0
0
0
0
Special mode
(Bits of high order and low order must be zero.)
c) Data Bytes (PWM configuration)
Data bytes set PWM diming. (Low order bit must be zero.)
7bit
6bit
5bit
4bit
3bit
2bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1bit
0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Note: Any data other than those specified above must not be programmed.
7
0bit
0
0
0
0
0
PWM Dimming (for reference only)
OFF(Default)
1/127
2/127
・・・
126/127
127/127
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TB62D612FTG
(3) Serial Packet Format in Special Mode
When data of 01100000 is input to the sub address, the operation moves to the special mode where all channels are selected in
order. Data of 24 channels should be input.
(If data of more than 24 channels are provided, the 25th and subsequent data are treated as invalid. If data of less than 24
channels are provided, those data are written to the channels in order and the remaining channels retain the previous data.)
To return to the normal mode, input data from the start command (ALL”H”8bit). In case of using this mode configuration, volume of
data can be omitted.
Start
Condition
[11111111]
Slave
Addresses
Sub-address
Data
Data
Data
Data
(Special mode set）
OUTR0
OUTG0
OUTB0
OUTR1
[01100000]
Data
Data
Data
Data
OUTB6 OUTR7 OUTG7 OUTB7
Period
Command
[10000001]
(4) Input example of data set
a) In case 127 PWM clocks/127(100% ON) are configured to all channels of slave address 00h.
Start
command
(11111111)
Slave address Sub address(R0)
(00000010)
(00000000)
Sub address(R1) Data bytes
(00001000)
(11111110)
Data bytes
(11111110)
Sub address(G1) Data bytes
(00001010)
(11111110)
Sub address(G7) Data bytes
(11111110)
(00101110)
Sub address(B7)
(00110000)
Sub address(G0) Data bytes
(00000100)
(11111110)
Sub address(B1) Data bytes
(11111110)
(00001100)
Data bytes
(11111110)
Sub address(B0) Data bytes
(00000110)
(11111110)
Sub address(R7)
(00101100)
Data bytes
(11111110)
Period command
(10000001)
b) In case 127 PWM clocks/127(100% ON) are configured to only /OUTR0 pin and /OUTB7 pin of slave address 02h.
Start
command
(11111111)
Slave
Addresses
(00000010)
Sub-address
(R0)
(00000010)
Data bytes
(11111110)
Sub-address
(B7)
(00110000)
Data bytes
(11111110)
Period
Command
(10000001)
As for other than /OUTR0 and /OUTB7 terminals in above configuration, output pins which have already outputted data continue to
output prior data. (In case of changing only outputting data which is required to be changed, this configuration is valid.)
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TB62D612FTG
(5) Data settings and Timing of outputs
Counter max.
Prior data
Period
command
No
Yes
Data transfer
Note）Data is transferred by synchronizing period command (10000001) with the internal PWM counter (MAX). So, if data is inputted after the period command is inputted and
before the internal PWM counter counts its maximum, data which is inputted after period input is not accepted. In order to set data to the same ID (IC), next data should be
inputted after 3 ms which corresponds to 128 internal PWM clocks is passed since the period command is inputted. However, in order to set data to the different ID,
terminal of 3 ms which corresponds to 128 internal PWM clocks should not be taken. Data is written to the shift register at the rising edge of SCLK every 8 bits, and is
transferred at the falling edge of eighth CLK. So, data should be inputted to the falling edge at the eighth CLK.
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TB62D612FTG
(6) Example of data input to the same ID
a)
In case data A is inputted up to the rising edge of 127 internal PWM clocks.
Transferring data A
Internal PWM clock
Pattern 1
Start Data A Period
127
Start output
1
1
127
Input invalid term
Data A output
Outputting data A starts at the rising edge of one internal PWM clock.
Inputting is invalid from the rising edge of 127 internal PWM clocks to the rising edge of one internal PWM clock which is just
after these 127 PWM clocks.
b) In case data A is inputted after the rising edge of 127 internal PWM clocks.
Start output
Transferring data A
Internal PWM clock
Pattern 2
127
Start Data A Period
1
1
127
Input invalid term
Data A output
Outputting data A does not start at the rising edge of one internal PWM clock just after the data A is inputted. It starts at the
next rising edge of one internal PWM clock.
Inputting is invalid from the data A (period) input to the rising edge of after the next one internal PWM clock.
c) In case data B is inputted after data of pattern 1 starts outputting.
Transferring data A
Internal PWM clock
Pattern 3
127
Start output
Transferring data B
1
Start output
1
127
Input invalid term
Input invalid term
Start Data A Period
Start Data B Period
Data B output
Data A output
Outputting data A starts at the rising edge of one internal PWM clock just after the data A is inputted. Outputting data B starts at
the rising edge of one internal PWM clock which is just after the data B input.
Inputting is invalid in the following term.
From the rising edge of 127 internal PWM clocks which are just after the data A is inputted to the rising edge of one internal
PWM clock which is just after these 127 clocks.
From the rising edge of 127 internal PWM clocks which is just after the data B input to the rising edge of one internal PWM
clock which is just after these 127 clocks.
Pay attention that the IC does not operate according to the configuration while the following patterns (patterns 4 and 5) are
inputted.
d) In case data B is inputted by the time the output of pattern 2 starts.
Transferring data A
Internal PWM clock
127
127
1
Input invalid term
Pattern 4
Start Data APeriod
Start output
1
Start Data B Period
Data A output
Inputting is invalid from the data A (period) input to the rising edge of the second internal clock. So, data B is invalid and data A
is outputted.
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TB62D612FTG
e) In case the period command mistakes.
Transferring data B
Internal PWM clock
Pattern 5
1
127
Start Data A
Start output
1
127
Start Data B Period
Input invalid term
Data B output
Outputting data A does not start at the rising edge of one internal clock which is just after the data A input. Outputting data B
starts at the rising edge of one internal PWM clock which is just after the data B input.
(7) Example of data input to the different ID.
a) In case the data B is inputted to slave (= 02h) just after the data A is inputted to slave (= 00h).
Transferring data A and data B. Start output
Internal PWM clock
Pattern 6
Start
Slave=00h, Data A
1
127
Period Start
Slave=002h, Data B Period
Slave=00h output
Data A output
Slave=02h output
Data B output
Both data A and data B are outputted at the rising edge of one internal PWM clock which is just after the data A and the data B
inputs.
Pay attention that the IC does not operate according to the configuration while following patterns (patterns 7 and 8) are inputted.
b) In case period command after inputting data A to the slave (=00h) is missed or omitted or in case period command after
inputting data B to the slave (=02h) is missed or omitted.
Transferring data A
Internal PWM clock
Pattern 7
Start
Slave=00h, Data A
Start output
1
127
Start
Slave=02h, Data B
Data A output
Slave=00h output
Slave=02h output
Data A is outputted. Data B is not outputted.
c) In case start command is inputted after data B of pattern 7 is inputted.
Transferring data A
Internal PWM clock
Pattern 8
Start
Slave=00h, Data A
127
Start
Slave=02h, Data B
Start output
0
Start
Data A output
Slave=00h output
Slave=02h output
Data A is outputted. Data B is not outputted.
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TB62D612FTG
7. Power-ON Reset (POR)
The POR circuitry resets all the internal data to the default values upon powering up the TB62D612FTG in order to
ensure proper device operation.
The POR circuitry is only activated when Vcc rises from 0 V. To reactivate POR, Vcc must be powered down to 0 V. The
internal data hold voltage is guaranteed after Vcc has once reached or exceeded 3.0 V.
Initial Clear
Vcc Waveform
Reset Completion Voltage
2.0 V
Minimum Data Hold Voltage
1.8 V
POR Completed
0V
POR Active
POR Not Active
POR Active
8. Thermal Shutdown (TSD)
When the die temperature reaches 150 °C , the thermal shutdown circuit is tripped, switching the constant-current outputs to off.
The constant-current outputs are automatically turned on when the temperature cools past the shutdown threshold.
TSD trip temperature: 150 °C to 180 °C
TSD recovery temperature: 30 °C below the TSD trip temperature
*Please avoid positively using TSD because TSD is a detecting function of the product.
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9. Points to Note when Setting Up the TB62D612FTG
1.
External resistors for specifying the LED driving current (Rext-R, Rext-G, Rext-B)
External resistors should be separately connected to the Rext-R, Rext-G and Rext-B pins. Three resistors must not be
collectively connected to a single pin. If they are connected to a single pin, current error is generated in each RBG.
2.
External resistors for ID configuration
The total resistance value of three external resistors used for specifying a device ID (which are connected between Vcc and
GND) should be about 30 kΩ or lower.
3.
ID configuration sequence
ID configuration can be performed after POR is released upon powering on. However, to avoid false operation of the ID
configuration, transient input signals of less than two clock cycles of the reference clock for the internal oscillator are not
accepted.
Vcc
2V
ID Configuration Not Allowed
1.8V
ID Configuration Allowed
ID Configuration Not Allowed
Care should be taken during the period between the POR released timing and
the timing when power supply has reached the rated Vcc voltage.
4.
ID configuration
Make sure to set IDs after releasing reset condition.
5．Data configuration
Do not input the data which is not on the list of the data configuration table in page 6 and 7.
Data is written to the shift resister at the rising edge of SCLK every 8 bits. And data is transferred at the falling edge of the
eighth clock. So, input data to the falling edge at the eighth clock.
6．Special mode
Data which corresponds to 24 channels should be inputted. If data of more than 24 channels are provided, the 25th and
subsequent data are treated as invalid. If data of less than 24 channels are provided, those data are written to the channels
in order and the remaining channels retain the previous data.
７．Timing of data configuration
In order to set data to the same slave address, next data should be inputted after３ms which corresponds to 127 internal
PWM clocks is passed since the period command is inputted. However, in order to set data to the different slave address,
terminal of 3 ms which corresponds to 127 internal PWM clocks should not be taken.
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10. State Transition Diagram
Power-ON
↓
Vcc reaches the POR release threshold voltage.
↓
ID specified by the master matches that of the TB62D612FTG
RESET=”H”
RESET=”L”
After the TB62D612FTG is powered on, data
can be programmed only after 15 ms has
Normal Mode
Output data is programmed for each ID device using
the DATA and CLK signals for providing dimming
control
Please refer the description from page 5 to 11 in
details.
Exceeds the TSD
Cools past the TSD
trip threshold
release threshold
temperature
temperature
/RESET=”H”
/RESET=”L”
Compares IDs again
Reset Mode
Internal data（ID/PWM data）are reset.
/RESET = ”H”:
Data is reset forcedly.
Output is turned off.
Operation moves to low consumption
mode.
TSD Mode (Thermal Shutdown)
When the die temperature exceeds the
TSD trip threshold temperature, all the
outputs are disabled, while internal
data is retained.
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11．Absolute Maximum Ratings (Ta = 25℃)
Characteristics
Symbol
Rating
Unit
Supply voltage
VCC
6.0
V
Input voltage
VIN
-0.3 to Vcc + 0.3 (Note 1)
V
Output current
IOUT
85
mA/ch
Output voltage
VOUT
-0.3 to 29
V
Pd
4.3 (Notes 2 and 3)
W
Rth (j-a)
29 (Note 2)
°C /W
Operating temperature range
Topr
-40 to 85
°C
Storage temperature range
Tstg
−55 to 150
°C
Tj
150
°C
Power dissipation
Thermal resistance
Maximum junction temperature
Note 1:
However, do not exceed 6.0 V.
Note 2:
When mounted on a PCB (76.2 × 114.3 × 1.6 mm; Cu = 30%; 35-μm-thick; SEMI-compliant)
Note 3:
Power dissipation is reduced by 1/Rth (j-a) for each °C above 25 °C ambient.
12．Operating Ranges (Ta = 40℃ to 85℃, unless otherwise specified)
Characteristics
Symbol
Test condition
Min
Typ.
Max
Unit
Supply voltage
VCC
⎯
3
⎯
5.5
V
Output voltage
VOUT (ON)
All Output
0.4
⎯
4
V
Output current
IOUT
All Output
5
⎯
40
mA/ch
0.7 ×
Vcc
⎯
Vcc
VIL
GND
⎯
0.3 ×
Vcc
VID0
0
⎯
0.3
VID1
1/3Vcc
-0.3
1/3
Vcc
1/3Vcc
+0.3
2/3Vcc
-0.3
2/3
Vcc
2/3Vcc
+0.3
Vcc －
0.3
⎯
Vcc
⎯
⎯
10
VIH
SDA, SCLK, RESET
Input voltage
ID0, ID1, ID2
VID2
VID3
SCLK clock frequency
fCLK
SCLK
(Note. 4)
Data setup time
tSU;DAT
SDA-SCLK
(Note. 4)
10
⎯
⎯
Data hold time
tHD;DAT
SCLK-SDA
(Note. 4)
10
⎯
⎯
“L” term of SCLK clock
tLOW
SCLK
(Note. 4)
50
⎯
⎯
“H” term of SCLK clock
tHIGH
SCLK
(Note. 4)
50
⎯
⎯
V
MHz
ns
Note. 4: Please refer to below timing chart.
fCLK
tHIGH
50%
SCLK
tSU;DAT
SDA
50%
tLOW
50%
50%
tHD;DAT
50%
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TB62D612FTG
13．Electrical Characteristics (Ta = 25℃, VCC = 4.5 to 5.5 V, unless otherwise specified)
Characteristics
Output current
Output current accuracy between
channels
Output leakage current
Input current
Changes in constant output current
dependent on VCC
Symbol
Test
Circuit
IOUT1
4
ΔIOUT2
Min
Typ.
Max
Unit
VOUT = 0.4 V, R-EXT = 1.2k Ω
Vcc = 5 V,
12.69
13.5
14.31
mA
4
VOUT = 0.4 V, R-EXT =1.2k Ω
All ch ON Vcc = 5 V,
⎯
⎯
±3.0
%
IOZ
4
VOUT = 28 V
⎯
⎯
1
μA
IIH
1
SDA, SCLK
―
―
1
RESET(Vcc=5V)
25
50
75
IIL
2
SDA, SCLK, RESET
―
―
-1
IID
1,2
ID0, ID1, ID2
―
―
±0.1
%/Vcc
4
Vcc = 4.5 V to 5.5 V
⎯
1
2
Icc 1
3
R-EXT=1.2 k Ω ,VOUT =0.4 V,
RESET=L
⎯
9
14
Icc 2
3
R-EXT = OPEN, VOUT = 28.0 V
⎯
3
5
Icc (PS)
3
R-EXT = 1.2 k Ω , VOUT = 0.4 V,
RESET = H (The input current of the
RESET pin is excluded.)
⎯
⎯
1
μA
ー
Time between a High to Low
transition on RESET and the timing
when an output current is generated
after input data is applied.
⎯
⎯
3
ms
Supply current
Current consumption in Reset mode
Time required for a mode transition
from Reset mode to Normal mode
tON2 (*1)
Test Condition
μA
%
mA
(*1): Internal data is reset forcedly by RESET command. In order to turn on the output current, data should be inputted again.
Pay attention that the output current flows after PWM counter counts its maximum (128 PWM CLKs) though data is
inputted again.
RESET recovery time: 3ms (MAX) ←In case the voltage is inputted until the PWM counter counts one cycle after
RESET release. (After RESET release, PWM counter starts from zero.)
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14．Test Circuits
Test Circuit 1: High-Level Input Current (IIH)
VIN = VDD
A
Vcc
RESET
/OUTR0
SDA
SCLK
/OUTB7
ID0,1,2
A
GND
REXT
REXT
REXT
Rext-R Rext-G Rext-B
Vcc = 4.5~5.5 V
A
A
Test Circuit 2: Low-Level Input Current (IIL)
A
Vcc
RESET
/OUTR0
SDA
A
SCLK
/OUTB7
ID0,1,2
A
GND
REXT
REXT
REXT
Rext-R Rext-G Rext-B
Vcc = 4.5~5.5 V
A
Test Circuit 3: Supply Current
RESET
F.G
VIH = Vcc
VIL = 0 V
Vcc
/OUTR0
SDA
SCLK
/OUTB7
ID0
ID1
ID2
VID0 =0.3V
VID1 =1/3Vcc±0.3V
VID0 =2/3Vcc±0.3V
VID0 =Vcc-0.3V
Rext-R Rext-G Rext-B
REXT
REXT REXT
= 1.2k Ω =1.2k Ω =1.2k Ω
17
GND
Vcc = 4.5~5.5 V
ID set
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TB62D612FTG
Test Circuit 4: Output Current, Output Leakage Current, Output current accuracy,
Changes in constant output current dependent on VCC
RESET
VIH = Vcc
VIL = 0 V
F.G
Vcc
/OUTR0
A
/OUTG1
A
/OUTB7
A
SDA
SCLK
ID0
ID2
VID0 =0.3V
VID1 =1/3Vcc±0.3V
VID0 =2/3Vcc±0.3V
VID0 =Vcc-0.3V
Rext-R Rext-G Rext-B
GND
REXT
REXT REXT
= 1.2k Ω =1.2k Ω =1.2k Ω
Vcc = 4.5~5.5 V
ID1
VOUT = 0.4V, 28V
ID set
Test Circuit 5: Switching Characteristics
F.G
/OUTR0
CL
SDA
SCLK
IOUT
/OUTB7
ID0
ID Set
ID1
CL = 10.5 pF
ID2
VID0 =0.3V
VID1 =1/3Vcc±0.3V
VID0 =2/3Vcc±0.3V
VID0 =Vcc-0.3V
RL=300 Ω
Rext-R Rext-G Rext-B
REXT
REXT REXT
= 1.2k Ω =1.2k Ω =1.2k Ω
18
GND
Vcc = 4.5~5.5 V
VIH = Vcc
VIL = 0 V
Vcc
VL = 5V
RESET
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TB62D612FTG
15. Characteristics of Output Current vs. External resistor
(For reference)
Output
current – REXT
出力電流‐REXT 特性(Vcc=5.0V, Ta=25℃)
100
90
80
Output 出力電流[mA]
current
70
60
50
40
30
20
10
0
0.1
1
10
External resistor
外付け抵抗 REXT[kΩ]
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16．Application Circuit Example
VCC
00
01
10
11
VLED
ID=“00000000”
ID=“00100000”
ID0
ID1 ID2
/OUTR0
ID0
/OUTB7
TB62D612FTG
C.P.U.
Rext-B
/OUTB7
Vcc
SDA
Rext-G
/OUTR0
TB62D612FTG
Vcc
SDA SCLK
Rext-R
ID1 ID2
GND
SCLK
Rext-R
Rext-G
Rext-B
GND
SDA
SCLK
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TB62D612FTG
Package Dimensions
Unit: mm
P-WQFN36-0606-0.50-001
A
(Detail view of A)
Weight: 0.083 g (typ.)
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Examples
The application examples provided in this data sheet are provided for reference only. Thorough evaluation
and testing should be implemented when designing your application’s mass production design.
In providing these application examples, Toshiba does not grant the use of any industrial property rights.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
IC Usage Considerations
Notes on handling of ICs
(1)
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause breakdown, damage or deterioration of the device, and may result
in injury by explosion or combustion.
(2)
Use an appropriate power supply fuse to ensure that a large current does not continuously flow in the
event of over current and/or IC failure. The IC will fully break down when used under conditions that
exceed its absolute maximum ratings, when the wiring is routed improperly, or when an abnormal
pulse noise occurs from the wiring or load, causing a large current to continuously flow. Such a
breakdown can lead to smoke or ignition. To minimize effects of a large current flow in the event of
breakdown, fuse capacity, fusing time, insertion circuit location, and other such suitable settings are
required.
(3)
If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current caused by inrush current at
power ON or the negative current caused by the back electromotive force at power OFF. IC
breakdown may cause injury, smoke or ignition.
For ICs with built-in protection functions, use a stable power supply. An unstable power supply may
cause the protection function to not operate, causing IC breakdown. IC breakdown may cause injury,
smoke or ignition.
(4)
Do not insert devices incorrectly or in the wrong orientation.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and
exceeding the rating(s) may cause breakdown, damage or deterioration of the device, which may
result in injury by explosion or combustion.
In addition, do not use any device that has had current applied to it while inserted incorrectly or in
the wrong orientation even once.
(5)
Carefully select power amp, regulator, or other external components (such as inputs and negative
feedback capacitors) and load components (such as speakers),.
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TB62D612FTG
If there is a large amount of leakage current such as input or negative feedback capacitors, the IC
output DC voltage will increase. If this output voltage is connected to a speaker with low input
withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause
smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied
Load (BTL) connection type IC that inputs output DC voltage to a speaker directly.
Points to remember on handling of ICs
(1)
Heat Dissipation Design
In using an IC with large current flow such as a power amp, regulator or driver, please design the
device so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at
any time or under any condition. These ICs generate heat even during normal use. An inadequate IC
heat dissipation design can lead to decrease in IC life, deterioration of IC characteristics or IC
breakdown. In addition, please design the device taking into consideration the effect of IC heat
dissipation on peripheral components.
(2)
Back-EMF
When a motor rotates in the reverse direction, stops, or slows down abruptly, a current flows back to
the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power
supply is small, the device’s motor power supply and output pins might be exposed to conditions
beyond absolute maximum ratings. To avoid this problem, take the effect of back-EMF into
consideration in your system design.
(3)
Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal
shutdown circuits operate against the over temperature, clear the heat generation status
immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings
can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation.
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RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
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