AD AD9020JZ 10-bit 60 msps a/d converter Datasheet

a
FEATURES
Monolithic 10-Bit/60 MSPS Converter
TTL Outputs
Bipolar (61.75 V) Analog Input
56 dB SNR @ 2.3 MHz Input
Low (45 pF) Input Capacitance
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrared Systems
10-Bit 60 MSPS
A/D Converter
AD9020
FUNCTIONAL BLOCK DIAGRAM
MSB LSBS
INVERT INVERT
61
ANALOG IN
59
8
OVERFLOW
9
+V REF 12
+V SENSE 11
R/2
512
R
385
C
R/2
O
3/4 REF 7
R/2
384
M
D
51 OVERFLOW
P
R
E
50 D9 (MSB)
C
49 D8
A
R
R
O
257
A
R/2
1/2 REF 1
The AD9020 A/D converter is a 10-bit monolithic converter
capable of word rates of 60 MSPS and above. Innovative architecture using 512 input comparators instead of the traditional
1024 required by other flash converters reduces input capacitance and improves linearity.
L
48 D7
A
47 D6
T
46 D5
C
23 D4
H
22 D3
OVERFLOW
E
256
R
L
1024
10
R
O
L
21 D
2
G
R
129
A
20 D1
I
T
19 D0 (LSB)
C
R/2
1/4 REF 63
C
R/2
Encode and outputs are TTL-compatible, making the AD9020
an ideal candidate for use in low power systems. An overflow
bit is provided to indicate analog input signals greater than
+VSENSE.
Voltage sense lines are provided to insure accurate driving of the
± VREF voltages applied to the units. Quarter-point taps on the
resistor ladder help optimize the integral linearity of the unit.
D
O
R/2
GENERAL DESCRIPTION
OVERFLOW
T
128
H
E
R
S
R
2
R
1
R/2
–V SENSE 57
–VREF 56
ENCODE 14
Either 68-pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and are specifically designed for low thermal
impedances. Two performance grades for temperatures of both
0°C to +70°C and –55°C to +125°C ranges are offered to allow
the user to select the linearity best suited for each application.
Dynamic performance is fully characterized and production
tested at +25°C. MIL-STD-883 units are available.
–VS
+V S
GROUND
The AD9020 A/D Converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9020/883B data sheet for detailed
specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
.Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD9020–SPECIFICATIONS
3/4REF, 1/2REF, 1/4REF Current . . . . . . . . . . . . . . . . . . . ± 10 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature
AD9020JE/KE/JZ/KZ . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature2 . . . . . . . . . . . . . . . . +175°C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300°C
ABSOLUTE MAXIMUM RATINGS 1
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +2 V
+VREF, –VREF, 3/4REF, 1/2REF, 1/4REF . . . . . . . . . . –2 V to +2 V
+VREF to –VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
DIGITAL INPUTS . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +VS
ELECTRICAL CHARACTERISTICS (6V = 65 V; 6V
S
Parameter (Conditions)
Temp
Test
Level
RESOLUTION
SENSE
Min
= 61.75 V; ENCODE = 40 MSPS unless otherwise noted)
AD9020JE/JZ
Typ
Max
10
AD9020KE/KZ
Min
Typ
Max
Units
10
Bits
3
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Bias Current4
Input Resistance
Input Capacitance4
Analog Bandwidth
REFERENCE INPUT
Reference Ladder Resistance
Ladder Tempco
Reference Ladder Offset
Top of Ladder
Bottom of Ladder
Offset Drift Coefficient
SWITCHING PERFORMANCE
Conversion Rate
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Delay (tOD)5
Output Time Skew5
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Effective Number of Bits (ENOB)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz
Signal-to-Noise Ratio6
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz
Signal-to-Noise Ratio6
(Without Harmonics)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz
+25°C
Full
+25°C
Full
Full
I
VI
I
VI
VI
1.0
+25°C
Full
+25°C
+25°C
+25°C
I
VI
I
V
V
+25°C
Full
Full
I
VI
V
+25°C
Full
+25°C
Full
Full
I
VI
I
VI
V
+25°C
+25°C
+25°C
+25°C
+25°C
I
V
V
I
I
+25°C
+25°C
V
V
+25°C
+25°C
+25°C
I
IV
IV
8.6
8.0
7.5
9.0
8.4
8.0
+25°C
+25°C
+25°C
I
I
I
54
50
47
+25°C
+25°C
+25°C
I
I
I
54
51
48
1.25
0.4
2.0
7.0
45
175
22
14
37
1.25
1.5
2.0
2.5
0.75
1.0
1.25
1.0
1.5
2.0
Guaranteed
LSB
LSB
LSB
LSB
1.0
2.0
0.4
1.0
2.0
mA
mA
kΩ
pF
MHz
56
66
Ω
Ω
Ω/°C
90
90
90
90
50
mV
mV
mV
mV
µV/°C
1
5
10
3
MSPS
ns
ps, rms
ns
ns
56
66
2.0
7.0
45
175
22
14
37
0.1
45
45
0.1
90
90
90
90
45
45
50
60
6
60
1
5
10
3
13
5
6
10
10
–2–
13
5
10
10
ns
ns
8.6
8.0
7.5
9.0
8.4
8.0
Bits
Bits
Bits
56
53
50
54
50
47
56
53
50
dB
dB
dB
56
54
52
54
51
48
56
54
52
dB
dB
dB
REV. A
AD9020
Parameter (Conditions)
Temp
Test
Level
Min
I
I
I
61
55
49
AD9020JE/JZ
Typ
Max
DYNAMIC PERFORMANCE (continued)
Harmonic Distortion
+25°C
fIN = 2.3 MHz
+25°C
fIN = 10.3 MHz
+25°C
fIN = 15.3 MHz
Two-Tone Intermodulation
+25°C
Distortion Rejection7
Differential Phase
+25°C
Differential Gain
+25°C
V
V
V
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Pulse Width (High)
Pulse Width (Low)
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
I
I
DIGITAL OUTPUTS
Logic “1” Voltage (IOH = 2 mA)
Logic “0” Voltage (IOL = 6 mA)
Full
Full
VI
VI
+25°C
Full
+25°C
Full
+25°C
Full
I
VI
I
VI
I
VI
440
Full
VI
6
POWER SUPPLY
+VS Supply Current
–VS Supply Current
Power Dissipation
Power Supply Rejection
Ratio (PSRR)8
67
59
53
AD9020KE/KZ
Min
Typ
Max
Units
61
55
49
67
59
53
dBc
dBc
dBc
70
0.5
1
dBc
Degree
%
70
0.5
1
2.0
2.0
0.8
20
800
0.8
20
800
5
5
6
6
6
6
2.4
2.4
V
V
0.4
140
2.8
V
V
µA
µA
pF
ns
ns
530
542
170
177
3.3
3.4
440
10
6
140
2.8
530
542
170
177
3.3
3.4
mA
mA
mA
mA
W
W
10
mV/V
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: θJC = 1°C/W; θJA = 17°C/W (no air flow); θJA = 15°C/W
(air flow = 500 LFM). 68-pin ceramic LCC: θJC = 2.6°C/W; θJA = 15°C/W (no air flow); θJA = 13°C/W (air flow = 500 LFM).
3
3/4REF, 1/2REF, and 1/4REF reference ladder taps are driven from dc sources at +0.875 V, 0 V, and –0.875 V, respectively. Accuracy of the overflow comparator is not
tested and not included in linearity specifications.
4
Measured with ANALOG IN = +V SENSE.
5
Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D 0–D9. Output skew
measured as worst-case difference in output delay among D 0–D9.
6
RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.
7
Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8
Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +V S or –VS.
Specifications subject to change without notice.
REV. A
–3–
AD9020
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
Test Level
I
– 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature extremes for commercial/industrial devices.
Device
Temperature
Range
Description
Package
Option*
AD9020JZ
AD9020JE
AD9020KZ
AD9020KE
AD9020SZ/883
AD9020SE/883
AD9020TZ/883
AD9020TE/883
AD9020/PCB
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
0°C to +70°C
68-Pin Leaded Ceramic
68-Terminal Ceramic LCC
68-Pin Leaded Ceramic
68-Terminal Ceramic LCC
68-Pin Leaded Ceramic
68-Terminal Ceramic LCC
68-Pin Leaded Ceramic
68-Terminal Ceramic LCC
Evaluation Board
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
*E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
DIE LAYOUT AND MECHANICAL INFORMATION
+ 5.0V
Die Dimensions . . . . . . . . . . . . . . . 206 3 140 3 15 (± 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
0.1 µF
3,6,15,18,25,30,33,34,
37,40,45,52,55,65,68
100Ω
AD1
8
9
+VS
ANALOG IN
510Ω
D0 – D4
19
23
510Ω
AD2
14 ENCODE
D5 – D9
+2V
12 +VREF
–2V
56
46
51
510Ω
AD9020
_
VREF
59 LSBs INVERT
GROUND
61 MSB INVERT
–VS
4,5,13,17,
27,31,32,
36,38,39,
43,53,66,67
2,16,28,29,35,
41,42,54,64
STATIC: AD1 = –2V; AD2 = +2.4V
DYNAMIC: AD1 = ±2V TRIANGLE WAVE
AD2 = TTL PULSE TRAIN
0.1µF
–5.2V
AD9020 Burn-In Circuit
–4–
REV. A
ANALOG IN
ANALOG IN
3/4 REF
+VS
GND
GND
+VS
–V S
1/2 REF
+VS
GND
GND
+VS
–VS
1/4 REF
NC
MSB INVERT
AD9020
9
61
60
10
NC
+VSENSE
+VREF
GND
ENCODE
+V S
–V S
GND
+V S
(LSB) D 0
D1
D2
D3
D4
AD9020
TOP VIEW
(Not to Scale)
NC
+V S
NC
26
44
43
GND
–VS
–V S
+V S
GND
GND
+VS
+VS
–VS
GND
+V S
GND
GND
+VS
–VS
–VS
GND
27
NC
LSBs INVERT
NC
–V SENSE
–V REF
+VS
–V S
GND
+VS
OVERFLOW
D9 (MSB)
D8
D7
D6
D5
+VS
NC
NC = NO CONNECT
AD9020 PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1
1/2REF
Midpoint of internal reference ladder.
2, 16, 28, 29, 35, 41, 42,
54, 64
–VS
Negative supply voltage; nominally –5.0 V ± 5%.
3, 6, 15, 18, 25, 30, 33, 34,
37, 40, 45, 52, 55, 65, 68
+VS
Positive supply voltage; nominally +5 V ± 5%.
4, 5, 13, 17, 27, 31, 32,
36, 38, 39, 43, 53, 66, 67
GROUND
All ground pins should be connected together and to low impedance ground
plane.
7
3/4REF
Three-quarter point of internal reference ladder.
8, 9
ANALOG IN
Analog input; nominally between ± 1.75 V.
11
+VSENSE
Voltage sense line to most positive point on internal resistor ladder.
Normally +1.75 V.
12
+VREF
Voltage force connection for top of internal reference ladder. Normally driven
to provide +1.75 V at +VSENSE.
14
ENCODE
TTL-compatible convert command used to begin digitizing process.
19–23, 46–50
D0–D9
TTL-compatible digital output data.
51
OVERFLOW
TTL-compatible output indicating ANALOG IN > +VSENSE.
56
–VREF
Voltage force connection for bottom of internal reference ladder. Normally
driven to provide –1.75 V at –VSENSE.
57
–VSENSE
Voltage sense line to most negative point on internal resistor ladder.
Normally –1.75 V.
59
LSBs INVERT
Normally grounded. When connected to +VS, lower order bits (D0–D8) are
inverted.
61
MSB INVERT
Normally grounded. When connected to +VS, most significant bit (MSB; D9)
is inverted.
63
1/4REF
One-quarter point of internal reference ladder.
REV. A
–5–
AD9020
Receiver sensitivity is limited by the Signal-to-Noise Ratio of the
system. The SNR for an ADC is measured in the frequency domain and calculated with a Fast Fourier Transform (FFT). The
SNR equals the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the noise. The noise is
the sum of all other spectral components, including harmonic
distortion, but excluding dc.
THEORY OF OPERATION
Refer to the AD9020 block diagram. As shown, the AD9020
uses a modified “flash,” or parallel, A/D architecture. The analog input range is determined by an external voltage reference
(+VREF and –VREF), nominally ± 1.75 V. An internal resistor ladder divides this reference into 512 steps, each representing two
quantization levels. Taps along the resistor ladder (1/4REF,
1/2REF and 3/4REF) are provided to optimize linearity. Rated performance is achieved by driving these points at 1/4, 1/2 and 3/4,
respectively, of the voltage reference range.
The A/D conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. The value of the least significant bit (LSB) is determined by a unique interpolation scheme
between adjacent comparators. The decoding logic processes
the comparator outputs and provides a 10-bit code to the output
stage of the converter.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the result of imperfections in the device transfer function (nonlinearities, delay mismatch, varying input impedance, etc.). In
the ADC, these spurious signals appear as Harmonic Distortion.
Harmonic Distortion is also measured with an FFT and is specified as the ratio of the fundamental component of the signal
(rms amplitude) to the rms value of the worst case harmonic
(usually the 2nd or 3rd).
Two-Tone Intermodulation Distortion (IMD) is a frequently cited
specification in receiver design. In narrow-band receivers, thirdorder IMD products result in spurious signals in the pass band
of the receiver. Like mixers and amplifiers, the ADC is characterized with two, equal-amplitude, pure input frequencies. The
IMD equals the ratio of the power of either of the two input signals to the power of the strongest third-order IMD signal. Unlike mixers and amplifiers, the IMD does not always behave as it
does in linear devices (reduced input levels do not result in predictable reductions in IMD).
Flash architecture has an advantage over other A/D architectures because conversion occurs in one step. This means the
performance of the converter is primarily limited by the speed
and matching of the individual comparators. In the AD9020, an
innovative interpolation scheme takes advantage of flash architecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
These advantages occur by using only half the normal number
of input comparator cells to accomplish the conversion. In addition, a proprietary decoding scheme minimizes error codes. Input control pins allow the user to select from among Binary,
Inverted Binary, Twos Complement and Inverted Twos
Complement coding (see AD9020 Truth Table).
Performance graphs provide typical harmonic and SNR data for
the AD9020 for increasing analog input frequencies. In choosing an A/D converter, always look at the dynamic range for the
analog input frequency of interest. The AD9020 specifications
provide guaranteed minimum limits at three analog test
frequencies.
APPLICATIONS
Many of the specifications used to describe analog/digital converters have evolved from system performance requirements in
these applications. Different systems emphasize particular specifications, depending on how the part is used. The following applications highlight some of the specifications and features that
make the AD9020 attractive in these systems.
Aperture Delay is the delay between the rising edge of the ENCODE command and the instant at which the analog input is
sampled. Many systems require simultaneous sampling of more
than one analog input signal with multiple ADCs. In these situations, timing is critical and the absolute value of the aperture
delay is not as critical as the matching between devices.
Wideband Receivers
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence
and spectral analysis all place stringent ac performance requirements on analog-to-digital converters (ADCs). Frequency domain characterization of the AD9020 provides signal-to-noise
ratio (SNR) and harmonic distortion data to simplify selection
of the ADC.
Aperture Uncertainty, or jitter, is the sample-to-sample variation
in aperture delay. This is especially important when sampling
high slew rate signals in wide bandwidth systems. Aperture uncertainty is one of the factors that degrade dynamic performance
as the analog input frequency is increased.
–6–
REV. A
AD9020
Digitizing Oscilloscopes
Oscilloscopes provide amplitude information about an observed
waveform with respect to time. Digitizing oscilloscopes must accurately sample this signal, without distorting the information to
be displayed.
One figure of merit for the ADC in these applications is Effective
Number of Bits (ENOBs). ENOB is calculated with a sine wave
curve fit and equals:
ENOB = N – LOG2 [Error (measured)/Error (ideal)]
N is the resolution (number of bits) of the ADC. The measured
error is the actual rms error calculated from the converter outputs with a pure sine wave input.
The Analog Bandwidth of the converter is the analog input frequency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. The analog bandwidth is a good indicator of a converter’s stewing capabilities.
The Maximum Conversion Rate is defined as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.
Imaging
Visible and infrared imaging systems both require similar characteristics from ADCs. The signal input (from a CCD camera,
or multiplexer) is a time division multiplexed signal consisting of
a series of pulses whose amplitude varies in direct proportion to
the intensity of the radiation detected at the sensor. These varying levels are then digitized by applying encode commands at
the correct times, as shown below.
The actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. The low frequency test for
SNR or ENOB is a good measure of the noise of the AD9020.
At this frequency, the static errors in the ADC determine the
useful dynamic range of the ADC.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not important. The Transient Response and Overvoltage Recovery Time
specifications insure that the ADC can track full-scale changes
in the analog input sufficiently fast to capture a valid sample.
Transient Response is the time required for the AD9020 to
achieve full accuracy when a step function is applied. Overvoltage Recovery Time is the time required for the AD9020 to recover to full accuracy after an analog input signal 150% of full
scale is reduced to the full-scale range of the converter.
Professional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also requires high resolution ADCs for studio quality measurement
and frame storage.
The AD9020 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and analog bandwidth are suitable for digitizing both composite and
RGB video sources.
+FS
AIN
AD9020
– FS
ENCODE
Imaging Application Using AD9020
REV. A
–7–
AD9020
The select resistors (RS) shown in the schematic (each pair can
be a potentiometer) are chosen to adjust the quarter-point voltage references, but are not necessary if R1–R4 match within
0.05%.
USING THE AD9020
Voltage References
The AD9020 requires that the user provide two voltage references: +VREF and –VREF. These two voltages are applied across
an internal resistor ladder (nominally 37 Ω) and set the analog
input voltage range of the converter. The voltage references
should be driven from a stable, low impedance source. In addition to these two references, three evenly spaced taps on the resistor ladder (1/4REF, 1/2REF, 3/4REF) are available. Providing a
reference to these quarter points on the resistor ladder will improve the integral linearity of the converter and improve ac performance. (AC and dc specifications are tested while driving the
quarter points at the indicated levels.) The figure below is not
intended to show the transfer function of the ADC, but illustrates how the linearity of the device is affected by reference
voltages applied to the ladder.
An alternative approach for defining the quarter-point references of the resistor ladder is to evaluate the integral linearity
error of an individual device, and adjust the voltage at the
quarter-points to minimize this error. This may improve the low
frequency ac performance of the converter.
62
10.0
56
9.0
50
8.0
44
7.0
38
6.0
32
0.4
0.6
0.8
1.0
1.4
1.2
±VSENSE – Volts
1.6
1.8
EFFECTIVE NUMBER OF BITS (ENOB)
SIGNAL-TO-NOISE (SNR) – dB
Performance of the AD9020 has been optimized with an analog
input voltage of ± 1.75 V (as measured at ± VSENSE). If the analog input range is reduced below these values, relatively larger
differential nonlinearity errors may result because of comparator
mismatches. As shown in the figure below, performance of the
converter is a function of ± VSENSE.
5.0
2.0
AD9020 SNR and ENOB vs. Reference Voltage
Effect of Reference Taps on Linearity
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause permanent damage to the AD9020. The design of
the reference circuit should limit the voltage available to the
references.
Resistance between the reference connections and the taps of
the first and last comparators causes offset errors. These errors,
called “top and bottom of the ladder offsets,” can be nulled by
using the voltage sense lines, +VSENSE and –VSENSE, to adjust the
reference voltages. Current through the sense lines should be
limited to less than 100 µA. Excessive current drawn through
the voltage sense lines will affect the accuracy of the sense line
voltage.
Analog Input Signal
The signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Equivalent Analog Input figure).
This connection typically has an input resistance of 7 kΩ, and
input capacitance of 45 pF. The input capacitance is nearly
constant over the analog input voltage range, as shown in the
graph which illustrates that characteristic.
The next page shows a reference circuit which nulls out the offset errors using two op amps and provides appropriate voltage
references to the quarter-point taps. Feedback from the sense
lines causes the op amps to compensate for the offset errors.
The two transistors limit the amount of current drawn directly
from the op amps; resistors at the base connections stabilize
their operation. The 10 kΩ resistors (R1–R4) between the voltage sense lines form an external resistor ladder; the quarter
point voltages are taken off this external ladder and buffered by
an op amp. The actual values of resistors R1–R4 are not critical,
but they should match well and be large enough (≥10 kΩ) to
limit the amount of current drawn from the voltage sense lines.
The analog input signal should be driven from a low distortion,
low noise amplifier. A good choice is the AD9617, a wide bandwidth, monolithic operational amplifier with excellent ac and dc
performance. The input capacitance should be isolated by a
small series resistor (24 Ω for the AD9617) to improve the ac
performance of the amplifier (see AD9020/PCB Evaluation
Board Block Diagram).
–8–
REV. A
AD9020
+VSENSE
ANALOG INPUT
+5V
150Ω
1/2 AD708
+1.75V
+VREF 12
0.1µF
*
3/4REF
+VSENSE 11
R/2
R1
10kΩ
R
RS
+0.875V
RS
7
R/2
0.1µF
R2
10kΩ
R
RS
150Ω
0V
AD580
RS
R/2
1/2REF
1/2 AD708
1
R/2
0.1 µF
R
R3
10kΩ
1/4REF
TO COMPARATORS
R
+2.5V
+1.75V
356Ω
1/2 REF
R/2
3/4REF
1/2 AD708
R
–0.875V
–V SENSE
R/2
1/4REF 63
1/2 AD708
R/2
0.1 µF
R4
10kΩ
AD9020 Equivalent Analog Input
R
+VS
R
R
20kΩ
R/2
20kΩ
DIGITAL BITS
AND OVERFLOW
–VSENSE 57
–1.75V
–VREF 56
0.1µF
1/2 AD708
150Ω
*
*
= WIRING
RESISTANCE = < 5Ω
AD9020
–5V
AD9020 Equivalent Digital Outputs
AD9020 Reference Circuit
+ 5.0V
13k
ENCODE 14
AD9020 Equivalent Encode Circuit
REV. A
–9–
AD9020
ANALOG
INPUT
N
N+1
ta
N
N+1
ENCODE
tOD
DATA
OUTPUT
DATA FOR N
DATA FOR N + 1
ta – Aperture Delay
tOD – Output Delay
AD9020 Timing Diagram
Timing
Layout and Power Supplies
In the AD9020, the rising edge of the ENCODE signal triggers
the A/D conversion by latching the comparators. (See the
AD9020 Timing Diagram.)
Proper layout of high speed circuits is always critical but is particularly important when both analog and digital signals are
involved.
The ENCODE is TTL/CMOS compatible and should be driven
from a low jitter (phase noise) source. Jitter on the ENCODE
signal will raise the noise floor of the converter. Fast, clean
edges will reduce the jitter in the signal and allow optimum ac
performance. Locking the system clock to a crystal oscillator
also helps reduce jitter. The AD9020 is designed to operate with
a 50% duty cycle; small (10%) variations in duty cycle should
not degrade performance.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch.
Data Format
The format of the output data (D0–D9) is controlled by the
MSB INVERT and LSBs INVERT pins. These inputs are dc
control inputs, and should be connected to GROUND or +VS.
The AD9020 Truth Table gives information to choose from
among Binary, Inverted Binary, Twos Complement and Inverted Twos Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at +VSENSE. The accuracy of the
overflow transition voltage and output delay are not tested or included in the data sheet limits. Performance of the overflow indicator is dependent on circuit layout and slew rate of the
encode signal. The operation of this function does not affect the
other data bits (D0–D9). It is not recommended for applications
requiring a critical measure of the analog input voltage.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane, on the component side of the board, will reduce noise on the circuit ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow
designers to lay out signal traces without interrupting the
ground plane and provide low impedance power planes.
It is especially important to maintain the continuity of the
ground plane under and around the AD9020. In systems with
dedicated digital and analog grounds, all grounds of the
AD9020 should be connected to the analog ground plane.
The power supplies (+VS and –VS) of the AD9020 should be isolated from the supplies used for external devices; this further reduces the amount of noise coupled into the A/D converter.
Sockets limit the dynamic performance and should be used only
for prototypes or evaluation—PCK Elastomerics Part # CCS-6855 is recommended for the LCC package. (Tel. 215-672-0787)
An evaluation board is available to aid designers and provide a
suggested layout.
–10–
REV. A
AD9020
62
10.0
62
9.0
56
10.0
7.0
44
+55°C & +125°C
38
6.0
32
5.0
26
4.0
1
2
4
6 8 10
20
40 60
INPUT FREQUENCY – MHz
100
200
50
8.0
44
7.0
38
6.0
32
5.0
26
4.0
20
AD9020 SNR and ENOB vs. Input Frequency
1
2
4
6 8 10
20
40
CONVERSION RATE – MSPS
60
AD9020 SNR and ENOB vs. Conversion Rate
30
70
35
60
INPUT CAPACITANCE – pF
40
HARMONICS – dBc
100
+125 C
45
50
–55 C
+25 C
55
60
65
70
1
2
6 8 10
20
40
4
INPUT FREQUENCY – MHz
60
100
48
47
40
CAPACITANCE
46
30
45
20
44
10
–1.8
AD9020 Harmonics vs. Input Frequency
50
RESISTANCE
–1.2
+ 0.6
+1.2
–0.6
0
ANALOG INPUT (AIN ) – Volts
INPUT RESISTANCE – kΩ
20
EFFECTIVE NUMBER OF BITS (ENOB)
+25°C
9.0
ANALOG INPUT = 2.3MHz
SIGNAL-TO-NOISE (SNR) – dB
SIGNAL-TO-NOISE (SNR) – dB
8.0
50
EFFECTIVE NUMBER OF BITS (ENOB)
ENCODE RATE = 40MSPS
56
+1.8
Input Capacitance/Resistance vs. Input Voltage
AD9020 Truth Table
Step
Range
0 = –1.75 V
FS = +1.75 V
1024
1023
1022
•
•
•
512
511
510
•
•
•
02
01
00
> +1.7500
+1.7466
+1.7432
•
•
•
+0.0034
0.000
–0.0034
•
•
•
–1.7432
–1.7466
<–1.7466
Offset Binary
True
Inverted
MSB INV = “0”
MSB INV = “1”
LSBs INV = “0”
LSBs INV = “1”
(1)1111111111
1111111111
1111111110
•
•
•
1000000000
0111111111
0111111110
•
•
•
0000000010
0000000001
0000000000
(1)0000000000
0000000000
0000000001
•
•
•
0111111111
1000000000
1000000001
•
•
•
1111111101
1111111110
1111111111
Twos Complement
True
Inverted
MSB INV = “1”
MSB INV = “0”
LSBs INV = “0”
LSBs INV = “1”
(1)0111111111
0111111111
0111111110
•
•
•
0000000000
1111111111
1111111110
•
•
•
1000000010
1000000001
1000000000
The overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered dc controls.
REV. A
–11–
(1)1000000000
1000000000
1000000001
•
•
•
1111111111
0000000000
0000000001
•
•
•
0111111101
0111111110
0111111111
AD9020
The AD9020/PCB Evaluation Board is available from the factory and is shown here in block diagram form. The board includes a reference circuit that allows the user to adjust both
references and the quarter-point voltages. The AD9617 is included as the drive amplifier, and the user can configure the
gain from –1 to –15.
C1348b–0–6/97
On-board reconstruction of the digital data is provided through
the AD9713, a 12-bit monolithic DAC. The analog and reconstructed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9020 and the effects of
the quarterpoint voltages. The digital data and an adjustable
Data Ready signal are available through a 37-pin edge connector.
AD9020/PCB EVALUATION BOARD
DAC
OUT
– 5V
+ 5V
AD9713 DAC IOUT
50Ω
D
BUFFERED
ANALOG
INPUT
DUT
ANALOG
INPUT
400Ω
+VS
GND
+ 5V
MSB INVERT
LSBs INVERT
J2
200Ω
50Ω
–VS
TO ERROR
WAVEFORM
CIRCUIT
U5
AD9617
24Ω
ANALOG
INPUT
TO ERROR
WAVEFORM
CIRCUIT
+VREF
AD9020
DUT
+VSENSE
REFERENCE
CIRCUIT
(LSB) D0
D
D1
D
D2
D
D3
D
D4
D
D5
D
D6
D
D7
D
D8
D
3/4REF
(MSB) D9
D
1/2REF
OVERFLOW
D
OUTPUT
DATA
CONNECTOR
Q
TTL
LATCHES
DATA
READY
CLK
1/4REF
–VSENSE
TTL CLK
–VREF
TIMING
CIRCUIT
ENCODE
AD9020/PCB Evaluation Board Block Diagram
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Terminal
Leadless Chip Carrier (LCC)
(E-68A)
PRINTED IN U.S.A.
68-Leaded Ceramic Chip Carrier
(Z-68)
–12–
REV. A
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