Cypress CY7C024-55AI 4k x 16/18 and 8k x 16/18 dual-port static ram with sem, int, busy Datasheet

CY7C024/024A/0241
CY7C025/0251
4K x 16/18 and 8K x 16/18 Dual-Port
Static RAM with SEM, INT, BUSY
Features
Functional Description
■
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■
4K x 16 organization (CY7C024/024A[1])
■
4K x 18 organization (CY7C0241)
■
8K x 16 organization (CY7C025)
■
8K x 18 organization (CY7C0251)
■
0.65 micron CMOS for optimum speed and power
■
High speed access: 15 ns
■
Low operating power: ICC = 150 mA (typ)
■
Fully asynchronous operation
The CY7C024/024A/0241 and CY7C025/0251 are low power
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various
arbitration schemes are included on the CY7C024/ 0241 and
CY7C025/0251 to handle situations when multiple processors
access the same piece of data. Two ports are provided,
permitting independent, asynchronous access for reads and
writes to any location in memory. The CY7C024/ 0241 and
CY7C025/0251 can be used as standalone 16 or 18-bit dual-port
static RAMs or multiple devices can be combined to function as
a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S
pin is provided for implementing 32-/36-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
■
Automatic power down
■
Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
■
On-chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper-byte and lower-byte control
■
Pin select for Master or Slave
■
Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin
(Pb-free) TQFP, and 100-pin TQFP
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip select (CE) pin.
The CY7C024/024A/0241 and CY7C025/0251 are available in
84-pin Pb-free PLCCs, 84-pin PLCCs (CY7C024 and CY7C025
only), 100-pin Pb-free Thin Quad Plastic Flatplack (TQFP), and
100-pin Thin Quad Plastic Flatpack.
Note
1. CY7C024 and CY7C024A are functionally identical.
Cypress Semiconductor Corporation
Document #: 38-06035 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 09, 2008
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Logic Block Diagram
R/WR
UBR
L
L
LBR
L
CE
R
OE R
OE L
[4]
I/O 8L – I/O 15L
I/O
CONTROL
[3]
I/O8R – I/O 15R[4]
I/O
CONTROL
I/O 0R– I/O 7R [3]
I/O 0L – I/O 7L
BUSYL
(CY7C025/0251)
[2]
[2]
BUSYR
A12R (CY7C025/0251)
A12L
A11L
MEMORY
ARRAY
ADDRESS
DECODER
A11R
ADDRESS
DECODER
A0L
A 0R
INTERRUPT
SEMAPHORE
ARBITRATION
CE L
OE L
CE R
OE R
UB R
LB R
UB L
LB L
R/W R
SEM R
R/W L
SEM L
INT L
M/S
INTR
Pin Configurations
9L
A
8L
A 10L
A
LB L
NC [5]
A11L
SEM L
CE L
UB L
R/WL
GND
I/O 1L
I/O0L
OE L
V CC
I/O2L
I/O4L
I/O3L
I/O5L
I/O7L
I/O6L
Figure 1. 84-Pin PLCC (Top View)
11 10 9 8 7 6 5 4 3 2
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A10R
A 9R
A 8R
A 7R
NC [6]
A11R
GND
SEMR
CER
UB R
LB R
OE R
R/WR
GND
I/O15R
I/O13R
I/O14R
I/O11R
I/O12R
I/O 9R
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
58
28
57
29
56
30
55
31
54
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O10R
I/O8L
I/O9L
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
65
CY7C024/024A/025
64
63
62
61
60
59
Notes
2. BUSY is an output in master mode and an input in slave mode.
3. I/O0 –I/O8 on the CY7C0241/0251.
4. I/O9 –I/O17 on the CY7C0241/0251.
5. A12L on the CY7C025/0251.
6. A12R on the CY7C025/0251.
Document #: 38-06035 Rev. *D
Page 2 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Pin Configurations (continued)
A7L
A6L
A9L
A8L
UBL
LBL
NC [5]
A11L
A10L
OEL
VCC
R/WL
SEML
CEL
I/O1L
I/O0L
I/O4L
I/O3L
I/O2L
GND
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
Figure 2. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C024/5
NC
NC
NC
NC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
NC
NC
NC
NC
A7R
A6R
A5R
NC[6]
A11R
A10R
A9R
A8R
R/WR
GND
SEMR
CER
UBR
LBR
GND
I/O15R
ŒR
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O13R
I/O14R
NC
NC
NC
NC
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
Pin Definitions
Left Port
CEL
R/WL
OEL
A0L–A11/12L
I/O0L–I/O15/17L
SEML
UBL
LBL
INTL
BUSYL
M/S
VCC
GND
Right Port
Description
CER
R/WR
OER
A0R–A11/12R
Chip Enable
Read/Write Enable
Output Enable
Address
I/O0R–I/O15/17R
SEMR
UBR
LBR
INTR
BUSYR
Data Bus Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
Document #: 38-06035 Rev. *D
Page 3 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Selection Guide
Parameter
Maximum Access Time (ns)
Typical Operating Current (mA)
Typical Standby Current for ISB1 (mA)
7C024/024A/0241–15
7C025/0251–15
15
190
50
Architecture
The CY7C024/024A/0241 and CY7C025/0251 consist of an
array of 4K words of 16/18 bits each and 8K words of 16/18 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be used for
port-to-port communication. Two semaphore (SEM) control pins
are used for allocating shared resources. With the M/S pin, the
CY7C024/024A/0241 and CY7C025/0251 can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The CY7C024/024A/0241 and CY7C025/0251 have an
automatic power down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 7) or the CE pin (see Figure 8).
Required inputs for non contention operations are summarized
in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is
asserted. If the user of the CY7C024/024A/0241 or
CY7C025/0251 wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024/024A/0241, 1FFF for the CY7C025/0251) is the
mailbox for the right port and the second-highest memory
location (FFE for the CY7C024/024A/0241, 1FFE for the
CY7C025/0251) is the mailbox for the left port. When one port
writes to the other port’s mailbox, an interrupt is generated to the
owner. The interrupt is reset when the owner reads the contents
of the mailbox. The message is user defined.
Document #: 38-06035 Rev. *D
7C024/0241–25
7C025/0251–25
25
170
40
7C024/0241–35
7C025/0251–35
35
160
30
7C024/0241–55
7C025/0251–55
55
150
20
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the BUSY signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active BUSY to a port prevents that port from reading its own
mailbox and thus resetting the interrupt to it.
If your application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2 on page 5.
Busy
The CY7C024/024A/0241 and CY7C025/0251 provide on-chip
arbitration to resolve simultaneous memory location access
(contention). If both ports’ CEs are asserted and an address
match occurs within tPS of each other, the busy logic determines
which port has access. If tPS is violated, one port definitely gains
permission to the location, but which one is not predictable.
BUSY is asserted tBLA after an address match or tBLC after CE
is taken LOW.
Master/Slave
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C024/024A/0241 and CY7C025/0251 provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports. The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies
its success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value is
available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port was successful (reads a zero), it assumes
control of the shared resource, otherwise (reads a one) it
assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a one), the left side succeeds in gaining
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Page 4 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port immediately owns the semaphore as soon as the left
port released it. Table 3 shows sample semaphore operations.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within tSPS of each other, the semaphore is
definitely obtained by one side or the other, but there is no
guarantee which side controls the semaphore
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
Table 1. Non-Contending Read/Write
Inputs
Outputs
I/O0–I/O7
[3]
Operation
I/O8–I/O15[4]
CE
R/W
OE
UB
LB
SEM
H
X
X
X
X
H
High Z
High Z
Deselected: Power Down
X
X
X
H
H
H
High Z
High Z
Deselected: Power Down
L
L
X
L
H
H
High Z
Data In
Write to Upper Byte Only
L
L
X
H
L
H
Data In
High Z
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
High Z
Data Out
Read Upper Byte Only
L
H
L
H
L
H
Data Out
High Z
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
X
X
H
X
X
X
High Z
High Z
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore Flag
H
X
X
X
L
Data In
Data In
Write DIN0 into Semaphore Flag
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
X
X
L
X
L
Not Allowed
L
X
X
X
L
L
Not Allowed
Table 2. Interrupt Operation Example (Assumes BUSYL=BUSYR=HIGH)[7]
Function
Left Port
Right Port
R/WL
CEL
OEL
A0L–11L
INTL
R/WR
CER
OER
A0R–11R
INTR
Set Right INTR Flag
L
L
X
(1)FFF
X
X
X
X
X
L[9]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
(1)FFF
H[8]
Set Left INTL Flag
X
X
X
X
L[8]
L
L
X
(1)FFE
X
[9]
X
X
X
X
X
Reset Left INTL Flag
Document #: 38-06035 Rev. *D
X
L
L
(1)FFE
H
Page 5 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Table 3. Semaphore Operation Example
Function
No action
I/O0–I/O15/17
Left
I/O0–I/O15/17
Right
1
1
Status
Semaphore-free
Left port writes 0 to semaphore
0
1
Left Port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore.
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore-free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Notes
7. A0L–12L and A0R–12R, 1FFF/1FFE for the CY7C025.
8. If BUSYR=L, then no change.
9. If BUSYL=L, then no change.
Document #: 38-06035 Rev. *D
Page 6 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
DC Input Voltage[11] ........................................–0.5V to +7.0V
Maximum Ratings [10]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current ................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential................–0.3V to +7.0V
Range
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
Commercial
Ambient Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Industrial
Electrical Characteristics Over the Operating Range
Parameter
Description
7C024/024A/0241–15 7C024/024A/0241–25
7C025/0251–15
7C025/0251–25
Unit
Min
Typ
Max
Min
Typ
Max
Test Conditions
VOH
Output HIGH Voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min, IOL = 4.0 mA
2.4
2.4
V
0.4
0.4
V
VIH
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
–0.7
0.8
–0.7
0.8
V
IIX
Input Leakage Current
–10
+10
–10
+10
μA
IOZ
Output Leakage Current Output Disabled,
GND ≤ VO ≤ VCC
–10
+10
–10
+10
μA
ICC
Operating Current
mA
ISB1
Standby Current
CEL and CER ≥ VIH,
(Both Ports TTL Levels) f = fMAX[12]
ISB2
Standby Current
(One Port TTL Level)
CEL or CER ≥ VIH,
f = fMAX[12]
ISB3
Standby Current
(Both Ports CMOS
Levels)
Both Ports CE and CER ≥
Com’l
VCC – 0.2V, VIN ≥ VCC – 0.2V Ind
or VIN ≤ 0.2V, f = 0[12]
Standby Current
(Both Ports CMOS
Levels)
One Port CEL or
Com’l
CER ≥ VCC – 0.2V,
Ind
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V,
[12]
Active Port Outputs, f = fMAX
ISB4
GND ≤ VI ≤ VCC
VCC = Max, IOUT = 0 mA,
Outputs Disabled
2.2
V
Com’l
190
300
170
250
Ind
200
320
170
290
Com’l
50
70
40
60
Ind
50
70
Com’l
120
180
100
150
Ind
120
180
100
170
3
15
3
15
3
15
3
15
110
160
90
130
110
160
90
150
mA
75
mA
mA
mA
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C024/024A/0241–35 7C024/024A/0241–55
7C025/0251–35
7C025/0251–55
Unit
Min
Typ
Max
Min
Typ
Max
VOH
Output HIGH Voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min, IOL = 4.0 mA
VIH
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
–0.7
0.8
IIX
Input Leakage Current
–10
IOZ
Output Leakage Current Output Disabled, GND ≤ VO ≤ VCC
–10
GND ≤ VI ≤ VCC
2.4
2.4
0.4
V
0.4
V
–0.7
0.8
V
+10
–10
+10
μA
+10
–10
+10
μA
2.2
V
Notes
10. The voltage on any input or I/O pin cannot exceed the power pin during power up
11. Pulse width < 20 ns.
12. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
Document #: 38-06035 Rev. *D
Page 7 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
7C024/024A/0241–35 7C024/024A/0241–55
7C025/0251–35
7C025/0251–55
Unit
Min
Typ
Max
Min
Typ
Max
Test Conditions
ICC
Operating Current
ISB1
Standby Current
CEL and CER ≥ VIH,
(Both Ports TTL Levels) f = fMAX[12]
Ind
30
65
20
65
ISB2
Standby Current
(One Port TTL Level)
CEL or CER ≥ VIH,
f = fMAX[12]
Com’l
85
135
75
135
Ind
85
150
75
150
ISB3
Standby Current
(Both Ports CMOS
Levels)
Both Ports CE and CER ≥
VCC – 0.2V, VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0[12]
Com’l
3
15
3
15
Ind
3
15
3
15
Standby Current
(Both Ports CMOS
Levels)
One Port CEL or
CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V,
Active Port Outputs, f = fMAX[12]
Com’l
80
120
70
120
Ind
80
135
70
135
ISB4
VCC = Max, IOUT = 0 mA,
Outputs Disabled
Com’l
160
230
150
230
Ind
160
260
150
260
Com’l
30
50
20
50
mA
mA
mA
mA
mA
Capacitance[13]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25×C, f = 1 MHz,
VCC = 5.0V
Max
Unit
10
pF
10
pF
Figure 3. AC Test Loads and Waveforms
5V
5V
R1 = 893Ω
RTH = 250Ω
OUTPUT
OUTPUT
R1 = 893Ω
OUTPUT
C = 30pF
C = 30 pF
C = 5 pF
R2 = 347Ω
R2 = 347Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
ALL INPUT PULSES
OUTPUT
3.0V
C = 30 pF
GND
10%
90%
90%
10%
≤ 3 ns
≤ 3 ns
Load (Load 2)
Note
13. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06035 Rev. *D
Page 8 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Switching Characteristics Over the Operating Range [14]
Parameter
Description
7C024/024A/0241–15 7C024/024A/0241–25 7C024/024A/0241–35 7C024/024A/0241–55
7C025/0251–15
7C025/0251–25
7C025/0251–35
7C025/0251–55
Min
Max
Min
Max
Min
Max
Min
Unit
Max
Read Cycle
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Output Hold From Address
Change
tACE[15]
CE LOW to Data Valid
15
25
35
55
ns
tDOE
OE LOW to Data Valid
10
13
20
25
ns
tLZOE[16, 17, 18]
tHZOE[16, 17, 18]
tLZCE[16, 17, 18]
tHZCE[16, 17, 18]
tPU[18]
tPD[18]
tABE[15]
OE Low to Low Z
25
ns
15
3
CE LOW to Power Up
25
3
ns
3
20
0
ns
ns
3
3
0
55
20
15
ns
3
3
3
0
35
15
10
55
3
3
10
CE HIGH to High Z
35
3
3
OE HIGH to High Z
CE LOW to Low Z
25
ns
25
0
ns
ns
CE HIGH to Power Down
15
25
25
55
ns
Byte Enable Access Time
15
25
35
55
ns
Write Cycle
tWC
Write Cycle Time
15
25
35
55
ns
tSCE[15]
CE LOW to Write End
12
20
30
35
ns
tAW
Address Setup to Write End
12
20
30
35
ns
tHA
Address Hold From Write End
0
0
0
0
ns
tSA[15]
Address Setup to Write Start
0
0
0
0
ns
tPWE
Write Pulse Width
12
20
25
35
ns
tSD
Data Setup to Write End
10
15
15
20
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE[17, 18]
tLZWE[17, 18]
tWDD[19]
tDDD[19]
R/W LOW to High Z
R/W HIGH to Low Z
10
0
15
0
20
0
25
0
ns
ns
Write Pulse to Data Delay
30
50
60
70
ns
Write Data Valid to Read
Data Valid
25
35
35
45
ns
Notes
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
15. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
17. Test conditions used are Load 3.
18. This parameter is guaranteed but not tested.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11.
Document #: 38-06035 Rev. *D
Page 9 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Switching Characteristics Over the Operating Range (continued)[14]
Parameter
Description
7C024/024A/0241–15 7C024/024A/0241–25 7C024/024A/0241–35 7C024/024A/0241–55
7C025/0251–15
7C025/0251–25
7C025/0251–35
7C025/0251–55
Min
Max
Min
Max
Min
Max
Min
Unit
Max
Busy Timing[20]
tBLA
BUSY LOW from Address
Match
15
20
20
45
ns
tBHA
BUSY HIGH from Address
Mismatch
15
20
20
40
ns
tBLC
BUSY LOW from CE LOW
15
20
20
40
ns
tBHC
BUSY HIGH from CE HIGH
15
20
20
35
ns
tPS
Port Setup for Priority
5
5
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
(Slave)
13
20
30
40
ns
tBDD[21]
BUSY HIGH to Data Valid
Note 21
Note 21
Note 21
Note 21
ns
Interrupt Timing[20]
tINS
INT Set Time
15
20
25
30
ns
tINR
INT Reset Time
15
20
25
30
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or
SEM)
10
12
15
20
ns
tSWRD
SEM Flag Write to Read Time
5
10
10
15
ns
tSPS
SEM Flag Contention Window
5
10
10
15
ns
tSAA
SEM Address Access Time
15
Data Retention Mode
The CY7C024/024A/0241 is designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC during
the power up and power down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5V).
25
35
55
ns
Timing
Data Retention Mode
VCC
4.5V
VCC > 2.0V
4.5V
VCC to VCC – 0.2V
CE
Parameter
ICCDR1
Test Conditions[22]
At VCCDR = 2V
tRC
V
IH
Max
Unit
1.5
mA
Notes
20. Test conditions used are Load 2.
21. tBDD is a calculated parameter and is the greater of tWDD– tPWE (actual) or tDDD– tSD (actual).
22. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06035 Rev. *D
Page 10 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access)[23, 24, 25]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[23, 26, 27]
tACE
CE and
LB or UB
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Figure 6. Read Cycle No. 3 (Either Port)[23, 25, 26, 26, 27]
tRC
ADDRESS
tOHA
tAA
UB or LB
tHZCE
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes
23. R/W is HIGH for read cycles
24. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
25. OE = VIL.
26. Address valid prior to or coincident with CE transition LOW.
27. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06035 Rev. *D
Page 11 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31]
tWC
ADDRESS
tHZOE [34]
OE
tAW
CE
[32,33]
tPWE[31]
tSA
tHA
R/W
tHZWE[34]
DATA OUT
tLZWE
NOTE 35
NOTE 35
tSD
tHD
DATA IN
Figure 8. Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 36]
tWC
ADDRESS
tAW
CE
[32,33]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
30. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tPWE.
32. To access RAM, CE = VIL, SEM = VIH.
33. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
34. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06035 Rev. *D
Page 12 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Switching Waveforms (continued)
Figure 9. Semaphore Read After Write Timing, Either Side[37]
tAA
A 0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tOHA
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention[38, 39, 40]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes
37. CE = HIGH for the duration of the above timing (both write and read cycle).
38. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
39. Semaphores are reset (available to both ports) at cycle start.
40. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Document #: 38-06035 Rev. *D
Page 13 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Switching Waveforms (continued)
Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)[41]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Figure 12. Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
41. CEL = CER = LOW
Document #: 38-06035 Rev. *D
Page 14 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Switching Waveforms (continued)
Figure 13. Busy Timing Diagram No.1 (CE Arbitration)[42]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSY L
Figure 14. Busy Timing Diagram No.2 (Address Arbitration)[42]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note
42. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Document #: 38-06035 Rev. *D
Page 15 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Switching Waveforms (continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INTR :
ADDRESSL
tWC
WRITE FFF (1FFF CY7C025)
tHA[43]
CE L
R/W L
INT R
tINS [44]
Right Side Clears INT R :
tRC
READ FFF
(1FFF CY7C025)
ADDRESSR
CE R
tINR [44]
R/WR
OE R
INTR
Right Side Sets INT L:
tWC
ADDRESSR
WRITE FFE (1FFE CY7C025)
tHA[43]
CE R
R/W R
INT L
[44]
tINS
Left Side Clears INT L:
tRC
READ FFE
(1FFE CY7C025)
ADDRESSR
CE L
tINR[44]
R/W L
OE L
INT L
Notes
43. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
44. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 38-06035 Rev. *D
Page 16 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Ordering Information (4K x16 Dual-Port SRAM)
Speed
(ns)
15
Ordering Code
A100
100-Pin Thin Quad Flat Pack
CY7C024-15AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
J83
84-Pin Plastic Leaded Chip Carrier
CY7C024-15JXC
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C024–25AC
A100
100-Pin Thin Quad Flat Pack
CY7C024-25AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C024–25JC
CY7C024A-25JXC
84-Pin Plastic Leaded Chip Carrier
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
A100
100-Pin Thin Quad Flat Pack
CY7C024-25AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
J83
84-Pin Plastic Leaded Chip Carrier
CY7C024-25JXI
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C024–35AC
A100
100-Pin Thin Quad Flat Pack
CY7C024-35AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C024–35JC
CY7C024-35JXC
J83
84-Pin Plastic Leaded Chip Carrier
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C024–35AI
A100
100-Pin Thin Quad Flat Pack
CY7C024-35AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C024–35JI
55
J83
CY7C024–25AI
CY7C024–25JI
35
Package Type
CY7C024–15AC
CY7C024–15JC
25
Package
Name
J83
84-Pin Plastic Leaded Chip Carrier
CY7C024-35JXI
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C024–55AC
A100
100-Pin Thin Quad Flat Pack
CY7C024-55AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C024–55JC
CY7C024-55JXC
J83
84-Pin Plastic Leaded Chip Carrier
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C024–55AI
A100
100-Pin Thin Quad Flat Pack
CY7C024-55AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C024–55JI
J83
84-Pin Plastic Leaded Chip Carrier
CY7C024-55JXI
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Ordering Information (8K x 16 Dual-Port SRAM)
Speed
(ns)
15
Ordering Code
Package
Name
Package Type
CY7C025–15AC
A100
100-Pin Thin Quad Flat Pack
CY7C025-15AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C025–15JC
CY7C025-15JXC
J83
84-Pin Plastic Leaded Chip Carrier
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C025–15AI
A100
100-Pin Thin Quad Flat Pack
CY7C025-15AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
Document #: 38-06035 Rev. *D
Operating
Range
Commercial
Industrial
Page 17 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Ordering Information (8K x 16 Dual-Port SRAM) (continued)
Speed
(ns)
25
35
55
Ordering Code
Package
Name
Package Type
CY7C025–25AC
A100
100-Pin Thin Quad Flat Pack
CY7C025-25AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C025–25JC
J83
84-Pin Plastic Leaded Chip Carrier
CY7C025-25JXC
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C025–25AI
A100
100-Pin Thin Quad Flat Pack
CY7C025-25AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C025–25JI
J83
84-Pin Plastic Leaded Chip Carrier
CY7C025-25JXI
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C025–35AC
A100
100-Pin Thin Quad Flat Pack
CY7C025-35AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C025–35JC
J83
84-Pin Plastic Leaded Chip Carrier
CY7C025-35JXC
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C025–35AI
A100
100-Pin Thin Quad Flat Pack
CY7C025-35AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C025–35JI
J83
84-Pin Plastic Leaded Chip Carrier
CY7C025-35JXI
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C025–55AC
A100
100-Pin Thin Quad Flat Pack
CY7C025-55AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C025–55JC
J83
84-Pin Plastic Leaded Chip Carrier
CY7C025-55JXC
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
CY7C025–55AI
A100
100-Pin Thin Quad Flat Pack
CY7C025-55AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C025–55JI
J83
84-Pin Plastic Leaded Chip Carrier
CY7C025-55JXI
J83
84-Pin Pb Free Plastic Leaded Chip Carrier
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Ordering Information (4K x 18 Dual-Port SRAM)
Speed
(ns)
15
25
35
Ordering Code
Package
Name
Package Type
CY7C0241–15AC
A100
100-Pin Thin Quad Flat Pack
CY7C0241-15AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–15AI
A100
100-Pin Thin Quad Flat Pack
CY7C0241-15AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–25AC
A100
100-Pin Thin Quad Flat Pack
CY7C0241-25AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–25AI
A100
100-Pin Thin Quad Flat Pack
CY7C0241-25AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–35AC
A100
100-Pin Thin Quad Flat Pack
CY7C0241-35AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–35AI
A100
100-Pin Thin Quad Flat Pack
CY7C0241-35AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
Document #: 38-06035 Rev. *D
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 18 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Ordering Information (4K x 18 Dual-Port SRAM) (continued)
Speed
(ns)
55
Ordering Code
Package
Name
Package Type
CY7C0241–55AC
A100
100-Pin Thin Quad Flat Pack
CY7C0241-55AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0241–55AI
A100
100-Pin Thin Quad Flat Pack
CY7C0241-55AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
Operating
Range
Commercial
Industrial
8K x 18 Dual-Port SRAM
Speed
(ns)
15
25
35
55
Ordering Code
CY7C0251–15AC
Package
Name
A100
Package Type
100-Pin Thin Quad Flat Pack
CY7C0251–15AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0251–25AC
A100
100-Pin Thin Quad Flat Pack
CY7C0251-25AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0251–25AI
A100
100-Pin Thin Quad Flat Pack
CY7C0251–25AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0251–35AC
A100
100-Pin Thin Quad Flat Pack
CY7C0251–35AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0251–35AI
A100
100-Pin Thin Quad Flat Pack
CY7C0251–35AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0251–55AC
A100
100-Pin Thin Quad Flat Pack
CY7C0251–55AXC
A100
100-Pin Pb Free Thin Quad Flat Pack
CY7C0251–55AI
A100
100-Pin Thin Quad Flat Pack
CY7C0251–55AXI
A100
100-Pin Pb Free Thin Quad Flat Pack
Document #: 38-06035 Rev. *D
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 19 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Package Diagrams
Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*C
Figure 17. 84-Pin Pb Free Plastic Leaded Chip Carrier J83
51-85006-*A
Document #: 38-06035 Rev. *D
Page 20 of 21
[+] Feedback
CY7C024/024A/0241
CY7C025/0251
Document History Page
Document Title: CY7C024/024A/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy
Document Number: 38-06035
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
110177
SZV
09/29/01
Change from Spec number: 38-00255 to 38-06035
*A
122286
RBI
12/27/02
Power up requirements added to Maximum Ratings Information
*B
236754
YDT
See ECN
Removed cross information from features section
Description of Change
*C
279132
RUY
See ECN
Added Lead (Pb)-Free packaging information
*D
2623540
VKN/PYRS
12/17/08
Added CY7C024A part
Updated Ordering information table
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
Clocks & Buffers
PSoC Solutions
psoc.cypress.com
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
image.cypress.com
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06035 Rev. *D
Revised December 09, 2008
Page 21 of 21
All products and company names mentioned in this document may be the trademarks of their respective holders.
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