Cypress CY7C265-15JC 8k x 8 registered prom Datasheet

65
CY7C265
8K x 8 Registered PROM
Features
If the asynchronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
• CMOS for optimum speed/power
• High speed (Commercial)
— 15 ns address set-up
— 12 ns clock to output
• Low power
— 660 mW (Commercial)
• On-chip edge-triggered registers
— Ideal for pipelined microprogrammed systems
• EPROM technology
— 100% programmable
— Reprogrammable (CY7C265W)
• 5V ±10% VCC, commercial and military
• Capable of withstanding >2001V static discharge
• Slim 28-pin, 300-mil plastic or hermetic DIP
Functional Description
The CY7C265 is a 8192 x 8 registered PROM. It is organized
as 8,192 words by 8 bits wide, and has a pipeline output
register. In addition, the device features a programmable
initialize byte that may be loaded into the pipeline register with
the initialize signal. The programmable initialize byte is the
8,193rd byte in the PROM and its value is programmed at the
time of use.
Packaged in 28 pins, the PROM has 13 address signals (A0
through A12), 8 data out signals (O0 through O7), E/I (enable
or initialize), and CLOCK.
CLOCK functions as a pipeline clock, loading the contents of
the addressed memory location into the pipeline register on
each rising edge. The data will appear on the outputs if they
are enabled. One pin on the CY7C265 is programmed to
perform either the enable or the initialize function.
Cypress Semiconductor Corporation
Document #: 38-04012 Rev. *A
•
If the synchronous enable (ES) is being used, the outputs will
go to the OFF or high-impedance state upon the next positive
clock edge after the synchronous enable input is switched to
a HIGH level. If the synchronous enable pin is switched to a
logic LOW, the subsequent positive clock edge will return the
output to the active state. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature allows the CY7C265 decoders and sense amplifiers to access
the next location while previously addressed data remains stable on the outputs.
If the E/I pin is used for INIT (asynchronous), then the outputs
are permanently enabled. The initialize function is useful
during power-up and time-out sequences, and can facilitate
implementation of other sophisticated functions such as a
built-in “jump start” address. When activated, the initialize
control input causes the contents of a user programmed
8193rd 8-bit word to be loaded into the on-chip register. Each
bit is programmable and the initialize function can be used to
load any desired combination of 1’s and 0’s into the register.
In the unprogrammed state, activating INIT will generate a
register clear (all outputs LOW). If all the bits of the initialize
word are programmed to be a 1, activating INIT performs a
register preset (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the pipeline register and
onto the outputs. The INIT LOW disables clock and must
return HIGH to enable clock independent of all other inputs,
including the clock.
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised October 9, 2002
CY7C265
Logic Block Diagram
Pin Configurations
DIP/Flatpack
Top View
A12
O7
A11
A10
O6
ROW
ADDRESS
A8
PROGRAMMABLE
ARRAY
COLUMN
MULTIPLEXER
O5
PROGRAMMABLE
INITIALIZE WORD
A9
A7
A6
ADDRESS
DECODER
A5
A5
A4
O4
8-BIT
EDGETRIGGERED
REGISTER
O3
O2
A3
COLUMN
ADDRESS
A2
A0
28
VCC
2
27
A8
A5
3
26
A9
A4
4
25
A 10
A3
5
24
A 11
A2
6
23
A 12
GND
7
22
E/E S ,I
CLK
8
21
GND
A1
9
20
GND
A0
10
19
O7
O0
11
18
O6
O1
12
17
O5
O2
13
16
O4
GND
14
15
O3
D
O
7C265
LCC/PLCC (Opaque Only)
Top View
O0
CLK
CLK
1
O1
A1
INIT/E/ES
A7
A6
A 4 A 5 A 6 A 7 VCC A 8 A 9
PROGRAMMABLE
MULTIPLEXER
4
C
3
2
1 28 27 26
A3
5
25
A 10
A2
GND
6
24
7
23
A 11
A 12
8
22
E/E S ,I
9
21
GND
10
20
11
19
15 16 17 18
GND
O7
CLK
A1
A0
O0
12 13 14
O 1 O 2 GND O 3 O 4 O 5 O 6
F
Selection Guides
Minimum Address Set-Up Time
Maximum Clock to Output
Maximum Operating Current
Com’l
7C265-15
7C265-25
7C265-40
7C265-50
Unit
15
25
40
50
ns
25
12
15
20
120
120
100
Mil
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
120
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Commercial
DC Program Voltage .....................................................13.0V
Document #: 38-04012 Rev. *A
mA
UV Exposure ................................................ 7258 Wsec/cm2
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
ns
mA
Military[1]
Ambient
Temperature
VCC
0°C to +70°C
5V ±10%
–55°C to +125°C
5V ±10%
Notes:
1. TA is the “instant on” case temperature.
Page 2 of 11
CY7C265
Electrical Characteristics Over the Operating Range[2]
7C265-15, 25
Parameter
VOH
Description
Test Conditions
Output HIGH Voltage
Min.
VCC = Min., IOH = –2.0 mA
Output LOW Voltage
7C265-50
2.4
V
VCC = Min., IOH = –4.0 mA
VOL
7C265-40
Max. Min. Max. Min. Max. Unit
2.4
VCC = Min., IOL = 8.0 mA Com’l
2.4
0.4
V
VCC = Min., IOL = 12.0 mA
0.4
VCC = Min., IOL = 6.0 mA Mil
0.4
0.4
VCC = Min., IOL = 8.0 mA
0.4
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
2.0
2.0
IIX
Input Load Current
GND < VIN < VCC
–10
+10
–10
+10
IOZ
Output Leakage Current
GND < VOUT < VCC,
Output Disabled
–40
+40
–40
+40
IOS[3]
Output Short Circuit Current
VCC = Max., VOUT = GND
ICC
VCC Operating Supply
Current
VCC = Max., IOUT = 0 mA Com’l
0.8
VPP
Programming Supply Voltage
IPP
Programming Supply Current
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
0.8
90
90
120
100
V
0.8
V
–10
+10
µA
–40
+40
µA
90
mA
mA
Mil
120
12
13
12
13
50
3.0
12
50
3.0
0.4
13
V
50
mA
3.0
0.4
V
0.4
V
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
10
pF
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
4. See Introduction to CMOS PROMs in this Data Book for general information on testing.
Document #: 38-04012 Rev. *A
Page 3 of 11
CY7C265
AC Test Loads and Waveforms
Test Load for -15 through -25 speeds
R1 500
(658Ω MIL)
R1 500Ω
(658Ω MIL)
5V
5V
OUTPUT
OUTPUT
R2 333Ω
(403Ω MIL)
30 pF
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
R2 333Ω
(403Ω MIL)
5 pF
≤ 5 ns
≤ 5 ns
INCLUDING
JIG AND
SCOPE
(a) NormalLoad
Equivalent to:
3.0V
(b) High Z Load
THÉVENIN EQUIVALENT
OUTPUT
RTH 200Ω
250Ω MIL
Test Load for -40 through -50 speeds
R1 250Ω
R1 250Ω
5V
5V
OUTPUT
OUTPUT
30 pF
5 pF
R2 167Ω
INCLUDING
JIG AND
SCOPE
R2 167Ω
INCLUDING
JIG AND
SCOPE
(c) Normal Load
(d) High Z Load
Equivalent to:
THÉVENIN EQUIVALENT
RTH 100Ω
OUTPUT
2.0V
Switching Characteristics Over the Operating Range[2, 4]
7C265-15
Parameter
Description
Min.
Max.
7C265-25
Min.
Max.
7C265-40
Min.
Max.
7C265-50
Min.
Max.
Unit
tAS
Address Set-Up to Clock
15
25
40
50
ns
tHA
Address Hold from Clock
0
0
0
0
ns
tCO
Clock to Output Valid
tPWC
Clock Pulse Width
12
15
15
20
ns
tSES
ES Set-Up to Clock
(Sync. Enable Only)
12
15
15
15
ns
tHES
ES Hold from Clock
5
tDI
INIT to Output Valid
tRI
INIT Recovery to Clock
12
15
20
25
ns
tPWI
INIT Pulse Width
12
15
25
35
ns
tCOS
Output Valid from Clock
(Sync. Mode)
12
15
20
25
ns
tHZC
Output Inactive from Clock
(Sync. Mode)
12
15
20
25
ns
tDOE
Output Valid from E LOW
(Async. Mode)
12
15
20
25
ns
tHZE
Output Inactive from E HIGH
(Async. Mode)
12
15
20
25
ns
Document #: 38-04012 Rev. *A
12
15
5
15
20
5
18
25
5
25
ns
ns
35
ns
Page 4 of 11
CY7C265
Switching Waveform
ADDRESS
tAS
SYNCHRONOUS
ENABLE
(PROGRAMMABLE)
tAH
tHES
tSES
CLOCK
tPWC
tCO
tCOS
VALID DATA
OUTPUT
tDI
tHZC
tHZE
tPWI
tDOE
ASYNCHRONOUS INIT
(PROGRAMMABLE)
tRI
ASYNCHRONOUS
ENABLE
Erasure Characteristics
Control Byte
Wavelengths of light less than 4000 angstroms begin to erase
the 7C265 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended
periods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV
intensity • exposure time) of 25 Wsec/cm2. For an ultraviolet
lamp with a 12 mW/cm2 power rating the exposure time would
be approximately 45 minutes. The 7C265 needs to be within
one inch of the lamp during erasure. Permanent damage may
result if the PROM is exposed to high-intensity UV light for an
extended period of time. 7258 Wsec/cm2 is the recommended
maximum dosage.
Bit Map Data
Programmer Address (Hex.)
RAM Data
Decimal
Hex
Contents
0
.
.
8191
8192
8193
0
.
.
1FFF
2000
2001
Data
.
.
Data
INIT Byte
Control Byte
Document #: 38-04012 Rev. *A
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize
Programming Modes
The 7C265 offers a limited selection of programmed architectures. Programming these features should be done with a
single 10-ms-wide pulse in place of the intelligent algorithm,
mainly because these features are verified operationally, not
with the VFY pin. Architecture programming is implemented by
applying the supervoltage to two additional pins during
programming. In programming the 7C265 architecture, VPP is
applied to pins 3, 9, and 22. The choice of a particular mode
depends on the states of the other pins during programming,
so it is important that the condition of the other pins be met as
set forth in the mode table. The considerations that apply with
respect to power-up and power-down during intelligent
programming also apply during architecture programming.
Once the supervoltages have been established and the
correct logic states exist on the other device pins,
programming may begin. Programming is accomplished by
pulling PGM from HIGH to LOW and then back to HIGH with
a pulse width equal to 10 ms.
Page 5 of 11
CY7C265
Table 1. Mode Selection
Pin Function
Read or Output Disable
A12
A11
A10–A7
A6
A5
A4–A3
A2
Other
A12
A11
A10–A7
A6
A5
A4–A3
A2
Asynchronous Enable Read
A12
A11
A10–A7
A6
A5
A4–A3
A2
Synchronous Enable Read
A12
A11
A10–A7
A6
A5
A4–A3
A2
Asynchronous Initialization Read
A12
A11
A10–A7
A6
A5
A4–A3
A2
Program Memory
A12
A11
A10–A7
A6
A5
A4–A3
A2
Program Verify
A12
A11
A10–A7
A6
A5
A4–A3
A2
Program Inhibit
A12
A11
A10–A7
A6
A5
A4–A3
A2
Program Synchronous Enable
VIHP
VIHP
A10–A7
VIHP
VPP
A4–A3
VIHP
Program Initialize
VILP
VIHP
A10–A7
VIHP
VPP
A4–A3
VILP
Program Initial Byte
A12
VILP
A10 – A7
VIHP
VPP
A4–A3
VILP
Mode
Pin Function
Read or Output Disable
A1
A0
GND
CLK
GND
E, I
O7–O0
Other
A1
A0
PGM
CLK
VFY
VPP
D7–D0
Asynchronous Enable Read
A1
A0
GND
VIL
GND
VIL
O7–O0
Synchronous Enable Read
A1
A0
GND
VIL/VIH
GND
VIL
O7–O0
Asynchronous Initialization Read
A1
A0
GND
VIL
GND
VIL
O7–O0
Program Memory
A1
A0
VILP
VILP
VIHP
VPP
D7–D0
Program Verify
A1
A0
VIHP
VILP
VILP
VPP
O7–O0
Program Inhibit
A1
A0
VIHP
VILP
VIHP
VPP
High Z
Program Synchronous Enable
VPP
VILP
VILP
VILP
VIHP
VPP
D7–D0
Program Initialize
VPP
VILP
VILP
VILP
VIHP
VPP
D7–D0
Program Initial Byte
VPP
VIHP
VILP
VILP
VIHP
VPP
D7–D0
A7
A6
A5
A4
A3
A2
PGM
CLK
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
14
15
25
24
23
22
21
20
19
18
17
16
LCC/PLCC (Opaque Only)
VCC
A8
A9
A10
A11
A12
VPP
NA
VFY
D7
D6
D5
D4
D3
A4
A5
A6
A7
VCC
A8
A9
DIP/Flatpack
A3
A2
PGM
CLK
A1
A0
D0
4 3 2 1 28 27 26
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12 1314151617 18
A10
A11
A12
VPP
NA
VFY
D7
D1
D2
GND
D3
D4
D5
D6
Mode
Figure 1. Programming Pinout
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
Document #: 38-04012 Rev. *A
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Page 6 of 11
CY7C265
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.6
1.2
1.4
1.1
NORMALIZED ICC
NORMALIZED ICC
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
ICC
1.0
0.8
0.6
4.0
TA =25°C
f=MAX.
4.5
5.0
5.5
ICC
1.0
0.9
0.8
–55
6.0
60
50
40
30
20
10
0
0.0
1.4
1.2
1.0
0.8
175
35
150
30
125
25
100
75
50
VCC = 5.0V
TA = 25°C
25
0
0.0
125
AMBIENT TEMPERATURE (°C)
1.0
2.0
3.0
2.0
3.0
4.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
DELTA t CO (ns)
1.6
1.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
OUTPUT SINK CURRENT (mA)
NORMALIZED ACCESS TIME
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
25
125
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE ( °C)
SUPPLY VOLTAGE (V)
0.6
–55
25
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
20
15
10
VCC =4.5V
TA = 25°C
5
4.0
OUTPUT VOLTAGE (V)
0
0
200
400
600
800 1000
CAPACITANCE (pF)
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
1.05
1.00
NORMALIZED ICC
VCC = 5.5V
TA = 25°C
0.95
0.90
0.85
0.80
0.75
0.70
0
25
50
75
100
CLOCK PERIOD (ns)
Document #: 38-04012 Rev. *A
Page 7 of 11
CY7C265
Ordering Information
Speed
(ns)
ICC
(mA)
15
120
25
120
40
100
50
120
Ordering Code
Package
Name
Operating
Range
Package Type
CY7C265-15JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
CY7C265-15WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C265-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C265-25WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C265-40PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C265-50DMB
D22
28-Lead (300-Mil) CerDIP
Military
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1, 2, 3
tAS
7, 8, 9, 10, 11
VOL
1, 2, 3
tHA
7, 8, 9, 10, 11
VIH
1, 2, 3
tCO
7, 8, 9, 10, 11
VIL
1, 2, 3
tPW
7, 8, 9, 10, 11
IIX
1, 2, 3
tSES
7, 8, 9, 10, 11
IOZ
1, 2, 3
tHES
7, 8, 9, 10, 11
ICC
1, 2, 3
tCOS
7, 8, 9, 10, 11
Document #: 38-04012 Rev. *A
Page 8 of 11
CY7C265
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032-**
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
Document #: 38-04012 Rev. *A
Page 9 of 11
CY7C265
Package Diagrams (continued)
28-Lead (300-Mil) Molded DIP P21
51-85014-*B
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087-**
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-04012 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C265
Document History Page
Document Title: CY7C265 8K x 8 Registered PROM
Document Number: 38-04012
ECN NO.
Issue
Date
Orig. of
Change
**
114139
03/18/02
DSG
Change from Spec number: 38-00084 to 38-04012
*A
118896
10/09/02
GBI
Update ordering information
REV.
Document #: 38-04012 Rev. *A
Description of Change
Page 11 of 11
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