FAIRCHILD SG1577A

SG1577A
Dual Synchronous DC/DC Controller
Features
Description
ƒ
ƒ
ƒ
Integrated Two Sets of MOSFET Drivers
ƒ
ƒ
ƒ
Maximum Input Supply Voltage: 15V
The SG1577A is a high-efficiency, voltage-mode, dualchannel, synchronous DC/DC PWM controller for two
independent outputs. The two channels are operated
out of phase. The internal reference voltage is trimmed
to 0.7V±1.5%. It is connected to the error amplifier’s
positive terminal for voltage feedback regulation.
ƒ
ƒ
ƒ
ƒ
ƒ
Two Soft-Start / EN Functions
Two Independent PWM Controllers
Constant Frequency Operation: Free-running Fixed
Frequency Oscillator Programmable: 61kHz to 340kHz
The soft-start circuit ensures the output voltage can be
gradually and smoothly increased from zero to its final
regulated value. The soft-start pin can also be used for
chip-enable function. When two soft-start pins are
grounded, the chip is disabled and the total operation
current can be reduced to under 0.7mA.
Programmable Output as Low as 0.7V
Internal Error Amplifier Reference Voltage:
0.7V±1.5%
Programmable Over-Current Protection (OCP)
Output Over-Voltage Protection (OVP)
The fixed-frequency is programmable from 60kHz to
340kHz. The Over-Current Protection (OCP) level can
be programmed by an external current sense resistor. It
has two integrated sets of internal MOSFET drivers.
20-Pin SOP
SG1577A is available in a 20-pin SOP package.
30V HIGH Voltage Pin for Bootstrap Voltage
Applications
ƒ
ƒ
CPU and GPU Vcore Power Supply
Power Supply Requiring Two Independent Outputs
Ordering Information
Part Number
Operating
Temperature Range
SG1577ASY
-40°C to +105°C
Eco Status
Green
Package
Packing
Method
20-Lead, Small Outline
Package (SOP-20)
Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
www.fairchildsemi.com
SG1577A — Dual Synchronous DC/DC Controller
September 2009
SG1577A — Dual Synchronous DC/DC Controller
Application Diagram
Figure 1.
Typical Application
Internal Block Diagram
Figure 2.
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
Functional Block Diagram
www.fairchildsemi.com
2
20
ZXYTT
SG1577A
TPM
1
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
F: Fairchild Logo
Z: Assembly Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: S = SOP
P: Y=Green Package
M: Mask Version
SOP-20
SG1577A — Dual Synchronous DC/DC Controller
Marking Diagram
www.fairchildsemi.com
3
Figure 3. SOP-20 Pin Configuration (Top View)
Pin Definitions
Name
Pin #
Type
Description
Switching frequency programming pin. An external resistor connecting
this pin to GND can program the switching frequency. The switching
Frequency Select
frequency is 61kHz when RT is open and becomes 340kHz when RT is
shorted to ground.
RT
1
IN1
2
Feedback
COMP1
3
Compensation
Output of the error amplifier and input to the PWM comparator. It is used
for feedback loop compensation.
SS1/ENB
4
Soft Start/Enable
A 35/15µA internal current source charging an external capacitor for softstart. Pull down this pin and pin 17 to disable the chip.
CLP1
5
Over Current
Protection
Inverting input of the error amplifier. It is normally connected to the
switching power supply output through a resistor divider.
Over-current protection for high-side MOSFET. Connect a resistor from
this pin to the high-side supply voltage to program the OCP level.
BST1
6
Boost Supply
DH1
7
High-Side Drive
CLN1
8
Switch Node
DL1
9
Low-Side Drive
Low-side MOSFET gate driver pin.
PGND
10
Driver Ground
Driver circuit reference. Connect to low-side MOSFET GND.
Supply for high-side driver. Connect to the internal bootstrap circuit.
Channel 1, high-side MOSFET gate driver pin.
Switch-node connection to inductor. For channel 1 high-side driver’s
reference ground.
VCC
11
Power Supply
DL2
12
Low-Side Drive
CLN2
13
Switch Node
DH2
14
High-Side Drive
BST2
15
Boost Supply
Supply for high-side driver. Connect to the internal bootstrap circuit.
CLP2
16
Over-Current
Protection
Over-current protection for the high-side MOSFET. Connect a resistor
from this pin to the high-side supply voltage to program the OCP level.
SS2/ENB
17
Soft-Start/Enable
COMP2
18
Compensation
IN2
19
Feedback
GND
20
Analog Ground
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
SG1577A — Dual Synchronous DC/DC Controller
Pin Configuration
Supply voltage input.
Low-side MOSFET gate driver pin.
Switch-node connection to inductor. For channel 2, high-side driver’s
reference ground.
Channel 2 high-side MOSFET gate driver pin.
A 35/15µA internal current source charging an external capacitor for
soft-start. Pull down this pin and pin 4 to disable the chip.
Output of the error amplifier and input to the PWM comparator. It is used
for feedback-loop compensation.
Inverting input of the error amplifier. It is normally connected to the
switching power supply output through a resistor divider.
The reference of internal control circuits.
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are
given with respect to the network ground terminal. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device.
Symbol
Max.
Unit
Supply Voltage, VCC to GND
16
V
BST1(or 2) –
CLN1(or 2)
BST1(2) to CLN1(2)
16
V
CLN1(or 2) –
GND
CLN1(2) to GND for 100ns Transient
18
V
BST1(or 2) –
GND
BST1(2) to GND for 100ns Transient
30
V
16
V
VCC+0.3
V
±1
V
VCC
Parameter
Min.
-4
DH1(or 2) –
CLN1(or 2)
CLN1(or 2),
DL1(or 2)
PGND
-0.3
PGND to GND
ΘJA
Thermal Resistance, Junction-Air
90
°C/W
TJ
Operating Junction Temperature
-40
+125
°C
TSTG
Storage Temperature Range
-65
+150
°C
ESD
Electrostatic Discharge
Protection Level
Human Body Model (HBM)
2
Charged Device Model (CDM)
1
SG1577A — Dual Synchronous DC/DC Controller
Absolute Maximum Ratings
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VCC
Supply Voltage
TA
Operating Ambient Temperature
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
Min.
-40
Max.
Unit
+15
V
+105
°C
www.fairchildsemi.com
5
VCC=12V, TA =25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VCC UVLO
VCC_ON
Turn-On Threshold
VCC Ramp-Up
9.5
10.0
10.5
V
VCC_HYS
UVLO Hysteresis
VCC Ramp-Down
1.5
2.0
2.5
V
Oscillator
fosc
Oscillator Frequency
fosc,rt
Total Accuracy
DON_MAX
RRT=OPEN
55
61
67
RRT=GND
308
340
372
20kΩ＜RRT
-10
Maximum Duty Cycle
KHz
10
%
%
85
90
95
0.6895
0.7000
0.7105
Error Amplifier
VREF
△VREF
(1)
Internal Reference Voltage
VCC=8V, VCC=15V
VREF Temperature Coefficient
TA=0~85 C
o
V
o
0.03
mV/ C
AVOL
Open-loop Voltage Gain
77
dB
BW
Unity Gain Bandwidth
3.5
MHz
ISOURCE
Output Source Current
IN1=IN2=0.6V
60
80
100
µA
Output Sink Current
IN1=IN2=0.8V
250
400
550
µA
VH RAMP_Peak
The Peak of VRAMP
Gate Output=DON_MAX
2.45
2.8
3.15
V
V RAMP_Valley
The Valley of VRAMP
No Gate Output
1.05
1.2
1.35
V
VCLP＜VCLN , VSS_Transition＞VSS
28
35
42
µA
VCLP＜VCLN , VSS_Transition＜VSS
13
16
19
µA
1.40
1.42
1.44
V
ISINK
SG1577A — Dual Synchronous DC/DC Controller
Electrical Characteristics
Two-Stage Soft-Start
ISOURCE_1
ISOURCE_2
st
nd
st
1 Soft-start Charge Current
2
nd
Soft-start Charge Current
st
VSS_Transition
ISINK
Soft-start Transition Point
ISOURCE_1 Transit to ISOURCE_2
See Figure 4
Soft-start Discharge Current
VCLP＞VCLN
OC Sink Current
VCC=12V
nd
50
µA
Protections
IOCSET
TOT
TOT_hys
VOVP
90
120
150
150
Over-Temperature
°C
20
Over-Temperature Hysteresis
Over-Voltage Protection of IN
VOVP/VIN
118
122
IDH
High-Side Current Source
VBST - VCLN=12V, VDH - VCLN=6V
1.0
1.8
RDH
High-Side Sink Resistor
VBST - VCLN=12V
IDL
Low-Side Current Source
VCC=12V, VDL =6V
1.0
1.8
RDL
Low-Side Sink Resistor
VCC=12V
Dead Time
VCC=12V, DH & DL=1000pF
µA
°C
126
%
Output
TDT
(2)
2.8
A
3.8
Ω
A
2.8
3.8
Ω
50
70
90
ns
3.3
4.3
5.3
mA
0.7
1.0
mA
Total Operating Current
ICC_OP
Operating Supply Current
VCC=12V, No load
ICC_SBY
Standby Current (Disabled)
SS1/ENB=SS2/ENB=0V
Notes:
1. Not tested in production, 30pcs sample.
2. When VDL falls less than 2V relative to VDH rising to 2V.
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
www.fairchildsemi.com
6
SG1577A — Dual Synchronous DC/DC Controller
Timing Diagrams
Figure 4. Timing Chart of Two-Stage Soft-Start
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
www.fairchildsemi.com
7
Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF and CSS2/ENB=168nF.
Figure 5. Power On at 0.3A Load
Figure 6. Power On at 3.6A Load
Figure 7. Power On at 9A Load
Figure 8. Power On at 18A Load
Figure 9. Power Off with 0.3A Load
Figure 10. Power Off with 18A Load
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
SG1577A — Dual Synchronous DC/DC Controller
Typical Performance Characteristics
www.fairchildsemi.com
8
Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF and CSS2/ENB=168nF.
Figure 11. Phase Shift at 0.3A Load
Figure 12. Phase Shift at 18A Load
Figure 13. Dead Time at 0.3A Load (Rising Edge)
Figure 14. Dead Time at 0.3A Load (Falling Edge)
Figure 15. Dead Time at 18A Load (Rising Edge)
Figure 16. Dead Time at 18A Load (Falling Edge)
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
SG1577A — Dual Synchronous DC/DC Controller
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
9
Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF and CSS2/ENB=168nF.
Figure 17. Load Transient Response (Step-Up)
20kΩ/22nF in Compensation Loop
Figure 18. Load Transient Response (Step-Down)
20kΩ/22nF in Compensation Loop
Figure 19. Over-Current Protection (OCP)
Figure 20. Over-Current Protection (“Hiccup” Mode)
SG1577A — Dual Synchronous DC/DC Controller
Typical Performance Characteristics (Continued)
150
Iocset 1
IO C S E T (u A )
140
Iocset 2
130
120
110
100
90
-40
-25
-10
5
20
35
50
65
80
95
o
Temperature ( C)
Figure 21. Over-Voltage Protection (OVP)
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
Figure 22. IOCSET vs. Temperature
www.fairchildsemi.com
10
compensation externally. Non-inverting inputs are
internally tied to a fixed 0.7V ± 1.5% reference voltage.
The SG1577A is a dual-channel voltage-mode PWM
controller. It has two sets of synchronous MOSFET
driving circuits. The two channels are running 180degrees out of phase. The following descriptions
highlight the advantages of the SG1577A design.
Oscillator Operation
The SG1577A has a frequency-programmable
oscillator. The oscillator is running at 61kHz when the
RT pin is floating. The oscillator frequency can be
adjusted from 61kHz up to 340kHz by an external
resistor RRT between RT pin and the ground. The
oscillator generates a sawtooth wave that has 90%
rising duty. Sawtooth wave voltage threshold is from
1.2V to 2.8V. The frequency of oscillator can be
programmed according to the following equation:
Soft Start
An internal start-up current (35/15µA) flows out of
SS/EN pin to charge an external capacitor. During the
startup sequence, SG1577A isn’t enabled until the
SS/ENB pin is higher than 1.2V. From 1.2V to (1.2 + 1.6
x DON / DON_MAX) V, the PWM duty cycle gradually
increases following the SS/ENB pin voltage to bring
output rising. After (1.2 + 1.6 x DON / DON_MAX) V, the
soft-start period ends and SS/ENB pin continually rises
to 4.8V. When input power is abnormal, the external
capacitor on the SS pin is shorted to ground and the
chip is disabled.
Output Driver
The high-side gate drivers need an external
bootstrapping circuit to provide the required boost
voltage. The highest gate driver’s output (15V is the
allowed) on high-side and low-side MOSFETs forces
external MOSFETs to have the lowest RDS(ON), which
results in higher efficiency.
5
CSS1 × (1.4V - 1.2V) = 35uA × t1; CSS1 × (1.2V + 1.6 × 12 - 1.4V) = 15µA × t 2
0.9
; t1 + t 2 = t SS1
3.3
CSS2 × (1.4V - 1.2V) = 35µA × t1; CSS2 × (1.2V + 1.6 × 12 - 1.4V) = 15µA × t 2
0.9
; t1 + t 2 = t SS2
CSS1 × 1.2V = 35µA × t 3;
(1)
Over-Temperature Protection (OTP)
CSS2 × 0.3V CSS2 × (1.2V - 0.3V)
+
= t4
15µA
35µA
The device is over-temperature protected. When chip
o
temperature is over 150 C, the chip enters tri-state
o
(high-side driver is turned off). The hysteresis is 20 C.
; t 4 - t 3 = t time - shift
Over-Current Protection (OCP)
Over-current protection is implemented by sensing the
voltage drop across the drain and the source of external
high-side MOSFET. Over-current protection is triggered
when the voltage drop on external high-side MOSFET’s
RDS(ON) is greater than the programmable current limit
voltage threshold. 120µA flowing through an external
resistor between input voltage and the CLP pin sets the
threshold of current limit voltage. When over-current
condition is true, the system is protected against the
cycle-by-cycle current limit. A counter counts a series of
over-current peak values to eight cycles; the soft-start
capacitor is discharged by a 50µA current until the
voltage on SS pin reaches 1.2V. During the discharge
period, the high-side driver is turned off and the lowside driver is turned on. Once the voltage on SS/ENB
pin is under 1.2V, the normal soft-start sequence is
initiated and the 35/15µA current charges the soft-start
capacitor again.
IL(OCP)= [(RSENSE x IOCSET + VOFFSET) / RDS(ON) (VIN - VOUT) x VOUT / (fOSC x LOUT x VIN x 2) ]
(3)
fOSC, RT(kHz) = 61kHz + 8522 / RRT(kΩ)
SG1577A — Dual Synchronous DC/DC Controller
Functional Description
Type II Compensation Design
(for Output Capacitors with High ESR)
SG1577A is a voltage-mode controller; the control loop
is a single voltage feedback path, including an error
amplifier and PWM comparator, as shown in Figure 23.
To achieve fast transient response and accurate output
regulation, an adequate compensator design is
necessary. A stable control loop has a 0dB gain
crossing with -20dB/decade slope and a phase margin
greater than 45°.
(2)
where VOFFSET ( ≒ 10mV) is the offset voltage
contributed by the internal OCP comparator.
Error Amplifier
The IN1 and IN2 pins are connected to the
corresponding internal error amplifier’s inverting input
and the outputs of the error amplifiers are connected to
the corresponding COMP1 and COMP2 pins. The
COMP1 and COMP2 pins are available for control-loop
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
Figure 23. Closed Loop
www.fairchildsemi.com
11
fP(LC) =
1
2π × L O × C O
fP1 = 0
1
2π × CO × ESR
1
2π × R 2 × C 2
fP2 =
1
2π × R 2 × (C1 // C2 )
(6)
Figure 25 shows the DC-DC converter gain vs.
frequency. The compensation gain uses external
impedance networks ZC and Zf to provide a stable, highbandwidth loop.
High crossover frequency is desirable for fast transient
response, but often jeopardizes system stability. To
cancel one of the LC filter poles, place the zero before
the LC filter resonant frequency. Place the zero at 75%
of the LC filter resonant frequency. Crossover frequency
should be higher than the ESR zero, but less than 1/5
of the switching frequency. The second pole should be
placed at half the switching frequency.
(4)
The next step of compensation design is to calculate
the ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough
ESR to satisfy stability requirements. The ESR zero of
the output capacitor is expressed as:
fZ(ESR ) =
fZ1 =
SG1577A — Dual Synchronous DC/DC Controller
1. Modulator Frequency Equations
The modulator transfer function is the small-signal
transfer function of VOUT/VE/A. This transfer function is
dominated by a DC gain and the output filter (LO and
CO) with a double-pole frequency at fLC and a zero at
fESR. The DC gain of the modulator is the input voltage
(VIN) divided by the peak-to-peak oscillator voltage
ΔVRAMP(=1.6V). The first step is to calculate the complex
conjugate poles contributed by the LC output filter. The
output LC filter introduces a double pole,
-40dB / decade gain slope above its corner resonant
frequency, and a total phase lag of 180 degrees. The
resonant frequency of the LC filter expressed as:
(5)
2. Compensation Frequency Equations
The compensation network consists of the error
amplifier and the impedance networks ZC and Zf, as
Figure 24 shows.
Figure 25. Bode Plot
Figure 24. Compensation Loop
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
www.fairchildsemi.com
12
Layout is important in high-frequency switching converter
design. If designed improperly, PCB can radiate
excessive noise and contribute to converter instability.
Place the PWM power stage components first. Mount
all the power components and connections in the top
layer with wide copper areas. The MOSFETs of buck,
inductor, and output capacitor should be as close to
each other as possible to reduce the radiation of EMI
due to the high-frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be
considered. Place the input capacitor near the drain of
high-side MOSFET. In multi-layer PCB, use one layer
as power ground and have a separate control signal
ground as the reference for all signals. To avoid the
signal ground being affected by noise and to achieve
the best load regulation, it should be connected to the
ground terminal of output.
Follow the below guidelines for best performance:
ƒ
Place the bootstrap capacitor near the BSTx and
CLNx pins.
ƒ
The resistor on the RT pin should be near this pin
and the GND return should be short and kept away
from the noisy MOSFET’s GND (which is shorted
together with IC’s PGND pin to GND plane on back
side of PCB).
ƒ
Place the compensation components close to the
INx and COMPx pins.
ƒ
The feedback resistors for both regulators should
be located as close as possible to the relevant INx
pin with vias tied straight to the ground plane as
required.
ƒ
Minimize the length of the connections between the
input capacitors, CIN, and the power switchers
(MOSFETs) by placing them nearby.
ƒ
Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible
and make the GND returns short (from the source
of lower MOSFET to VIN capacitor GND).
ƒ
ƒ
A two-layer printed circuit board is recommended.
Use the bottom layer of the PCB as a ground plane
and make all critical component ground
connections through vias to this layer.
ƒ
ƒ
Keep the metal running from the CLNx terminal to
the output inductor short.
Position the output inductor and output capacitors
between the upper MOSFET and lower MOSFET
and the load.
ƒ
ƒ
Use copper-filled polygons on the top (and bottom,
if two-layer PCB) circuit layers for the CLN node.
AGND should be on the clearer plane and kept
away from the noisy MOSFET GND.
ƒ
ƒ
The small-signal wiring traces from the DLx and
DHx pins to the MOSFET gates should be kept
short and wide enough to easily handle the several
amps of drive current.
PGND should be short, together with MOSFET
GND, then through vias to GND plane on the
bottom of PCB.
ƒ
The critical, small-signal components include any
bypass capacitors (SMD-type of capacitors applied
at VCC and SSx/ENB pins), feedback components
(resistor divider), and compensation components
(between INx and COMPx pins). Position those
components close to their pins with a local, clear,
GND connection or directly to the ground plane.
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
SG1577A — Dual Synchronous DC/DC Controller
Layout Considerations
www.fairchildsemi.com
13
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
0.51
0.35
1.27
0.25
M
10
1.27
0.65
C B A
LAND PATTERN RECOMMENDATION
2.65 MAX
SG1577A — Dual Synchronous DC/DC Controller
Physical Dimensions
SEE DETAIL A
0.33
0.20
C
0.75
0.25
X 45°
0.10 C
0.30
0.10
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
GAGE PLANE
(R0.10)
0.25
8°
0°
1.27
0.40
SEATING PLANE
(1.40)
DETAIL A
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 26. 20-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
www.fairchildsemi.com
14
SG1577A — Dual Synchronous DC/DC Controller
© 2009 Fairchild Semiconductor Corporation
SG1577A • Rev. 1.0.0
www.fairchildsemi.com
15