Panasonic AN44067A Driver ic for stepping motor Datasheet

DATA SHEET
Part No.
AN44067A
Package Code No.
HSOP034-P-0300A
Publication date: October 2008
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AN44067A
Contents
„ Overview ………………………………………………….…………………………………………………………. 3
„ Features ………………………………………………….…………………………………………………………. 3
„ Applications ……….………………………………………………………………………………………………… 3
„ Package ……………………………………………………………………………………………………………. 3
„ Type …………………………………...……………………………………………………………………………. 3
„ Application Circuit Example (Block Diagram)
„ Pin Descriptions
….……………………………………………………………… 4
…………………..………………………………………………………………………………. 5
„ Absolute Maximum Ratings ……………………..……………..…………………………………………………. 6
„ Operating Supply Voltage Range …………..……………………………………………………………………. 6
„ Electrical Characteristics
………………….………………….………………….………………………………. 7
„ Electrical Characteristics (Reference values for design) ………………….………………….………………. 9
„ Technical Data …………………………………….………………….……………………………………………. 10
1. Control mode ……………………….……........………….….…………………………………………………. 10
2. Each phase current value …………………….……........………………….…………………………………. 11
3. Each phase current (timing chart)
4. Timing chart at change of DIR
………...……………….…………………………………………………. 13
…………...................…………….…………………………………………. 17
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AN44067A
AN44067A
Driver IC for stepping motor
„ Overview
AN44067A is s two channel H-bridge driver IC. Bipolar stepping motor can be controlled by a single driver IC.
2 phase excitation, half- step, 1-2 phase excitation, W1-2 phase excitation and 2W1-2 phase excitation can be selected.
„ Features
y Built-in decoder for micro steps
(2 phase excitation, half-step, 1-2 phase excitation, W1-2 phase excitation and 2W1-2 phase excitation)
Stepping motor can be driven by only external clock signal.
y PMW can be driven by built-in CR (3-value can be selected during PWM OFF period.)
Selection during PWM OFF period enables the best PWM drive.
y Mix decay compatible (4-value for fast decay ratio can be selected.)
Mix decay control can improve accuracy of motor current wave form.
y Built -in low voltage detection
If supply voltage lowers less than the range of operating supply voltage, low voltage detection operates and all phases of motor
drive output are turned OFF.
y Built-in thermal protection
If chip junction temperature rises and reaches setup temperature, all phases of motor drive output are turned OFF.
y 1 power supply with built-in 5 V power supply (accuracy ±5%)
Motor can be driven by only 1 power supply because of built-in 5 V power supply.
y Built-in standby function
Operation of standby function can lower current consumption of IC.
y Built-in Home position function
Home position function can detect the position of a motor.
„ Applications
y IC for stepping motor drives
„ Package
y 34 pin plastic small outline package with heat sink (SOP type)
„ Type
y Bi-CDMOS IC
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AN44067A
„ Application Circuit Example (Block Diagram)
0.01 μF
15 VPUMP
CHARGE
PUMP
BC1 13
VM
BC2 14
0.01 μF
BOUT1
Protection of
GND
BOUT2
ENABLE 19
Gate circuit
6 BOUT2
R
TJMON 3
SQ
TEST 25
7 RCSB
TEST
100 kΩ
only
TEST = High-level input
DACB
8 BOUT1
VREF 23
1 VM2
1/10
S5VOUT
UVLO
PWMSW 33
PWMSW
OSC
0.1 μF
TSD
47 μF
UVLO
BLANK
17 VM1
1/10
10 AOUT2
PHA 28
DACA
11 RCSA
R
ST1 31
ST2 30
ST3 29
Micro
step
decoder
QS
DIR 32
DECAY1 21
12 AOUT1
DECAY2 20
Gate circuit
0.1 μF
S5VOUT 24
AMP
BG
VM
VM
STBY 22
Protection of
GND
AOUT1
AOUT2
27 GND
4 GND
STBY
Note) This application circuit is shown as an example but does not guarantee the design for mass production set.
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AN44067A
„ Pin Descriptions
Pin No.
Pin Name
Type
Description
1
VM2
Power supply
2
N.C.
⎯
3
TJMON
Output
VBE monitor / Test output / Home position output
4
GND
Ground
ground
5
N.C.
⎯
6
BOUT2
7
RCSB
8
BOUT1
Output
Phase B motor drive output 1
9
GND
Ground
Die pad ground
10
AOUT2
Output
Phase A motor drive output 2
11
RCSA
12
AOUT1
Output
Phase A motor drive output 1
13
BC1
Output
Charge pump capacitor connection 1
14
BC2
Output
Charge pump capacitor connection 2
15
VPUMP
Output
Charge pump circuit output
16
N.C.
⎯
17
VM1
Power supply
18
N.C.
⎯
19
ENABLE
Input
Enable / disable CTL
20
DECAY2
Input
Mix decay setup 2
21
DECAY1
Input
Mix decay setup 1
22
STBY
Input
Standby
23
VREF
Input
Torque reference voltage input
24
S5VOUT
25
TEST
Input
26
GND
Ground
Die pad ground
27
GND
Ground
Signal ground
28
PHA
Input
Clock input
29
ST3
Input
Step select 3
30
ST2
Input
Step select 2
31
ST1
Input
Step select 1
32
DIR
Input
Rotation direction
33
PWMSW
Input
PWM OFF period selection input
34
N.C.
Output
Input / Output
Input / Output
Output
Motor power supply 2
⎯
⎯
Phase B motor drive output 2
Phase B current detection
Phase A current detection
⎯
Motor power supply 1
⎯
Internal reference voltage (output 5 V)
Test mode
⎯
⎯
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AN44067A
„ Absolute Maximum Ratings
A No.
Parameter
Symbol
Rating
Unit
Note
VM
37
V
*1
1
Supply voltage (pin 1, pin 17)
5
Output pin voltage (pin 6, pin 8, pin 10, pin 12)
VOUT
37
V
*2
6
Motor drive current (pin 6, pin 8, pin 10, pin 12)
IOUT
±2.5
A
*3, *4
7
Flywheel diode current
(pin 6, pin 8, pin 10, pin 12)
If
2.5
A
*3, *4
2
Power dissipation
PD
0.466
W
*5
3
Operating ambient temperature
Topr
–20 to +70
°C
*6
4
Storage temperature
Tstg
–55 to +150
°C
*6
Note) *1: The range under absolute maximum ratings, power dissipation.
*2: This is output voltage rating and do not apply input voltage from outside to these pins. Set not to exceed allowable range at any time.
*3: Do not apply external currents to any pin specially mentioned. For circuit currents, (+) denotes current flowing into the IC and (–) denotes
current flowing out of the IC.
*4: Rating when cooling fin on the back side of the IC is connected to the GND pattern of the glass epoxy 4-layer board.
(GND area: 2nd-layer or 3rd-layer: more than 1 500 mm2 )
In case of no cooling fin on the back side of the IC, rating current is 1.5 A on the glass epoxy 2-layer board.
*5: Power dissipation shows the value of only package at Ta = 70°C.
When using this IC, refer to the 7. PD – Ta diagram in the „ Technical Data and use under the condition not exceeding the allowable value.
*6: Expect for the storage temperature and operating ambient temperature, all ratings are for Ta = 25°C.
„ Operating Supply Voltage Range
Parameter
Supply voltage range
Symbol
Range
Unit
Note
VM
10.0 to 34.0
V
⎯
Note) The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
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AN44067A
„ Electrical Characteristics at VM = 24 V
Note) Ta = 25°C±2°C unless otherwise specified.
B
No.
Parameter
Symbol
Conditions
Limits
Min
Typ
Unit
No
te
⎯
V
⎯
Max
Output drivers
VM
VM
– 0.75 – 0.42
1
High-level output saturation voltage
VOH
I = –1.2 A
2
Low-level output saturation voltage
VOL
I = 1.2 A
⎯
0.54
0.825
V
⎯
3
Flywheel diode forward voltage
VDI
I = 1.2 A
0.5
1.0
1.5
V
⎯
4
Output leakage current
ILEAK
VM = 37 V, VRCS = 0 V
⎯
10
20
μA
⎯
5
Supply current (active)
IM
ENABLE = High, STBY = High
⎯
5.5
10
mA
⎯
6
Supply current (STBY)
IMSTBY
STBY = Low
⎯
25
50
μA
⎯
I/O block
7
High-level STBY input voltage
VSTBYH
⎯
2.1
⎯
5.5
V
⎯
8
Low-level STBY input voltage
VSTBYL
⎯
0
⎯
0.6
V
⎯
9
High-level STBY input current
ISTBYH
STBY = 5 V
25
50
100
μA
⎯
10
Low-level STBY input current
ISTBYL
STBY = 0 V
−2
⎯
2
μA
⎯
11
High-level PHA input voltage
VPHAH
⎯
2.1
⎯
5.5
V
⎯
12
Low-level PHA input voltage
VPHAL
⎯
0
⎯
0.6
V
⎯
13
High-level PHA input current
IPHAH
PHA = 5 V
25
50
100
μA
⎯
14
Low-level PHA input current
IPHAL
PHA = 0 V
−2
⎯
2
μA
⎯
15
Highest-level PHA input frequency
fPHA
⎯
⎯
⎯
100
kHz
⎯
16
High-level ENABLE input voltage
VENABLEH
⎯
2.1
⎯
5.5
V
⎯
17
Low-level ENABLE input voltage
VENABLEL
⎯
0
⎯
0.6
V
⎯
18
High-level ENABLE input current
IENABLEH
ENABLE = 5 V
25
50
100
μA
⎯
19
Low-level ENABLE input current
IENABLEL
ENABLE = 0 V
−2
⎯
2
μA
⎯
20
High-level PWMSW input voltage
VPWMSWH
⎯
2.3
⎯
5.5
V
⎯
21
Middle-level PWMSW input voltage
VPWMSWM
⎯
1.3
⎯
1.7
V
⎯
22
Low-level PWMSW input voltage
VPWMSWL
⎯
0
⎯
0.6
V
⎯
23
High-level PWMSW input current
IPWMSWH
PWMSW = 5 V
40
83
150
μA
⎯
24
Low-level PWMSW input current
IPWMSWL
PWMSW = 0 V
–70
–36
–18
μA
⎯
25
PWMSW voltage at open
VPWMSWO
1.3
1.5
1.7
V
⎯
⎯
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AN44067A
„ Electrical Characteristics at VM = 24 V (continued)
Note) Ta = 25°C±2°C unless otherwise specified.
B
No.
Parameter
Symbol
Conditions
Limits
Min
Typ
Max
Unit
No
te
I/O block (continued)
26
High-level DECAY input voltage
VDECAYH
⎯
2.1
⎯
5.5
V
⎯
27
Low-level DECAY input voltage
VDECAYL
⎯
0
⎯
0.6
V
⎯
28
High-level DECAY input current
IDECAYH
DECAY1 = DECAY2 = 5 V
25
50
100
μA
⎯
29
Low-level DECAY input current
IDECAYL
DECAY1 = DECAY2 = 0 V
−2
⎯
2
μA
⎯
30
High-level DIR input voltage
VDIRH
⎯
2.1
⎯
5.5
V
⎯
31
Low-level DIR input voltage
VDIRL
⎯
0
⎯
0.6
V
⎯
32
High-level DIR input current
IDIRH
DIR = 5 V
25
50
100
μA
⎯
33
Low-level DIR input current
IDIRL
DIR = 0 V
−2
⎯
2
μA
⎯
34
High-level ST input voltage
VSTH
⎯
2.1
⎯
5.5
V
⎯
35
Low-level ST input voltage
VSTL
⎯
0
⎯
0.6
V
⎯
36
High-level ST input current
ISTH
ST1 = ST2 = ST3 = 5 V
25
50
100
μA
⎯
37
Low-level ST input current
ISTL
ST1 = ST2 = ST3 = 0 V
−2
⎯
2
μA
⎯
38
High-level TEST input voltage
VTESTH
⎯
4.0
⎯
5.5
V
⎯
39
Middle-level TEST input voltage
VTESTM
⎯
2.3
⎯
2.7
V
⎯
40
Low-level Test input voltage
VTESTL
⎯
0
⎯
0.6
V
⎯
41
High-level TEST input current
ITESTH
TEST = 5 V
25
50
100
μA
⎯
42
Low-level TEST input current
ITESTL
TEST = 0 V
−2
⎯
2
μA
⎯
Torque control block
43
Input bias current 1
IREFH
VREF = 5 V
−15
⎯
5
μA
⎯
44
Input bias current 2
IREFL
VREF = 0 V
−2
⎯
2
μA
⎯
45
PWM OFF time 1
TOFF1
PWMSW = L
16.8
28
39.2
μs
⎯
46
PWM OFF time 2
TOFF2
PWMSW = M
9.1
15.2
21.3
μs
⎯
47
PWM OFF time 3
TOFF3
PWMSW = H
4.9
8.1
11.3
μs
⎯
48
Pulse blanking time
TB
VREF = 0 V
0.4
0.7
1.0
μs
⎯
49
Comp threshold
VTCMP
VREF = 5 V
475
500
525
mV
⎯
Reference voltage block
50
Reference voltage
VS5VOUT
IS5VOUT = 0 mA
4.75
5.0
5.25
V
⎯
51
Output impedance
ZS5VOUT
IS5VOUT = –7 mA
⎯
⎯
10
Ω
⎯
Pull up TJMON pin to 5 V
with 100 kΩ.
⎯
0.1
0.3
V
⎯
VTJMON = 5 V
⎯
⎯
5
μA
⎯
Home position block
52
At TEST high-level input
TJMON output Low-level voltage
53
At TEST high-level input
TJMON output leakage current
VTJL
ITJ(leak)
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AN44067A
„Electrical Characteristics (Reference values for design) at VM = 24 V
Note) Ta = 25°C±2°C unless otherwise specified.
The characteristics listed below are reference values for design of the IC and are not guaranteed by inspection.
If a problem does occur related to these characteristics, Panasonic will respond in good faith to user concerns.
B
No.
Parameter
Symbol
Conditions
Limits
Min
Typ
Max
Unit
No
te
Output drivers
54
Output slew rate 1
VTr
Output voltage rise
⎯
220
⎯
V/μs
⎯
55
Output slew rate 2
VTf
Output voltage fall
⎯
200
⎯
V/μs
⎯
56
Dead time
TD
⎯
⎯
0.8
⎯
μs
⎯
Thermal protection
57
Thermal protection operating
temperature
TSDon
⎯
⎯
150
⎯
°C
⎯
58
Thermal protection hysteresis width
ΔTSD
⎯
⎯
40
⎯
°C
⎯
Low voltage protection
59
Protection operating voltage
VUVLO1
⎯
⎯
7.9
⎯
V
⎯
60
Protection releasing voltage
VUVLO2
⎯
⎯
8.7
⎯
V
⎯
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AN44067A
„ Technical Data
1. Control mode
1) Truth table (step select)
Output excitation mode
(phase B 90° delay: to phase A)
ENABLE
DIR
ST1
ST2
ST3
High
⎯
⎯
⎯
⎯
Low
Low
Low
Low
Low
2 phase excitation drive (4-step sequence)
Low
Low
Low
High
Low
Half-step drive (8-step sequence)
Low
Low
High
Low
Low
1-2 phase excitation drive (8-step sequence)
Low
Low
High
High
Low
W1-2 phase excitation drive (16-step sequence)
Low
Low
⎯
⎯
High
2W1-2 phase excitation drive (32-step sequence)
ENABLE
DIR
ST1
ST2
ST3
High
⎯
⎯
⎯
⎯
Low
High
Low
Low
Low
2 phase excitation drive (4-step sequence)
Low
High
Low
High
Low
Half-step drive (8-step sequence)
Low
High
High
Low
Low
1-2 phase excitation drive (8-step sequence)
Low
High
High
High
Low
W1-2 phase drive (16-step sequence)
Low
High
⎯
⎯
High
2W1-2 phase drive (32-step sequence)
Output OFF
Output excitation mode
(phase B 90° advance: to phase A)
Output OFF
2) Truth table (control/charge pump circuit)
STBY
ENABLE
Control
/Charge pump circuit
Output transistor
Low
—
OFF
OFF
High
High
ON
OFF
High
Low
ON
ON
3) Truth table (PWM OFF period selection)
PWMSW
PWM OFF period
Low
28.0 μs
Middle
15.2 μs
High
8.1 μs
5) Truth table (test mode)
4) Truth table (decay selection)
DECAY1
DECAY2
Decay control
TEST
TJMON
Low
Low
Slow decay
Low
VBE monitor
Low
High
25%
Middle
High
Low
50%
Test output
(Output transistor: OFF)
High
High
100%
High
Home position output
Note) For each PWM OFF period, Fast decay is applied according to the above table.
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AN44067A
„ Technical Data (continued)
2. Each phase current value
1) 1-2 phase, W1-2 phase, 2W1-2 phase DIR = Low
Note) The definition of Phase A and B current 100%: (VREF × 0.1) / current detection resistance
1-2 phase
(8 step)
W1-2 phase
(16 step)
1
1
2
3
2
4
5
3
6
7
4
8
9
5
10
11
6
12
13
7
14
15
8
16
2W1-2 phase
(32 step)
Phase A current (%)
Phase B current (%)
1
19.5
–98.1
2
38.3
–92.4
3
55.6
–83.2
4
70.7
–70.7
5
83.2
–55.6
6
92.4
–38.3
7
98.1
–19.5
8
100
0
9
98.1
19.5
10
92.4
38.3
11
83.2
55.6
12
70.7
70.7
13
55.6
83.2
14
38.3
92.4
15
19.5
98.1
16
0
100
17
–19.5
98.1
18
–38.3
92.4
19
–55.6
83.2
20
–70.7
70.7
21
–83.2
55.6
22
–92.4
38.3
23
–98.1
19.5
24
–100
0
25
–98.1
–19.5
26
–92.4
–38.3
27
–83.2
–55.6
28
–70.7
–70.7
29
–55.6
–83.2
30
–38.3
–92.4
31
–19.5
–98.1
32
0
–100
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AN44067A
„ Technical Data (continued)
2. Each phase current value (continued)
2) 1-2 phase, W1-2 phase, 2W1-2 phase DIR = High
Note) The definition of Phase A and B current 100%: (VREF × 0.1) / current detection resistance
1-2 phase
(8 step)
W1-2 phase
(16 step)
1
1
2
3
2
4
5
3
6
7
4
8
9
5
10
11
6
12
13
7
14
15
8
16
2W1-2 phase
(32 step)
Phase A current (%)
Phase B current (%)
1
–19.5
–98.1
2
–38.3
–92.4
3
–55.6
–83.2
4
–70.7
–70.7
5
–83.2
–55.6
6
–92.4
–38.3
7
–98.1
–19.5
8
–100
0
9
–98.1
19.5
10
–92.4
38.3
11
–83.2
55.6
12
–70.7
70.7
13
–55.6
83.2
14
–38.3
92.4
15
–19.5
98.1
16
0
100
17
19.5
98.1
18
38.3
92.4
19
55.6
83.2
20
70.7
70.7
21
83.2
55.6
22
92.4
38.3
23
98.1
19.5
24
100
0
25
98.1
–19.5
26
92.4
–38.3
27
83.2
–55.6
28
70.7
–70.7
29
55.6
–83.2
30
38.3
–92.4
31
19.5
–98.1
32
0
–100
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AN44067A
„ Technical Data (continued)
3. Each phase current (timing chart)
1) 2 phase excitation drive (4-step sequence)
(ST1 = Low, ST2 = Low, ST3 = Low)
1
2
3
4
1
2
3
4
1
1
2
3
4
1
2
3
4
1
CLK
CLK
+100%
+100%
0%
IAOUT1
IBOUT1
0%
IAOUT1
–100%
–100%
+100%
+100%
0%
IBOUT1
0%
–100%
–100%
REV
(DIR = High)
FWD
(DIR = Low)
2) Half-step drive (8-step sequence)
(ST1 = Low, ST2 = High, ST3 = Low)
1
2
3
4
5
6
7
8
1
1
2
3
4
5
6
7
8
1
CLK
CLK
+100%
+100%
0%
IAOUT1
IBOUT1
0%
IAOUT1
–100%
–100%
+100%
+100%
0%
IBOUT1
0%
–100%
–100%
REV
(DIR = High)
FWD
(DIR = Low)
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AN44067A
„ Technical Data (continued)
3. Each phase current (timing chart) (continued)
3) 1-2 phase excitation (8-step sequence)
(ST1 = High, ST2 = Low, ST3 = Low)
1
2
3
4
5
6
7
8
1
1
CLK
2
3
4
5
6
7
8
1
CLK
+100%
IAOUT1
0%
IBOUT1
+100%
0%
IAOUT1
–100%
–100%
+100%
+100%
0%
IBOUT1
0%
–100%
–100%
REV
(DIR = High)
FWD
(DIR = Low)
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AN44067A
„ Technical Data (continued)
3. Each phase current (timing chart) (continued)
4) W1-2 phase excitation (16-step sequence)
(ST1 = High, ST2 = High, ST3 = Low)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLK
+100%
IAOUT1
0%
–100%
+100%
IBOUT1
0%
–100%
FWD
(DIR = Low)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLK
+100%
IAOUT1
0%
–100%
+100%
IBOUT1
0%
–100%
REV
(DIR = High)
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AN44067A
„ Technical Data (continued)
3. Each phase current (timing chart) (continued)
5) 2W1-2 phase excitation (32-step sequence)
(ST3 = High)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1
CLK
+100%
0%
IAOUT1
–100%
+100%
IBOUT1
0%
–100%
FWD
(DIR = Low)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1
CLK
+100%
0%
IAOUT1
–100%
+100%
0%
IBOUT1
–100%
REV
(DIR = High)
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16
AN44067A
„ Technical Data (continued)
4. Timing chart at change of DIR
(Ex.1) Timing chart at 1-2 phase excitation (DIR: Low → High)
PHA
DIR
A-ch.
motor current
B-ch.
motor current
State : 5
6
7
6
7
6
5
At change of DIR, the state before the change is held and the operation is continued.
(Ex.2) Timing chart at 1-2 phase excitation (DIR: High → Low)
PHA
DIR
A-ch.
motor current
B-ch.
motor current
State
: 3
4
5
4
3
2
1
At change of DIR, the state before the change is held and the operation is continued.
SDL00012BEB
17
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(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
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