AD AD5544ARS Quad, current-output, serial-input 16-/14-bit dac Datasheet

Quad, Current-Output,
Serial-Input 16-/14-Bit DACs
AD5544/AD5554
FEATURES
SPI®-compatible 3-wire interface
Double buffered registers enable
Simultaneous multichannel change
Internal power ON reset
Compact SSOP-28 package
VREFA B C D
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
SDO
SDI
RFBA
INPUT
REGISTER R
DAC A
REGISTER R
DAC A
IOUTA
AGNDA
RFBB
16
INPUT
REGISTER R
DAC B
REGISTER R
DAC B
IOUTB
AGNDB
RFBC
INPUT
REGISTER R
DAC C
REGISTER R
DAC C
IOUTC
AGNDC
CS
CLK
RFBD
EN
INPUT
REGISTER R
DAC A
B
C
D
2:4
DECODE
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
DAC D
REGISTER R
DAC D
IOUTD
AGNDD
POWERON
RESET
DGND
RS
MSB
AD5544
LDAC
AGNDF
00943-0-001
AD5544 16-bit resolution
AD5554 14-bit resolution
2 mA full-scale current ±20%, with VREF = ±10 V
2 µs settling time
VSS BIAS for zero-scale error reduction @ temp
midscale or zero-scale reset
Four separate, 4-Q multiplying reference inputs
FUNCTIONAL BLOCK DIAGRAM
VSS
Figure 1.
GENERAL DESCRIPTION
1.0
The AD5544/AD5554 quad, 16-/14-bit, current-output, digital
to-analog converters are designed to operate from a single
5 V supply.
DAC A
0.5
0
–0.5
The applied external reference input voltage (VREF) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
DAC B
0.5
0
INL (LSB)
–0.5
–1.0
1.0
DAC C
0.5
0
–0.5
–1.0
1.0
DAC D
0.5
0
–0.5
–1.0
0
8192
16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
00943-0-002
A double-buffered serial-data interface offers high speed,
3-wire, SPI- and microcontroller-compatible inputs using serialdata-in (SDI), a chip-select (CS), and clock (CLK) signals. In
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common, level-sensitive,
load-DAC strobe (LDAC) input allows the simultaneous update
of all DAC outputs from previously loaded input registers.
Additionally, an internal power ON reset forces the output
voltage to zero at system turn ON. An MSB pin allows system
reset assertion (RS) to force all registers to zero code when
MSB = 0, or to half-scale code when MSB = 1.
–1.0
1.0
Figure 2. AD5544 INL vs. Code Plot (TA = 25°C)
The AD5544/AD5554 are packaged in the compact SSOP-28.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5554/AD5554
TABLE OF CONTENTS
Specifications..................................................................................... 3
Circuit Operation ........................................................................... 14
AD5544 Electrical Characteristics ............................................. 3
D/A Converter ............................................................................ 14
AD5554 Electrical Characteristics ............................................. 4
Serial Data Interface....................................................................... 16
Absolute Maximum Ratings............................................................ 6
Power On Reset .......................................................................... 17
ESD Caution.................................................................................. 6
Applications ................................................................................ 17
Pin Configuration and Function Descriptions............................. 7
Outline Dimensions ....................................................................... 18
Typical Performance Characteristics ........................................... 10
Ordering Guide .......................................................................... 18
REVISION HISTORY
12/04—Rev. 0 to Rev. A
Updated Format...................................................................... Universal
Change to Electrical Characteristics Tables .......................................4
Change to Pin Description Table.......................................................10
Addition of Power Supply Sequence Section...................................19
Addition of Layout and Power Supply Bypassing Section .............19
Addition of Grounding Section.........................................................19
Addition of Figure 32..........................................................................19
4/00—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD5544/AD5554
SPECIFICATIONS
AD5544 ELECTRICAL CHARACTERISTICS
VDD = 5 V ±10%, VSS = 0 V, IOUTX = virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless
otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
REFERENCE INPUT
VREFX Range
Input Resistance
Input Resistance Match
Input Capacitance2
ANALOG OUTPUT
Output Current
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
INTERFACE TIMING2, 3
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Clock to SDO Prop Delay
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup
Load Hold
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
Symbol
Condition
N
INL
DNL
IOUTX
IOUTX
GFSE
TCVFS
RFBX
1 LSB = VREF/216 = 153 µV when VREF = 10 V
VREFX
RREFX
RREFX
CREFX
IOUTX
COUTX
VIL
VIH
IIL
CIL
VOL
VOH
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA max
Data = FFFFH
VDD = 5 V
4
−15
4
Data = FFFFH
Code-dependent
Typ
±0.75
1
6
Max
Unit
16
±4
±1.5
10
20
±3
Bits
LSB
LSB
nA
nA
mV
ppm/°C
kΩ
8
+15
8
V
kΩ
%
pF
2.5
mA
pF
0.8
4
V
V
µA
pF
V
V
25
25
0
25
2
25
20
20
5
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Channel-to-channel
6
1
5
1.25
80
2.4
IOL = 1.6 mA
IOH = 100 µA
tCH
tCL
tCSS
tCSH
tPD
tLDAC
tDS
tDH
tLDS
tLDH
VDD RANGE
IDD
ISS
PDISS
PSS
Min
1
10
0.4
20
4.5
Logic inputs = 0 V
Logic inputs = 0 V, VSS = –5 V
Logic inputs = 0 V
∆VDD = ±5%
Rev. A | Page 3 of 20
50
0.001
5.5
250
1
1.25
0.006
V
µA
µA
mW
%/%
AD5554/AD5554
Parameter
AC CHARACTERISTICS4
Output Voltage Settling Time
Output Voltage Settling Time
Symbol
Condition
tS
To ±0.1% of full scale, data = 0000H to FFFFH to
0x0000
To ±0.0015% of full scale, data = 0000H to FFFFH to
0000H
VREFX = 100 mV rms, data = FFFFH, CFB = 15 pF
VREFX = 10 V, data 0000H to 8000H to 0000H
Data = 0000H, VREFX = 100 mV rms, f = 100 kHz
Data = 0000H, VREFB = 100 mV rms, adjacent
channel, f = 100 kHz
CS = 1, and fCLK = 1 MHz
VREF = 5 V p-p, data = FFFFH, f = 1 kHz
f = 1 kHz, BW = 1 Hz
tS
Reference Multiplying BW
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
BW − 3 dB
Q
VOUTX/VREFX
VOUTA/VREFB
Digital Feedthrough
Total Harmonic Distortion
Output Spot Noise Voltage
Q
THD
eN
Min
Typ
Max
1
Unit
µs
2
µs
2
12
−65
−90
MHz
nV-s
dB
dB
5
−90
7
nV-s
dB
nV√Hz
1
All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 RFB terminal is
tied to the amplifier output. Typical values represent average readings measured at 25 °C.
These parameters are guaranteed by design and not subject to production testing.
3
All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4
All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.
2
AD5554 ELECTRICAL CHARACTERISTICS
VDD = 5 V ±10%, VSS = 0 V, IOUTX = virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless
otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
REFERENCE INPUT
VREFX Range
Input Resistance
Input Resistance Match
Input Capacitance2
ANALOG OUTPUT
Output Current
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
Symbol
Condition
N
INL
DNL
IOUTX
IOUTX
GFSE
TCVFS
RFBX
1 LSB = VREF/214 = 610 µV when VREF = 10 V
VREFX
RREFX
RREFX
CREFX
IOUTX
COUTX
VIL
VIH
IIL
CIL
VOL
VOH
Min
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA Max
Data = 3FFFH
VDD = 5 V
4
−15
4
Channel-to-channel
Data = 3FFFH
Code-dependent
Typ
±2
1
6
6
1
5
1.25
Max
Unit
14
±1
±1
10
20
±10
Bits
LSB
LSB
nA
nA
mV
ppm/°C
kΩ
8
+15
8
V
kΩ
%
pF
2.5
mA
pF
0.8
V
V
µA
pF
V
V
80
2.4
IOL = 1.6 mA
IOH = 100 µA
Rev. A | Page 4 of 20
1
10
0.4
4
AD5544/AD5554
Parameter
INTERFACE TIMING2, 3
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Clock to SDO Prop Delay
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup
Load Hold
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
AC CHARACTERISTICS4
Output Voltage Settling Time
Output Voltage Settling Time
Symbol
Condition
tCH
tCL
tCSS
tCSH
tPD
tLDAC
tDS
tDH
tLDS
tLDH
VDD RANGE
IDD
ISS
PDISS
PSS
tS
tS
Reference Multiplying BW
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
BW – 3 dB
Q
VOUTX/VREFX
VOUTA/VREFB
Digital Feedthrough
Total Harmonic Distortion
Output Spot Noise Voltage
Q
THD
eN
Min
Typ
25
25
0
25
2
25
20
20
5
25
Max
20
4.5
5.5
250
1
1.25
0.006
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
µA
µA
mW
%/%
Logic inputs = 0 V
Logic inputs = 0 V, VSS = –5 V
Logic inputs = 0 V
∆VDD = ±5%
50
0.001
To ±0.1% of full scale, data = 0000H to 3FFFH to 0000H
To ±0.0015% of full scale, data = 0000H to 3FFFH
to 0000H
VREFX = 100 mV rms, data = 3FFFH, CFB = 15 pF
VREFX = 10 V, data 0000H to 2000H to 0000H
Data = 0000H, VREFX = 100 mV rms, f = 100 kHz
Data = 0000H, VREFB = 100 mV rms, adjacent channel,
f = 100 kHz
CS = 1, and fCLK = 1 MHz
VREF= 5 V p-p, data = 3FFFH, f = 1 kHz
f = 1 kHz, BW = 1 Hz
1
2
µs
µs
2
12
–65
–90
MHz
nV-s
dB
dB
5
–90
7
nV-s
dB
nV√Hz
1
All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554 RFB terminal is
tied to the amplifier output. Typical values represent average readings measured at 25°C.
These parameters are guaranteed by design and not subject to production testing.
3
All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4
All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.
2
Rev. A | Page 5 of 20
AD5554/AD5554
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to GND
VSS to GND
VREF to GND
Logic Input and Output to GND
V(IOUT) to GND
AGNDX to DGND
Input Current to Any Pin Except Supplies
Package Power Dissipation
Thermal Resistance
28-Lead Shrink Surface-Mount (RS-28)
Maximum Junction Temperature (TJ Max)
Operating Temperature Range: Model A
Storage Temperature Range
Lead Temperature:
RS-28 (Vapor Phase, 60 secs)
RS-28 (Infrared, 15 secs)
Rating
−0.3 V, +8 V
+0.3 V, −7 V
−18 V, +18 V
−0.3 V, +8 V
−0.3 V, VDD+ 0.3 V
−0.3 V, + 0.3 V
±50 mA
(TJ Max − TA)/θJA
θJA
100°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 20
AD5544/AD5554
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGNDA 1
28
AGNDD
IOUTA 2
27
IOUTD
VREF A 3
26
VREFD
RFBA 4
25
RFBD
24
DGND
23
VSS
MSB 5
AD5544/
AD5554
RS 6
VDD 7
22 AGNDF
TOP VIEW
CS 8 (Not to Scale) 21 LDAC
20
SDI 10
19
SDO
NC
RFBB 11
18
RFBC
VREF B 12
17
VREFC
IOUTB 13
16
IOUTC
AGNDB 14
15
AGNDC
NC = NO CONNECT
00943-0-005
CLK 9
Figure 3. AD5544/AD5554 Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
1
2
3
4
5
6
Name
AGNDA
IOUTA
VREFA
RFBA
MSB
RS
7
8
VDD
CS
9
10
11
12
13
14
15
16
17
18
19
20
CLK
SDI
RFBB
VREFB
IOUTB
AGNDB
AGNDC
IOUTC
VREFC
RFBC
NC
SDO
21
LDAC
22
23
24
25
26
27
28
AGNDF
VSS
DGND
RFBD
VREFD
IOUTD
AGNDD
Function
DAC A Analog Ground.
DAC A Current Output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.
Establish voltage output for DAC A by connecting to external amplifier output.
MSB Bit. Set pin during a reset pulse (RS) or at system power ON if tied to ground or VDD.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD5544
and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB = 0.
Register Data = 8000H for AD5544 and 2000H.
Positive Power Supply Input. Specified range of operation 5 V ±10%.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input
register when CS/LDAC returns high. Does not effect LDAC operation.
Clock Input. Positive edge clocks data into shift register.
Serial Data Input. Input data loads directly into the shift register.
Establish voltage output for DAC B by connecting to external amplifier output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.
DAC B Current Output.
DAC B Analog Ground.
DAC C Analog Ground.
DAC C Current Output.
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.
Establish voltage output for DAC C by connecting to external amplifier output.
No Connect. Leave pin unconnected.
Serial Data Output. Input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD5544
and 17 clock pulses for AD5554 after input at the SDI pin.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous
active low input. See Table 5 and Table 6 for operation.
High Current Analog Force Ground.
Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
Digital Ground Pin.
Establish Voltage Output for DAC D by Connecting to External Amplifier Output.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.
DAC D Current Output.
DAC D Analog Ground.
Rev. A | Page 7 of 20
AD5554/AD5554
SDI
A1
A0
D15
D14
D13
D12
D11
D10
D1
D0
INPUT
REG
LD
CLK
tDS
tCSS
CS
tDH
tCH
tCL
tCSH
tLDS
LDAC
tLDH
tLDAC
00943-0-003
tPD
SDO
Figure 4. AD5544 Timing Diagram
A1
A0
D13
D12
D11
D10
D09
D08
D1
D0
INPUT
REG
LD
CLK
tDS
tCSS
CS
tDH
tCH
tCL
tCSH
tLDS
LDAC
tPD
tLDH
tLDAC
SDO
00943-0-004
SDI
Figure 5. AD5554 Timing Diagram
Table 5. AD55441 Control-Logic Truth Table
CS
CLK
LDAC
RS
MSB
Serial Shift Register Function
Input Register Function
DAC Register
H
L
L
X
L
↑+
H
H
H
H
H
H
X
X
X
Latched
Latched
Latched
Latched
Latched
Latched
L
↑+
H
L
H
H
H
H
X
X
No Effect
No Effect
Shift-Register-Data Advanced
One Bit
No Effect
No Effect
Latched
Latched
H
H
H
X
X
X
L
H
H
H
H
X
X
X
No Effect
No Effect
No Effect
Latched
Selected DAC Updated with Current
SR Contents
Latched
Latched
Latched
Transparent
Latched
Latched
H
H
X
X
L
L
0
H
No Effect
No Effect
Latched Data = 0000H
Latched Data = 8000H
Latched Data = 0000H
Latched Data = 8000H
1
↑+
H
H
For the AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.
Rev. A | Page 8 of 20
AD5544/AD5554
Table 6. AD55541 Control-Logic Truth Table
CS
CLK
H
L
L
X
L
L
LDAC
RS
MSB
3
Serial Shift Register2 Function
Input Register2 Function
DAC Register
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched Data = 0000H
Latched Data = 2000H
↑+2
H
H
H
H
H
H
X
X
X
↑+2
H
L
H
H
H
H
X
X
No Effect
No Effect
Shift-Register-Data Advanced
One Bit
No Effect
No Effect
H
H
H
X
X
X
L
H
H
H
H
X
X
X
No Effect
No Effect
No Effect
Latched
Selected DAC Updated with Current
Shift-Register Contents4
Latched
Latched
Latched
H
H
X
X
L
L
0
H
No Effect
No Effect
Latched Data = 0000H
Latched Data = 2000H
↑+
H
H
1
For the AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.
↑+ positive logic transition.
3
X = don’t care.
4
At power on both the input register and the DAC register are loaded with all zeros.
2
Table 7. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
B17
A1
Bit Position
Data Word
1
B16
A0
B15
D15
B14
D14
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (Bits D15 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0. Any
extra bits clocked into the AD5544 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC registers.
Table 8. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
Bit Position
Data Word
1
MSB
B15
A1
B14
A0
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point an
internally generated load strobe transfers the serial register data contents (Bits D13 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0.
Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be
tied logic low to disable the DAC registers.
Table 9. Address Decode
A1
0
0
1
1
A0
0
1
0
1
DAC Decoded
DAC A
DAC B
DAC C
DAC D
Rev. A | Page 9 of 20
AD5554/AD5554
TYPICAL PERFORMANCE CHARACTERISTICS
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
0.25
0
–0.25
DAC A
0.50
0.25
–0.25
DAC B
–0.50
DNL (LSB)
DNL (LSB)
0
0.50
0.25
0
–0.25
DAC C
–0.50
0.25
0
DAC D
0
8192
16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
00943-0-006
–0.25
DAC B
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
0.50
–0.50
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
DAC C
DAC D
0
Figure 6. AD5544 DNL vs. Code, TA = 25°C
1.0
INTEGRAL NONLINEARITY ERROR (LSB)
–0.5
–1.0
DAC B
0.5
0
–1.0
DAC C
0.5
0
–1.0
1.0
0
–0.5
0
2048
4096
6144
8192
10240 12288 14336 16384
CODE (Decimal)
VDD = 5V
VREF = 10V
TA = 25°C
F000H
1.0
8000H
0.5
0
7FFFH
–0.5
0FFFH
–1.0
–1.5
–1000
0
–500
500
OP AMP OFFSET VOLTAGE (µV)
1000
1500
Figure 9. AD5544 Integral Nonlinearity Error vs. Op Amp Offset
DAC D
0.5
–1.0
1.5
–2.0
–1500
–0.5
00943-0-007
INL (LSB)
–0.5
1.0
6144
8192
10240 12288 14336 16384
CODE (Decimal)
2.0
0
1.0
4096
Figure 8. AD5554 DNL vs. Code, TA = 25°C
DAC A
0.5
2048
Figure 7. AD5554 INL vs. Code, TA = 25°C
Rev. A | Page 10 of 20
00943-0-009
–0.50
DAC A
00943-0-008
0.50
AD5544/AD5554
10.0
VDD = 5V
VREF = 10V
TA = 25°C
0.50
VDD = 5V
VREF = 10V
TA = 25°C
7.5
3000H
GAIN ERROR (LSB)
5.0
0.25
2000H
0
1FFFH
–0.25
0FFFH
2.5
0
–2.5
–5.0
–0.50
–0.75
0
–2000 –1500 –1000 –500
500
1000
OP AMP OFFSET VOLTAGE (µV)
1500
2000
–10.0
–1500
Figure 10. AD5554 Integral Nonlinearity Error vs. Op Amp Offset
GAIN ERROR (LSB)
F000H
0FFFH
–0.25
–0.50
–0.75
0
–1
–2
–750
0
–500 –250
250
500
OP AMP OFFSET VOLTAGE (µV)
750
1000
–5
–1500
–1000
0
–500
500
OP AMP OFFSET VOLTAGE (µV)
1000
1500
00943-0-014
–4
1.5
00943-0-015
–1.00
–1000
1
–3
00943-0-011
DIFFERENTIAL NONLINEARITY ERROR (LSB)
2
0
Figure 14. AD5554 Gain Error vs. Op Amp Offset
Figure 11. AD5544 Differential Nonlinearity Error vs. Op Amp Offset
0.3
30
VDD = 5V
VREF = 10V
TA = 25°C
SS = 120 UNITS
VDD = 5V
VREF = 10V
TA = –40°C TO +85°C
2000H
3000H
20
FREQUENCY
0.1
0
0FFFH
–0.1
10
ACCURACY DEGRADATION
DUE TO EXTERNAL OP AMP
INPUT OFFSET VOLTAGE
SPECIFICATION.
–0.2
–1000
0
–500
500
OP AMP OFFSET VOLTAGE (µV)
1000
1500
00943-0-012
DIFFERENTIAL NONLINEARITY ERROR (LSB)
1500
VDD = 5V
VREF = 10V
TA = 25°C
3
8000H
0.25
–0.3
–1500
1000
4
VDD = 5V
VREF = 10V
TA = 25°C
0.50
0.2
0
–500
500
OP AMP OFFSET VOLTAGE (µV)
Figure 13. AD5544 Gain Error vs. Op Amp Offset
1.00
0.75
–1000
00943-0-013
–7.5
00943-0-010
INTEGRAL NONLINEARITY ERROR (LSB)
0.75
0
0
0.5
1.0
FULL-SCALE TEMPCO (ppm/°C)
Figure 15. AD5544 Full-Scale Tempco (ppm/°C)
Figure 12. AD5554 Differential Nonlinearity Error vs. Op Amp Offset
Rev. A | Page 11 of 20
AD5554/AD5554
50
SS = 180 UNITS
VDD = 5V
VREF = 10V
TA = –40°C TO +85°C
VDD = 5V
VREF = 10V
TA = 25°C
AV = –343
1LSB = 52mV
30
VOUT
(10V/DIV)
VOUT
(50mV/DIV)
00943-0-019
20
10
00943-0-016
1µs/DIV
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
FULL-SCALE ERROR TEMPCO (ppm/°C)
1.8
Figure 19. AD5544 Small Signal Settling Time
Figure 16. AD5554 Full-Scale Tempco (ppm/°C)
7FFFH
8000H
10000
VDD = 5V
VREF = 10V
TA = 25°C
VDD = 5V
VREF = 10V
TA = 25°C
CS
(5V/DIV)
5555H
FFFFH
8000H
IDD (µA)
1000
VOUT
(50mV/DIV)
0000H
100ns/DIV
10
1k
Figure 17. AD5544 Midscale Transition
FFFFH
VDD = 5V
VREF = 10V
TA = 25°C
100k
1M
CLOCK FREQUENCY (Hz)
10M
100M
Figure 20. AD5544 Power Supply Current vs. Clock Frequency
10000
VDD = 5V
VREF = 10V
TA = 25°C
CS
(5V/DIV)
1555H
3FFFH
2000H
IDD (µA)
1000
VOUT
(5V/DIV)
0000H
100
00943-0-018
0000H
10k
00943-0-020
00943-0-017
100
2µs/DIV
10
1k
Figure 18. AD5544 Large Signal Settling Time
10k
100k
1M
CLOCK FREQUENCY (Hz)
10M
100M
Figure 21. AD5554 Power Supply Current vs. Clock Frequency
Rev. A | Page 12 of 20
00943-0-021
FREQUENCY
40
AD5544/AD5554
100
90
600
VDD = 5V ±10%
TA = 25°C
VDD = 5V
VREF = 10V
TA = 25°C
500
80
IDD (µA)
PSRR (dB)
400
70
60
50
300
200
40
100
1k
10k
100k
CLOCK FREQUENCY (Hz)
1M
0
0
55
SUPPLY CURRENT (µA)
53
VDD = 5V
VREF = 10V
LOGIC = VDD
52
51
50
49
48
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
00943-0-023
47
46
–50
2
3
LOGIC INPUT VOLTAGE (V)
4
5
Figure 24. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage
Figure 22. AD5544/AD5554 Power Supply Rejection vs. Frequency
54
1
00943-0-024
20
100
00943-0-022
30
Figure 23. AD5544/AD5554 Power Supply Current vs. Temperature
Rev. A | Page 13 of 20
AD5554/AD5554
CIRCUIT OPERATION
Each part contains four current-steering R-2R ladder DACs.
Figure 25 shows a typical equivalent DAC. Each DAC contains a
matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin connects to the output of the
external amplifier. The IOUTX terminal connects to the inverting
input of the external amplifier. The AGNDX pin should be Kelvinconnected to the load point requiring full 16-bit accuracy. These
DACs are designed to operate with both negative or positive
reference voltage. The VDD power pin is only used by the logic to
drive the DAC switches on and off. Note that a matching switch
is used in series with the internal 5 kΩ feedback resistor. If users
attempt to measure the value of RFB, power must be applied to
VDD in order to achieve continuity. An additional VSS bias pin is
used to guard the substrate during high temperature applications, minimizing zero-scale leakage currents that double every
10°C. The DAC output voltage is determined by VREF and the
digital data (D) in the following equations:
VOUT = − VREF ×
D
(For AD5544 )
65536
(1)
VOUT = − VREF ×
D
(For AD5554 )
16384
(2)
Note that the output polarity is opposite to the VREF polarity for
dc reference voltages.
FFFFH
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
ZS
100
VDD
2R
2R
RFBX
R
S1
IOUTX
AGNDF
AGNDX
VSS
DGND
00943-0-025
FROM OTHER DACS AGND
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED.
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 26. AD5554 Reference Multiplying Bandwidth vs. Code
5kΩ
S2
1k
3FFFH
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 25. Typical Equivalent DAC Channel
These DACs are also designed to accommodate ac reference
input signals. Both the AD5544 and the AD5554 accommodate
input reference voltages in the range of −12 V to +12 V. The
reference voltage inputs exhibit a constant nominal input
Rev. A | Page 14 of 20
VDD = 5V
VREF = 100mV rm s
TA = 25°C
CF = 23pF
ZS
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 27. AD5554 Reference Multiplying Bandwidth vs. Code
00943-0-027
2R
R
GAIN (12dB/DIV)
R
R
VREFX
VDD = 5V
VREF = 100mV rm s
TA = 25°C
00943-0-026
D/A CONVERTER
resistance of 5 kΩ, ±30%. On the other hand, the DAC outputs
IOUTA, B, C, D are code-dependent and produce various output resistances and capacitances. The choice of external amplifier should take into account the variation in impedance
generated by the AD5544/AD5554 on the amplifiers’ inverting
input node. The feedback resistance, in parallel with the DAC
ladder resistance, dominates output voltage noise. For multiplying mode applications, an external feedback compensation
capacitor (CFB) may be needed to provide a critically damped
output response for step changes in reference input voltages.
Figure 26 and Figure 27 show the gain vs. frequency performance at various attenuation settings using a 23 pF external
feedback capacitor connected across the IOUTX and RFBX terminals for AD5544 and AD5554, respectively. In order to maintain good analog performance, power supply bypassing of
0.01 µF, in parallel with 1 µF, is recommended. Under these
conditions, a clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not
suitable for this application due to the higher ripple voltage and
PSS frequency-dependent characteristics. It is best to derive the
AD5544/AD5554’s 5 V supply from the system’s analog supply
voltages. Do not use the digital 5 V supply (see Figure 28).
GAIN (12dB/DIV)
The AD5544 and AD5554 contain four, 16-bit and 14-bit, current-output, digital-to-analog converters, respectively. Each
DAC has its own independent multiplying reference input. Both
the AD5544 and the AD5554 use a 3-wire, SPI compatible, serial
data interface, with a configurable asynchronous RS pin for
half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition,
an LDAC strobe enables four channel simultaneous updates for
hardware synchronized output voltage changes.
AD5544/AD5554
15V
2R
5V
+
ANALOG
POWER
SUPPLY
R
VDD
AD5544
RR
VREFX
2R
RFBX
R
2R
2R
R
5kΩ
15V
S2
S1
VCC
IOUTX
AGNDF
AGNDX
VOUT
A1
+
VEE
FROM OTHER DACS AGND
LOAD
DIGITAL INTERFACE CONNECTIONS OMITTED.
FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED,
VDD MUST BE POWERED.
Figure 28. Recommended Kelvin-Sensed Hookup
Rev. A | Page 15 of 20
00943-0-028
DGND
VSS
AD5554/AD5554
SERIAL DATA INTERFACE
the CS line low between the first, second, and third byte transfers will result in a successful serial register update. Similarly,
two right justified data bytes can be written to the AD5554.
Keeping the CS line low between the first and second byte
transfer will result in a successful serial register update.
The AD5544/AD5554 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. Serial data of AD5544 and AD5554 is
clocked into the serial input register in an 18-bit and 16-bit
data-word format respectively. MSB bits are loaded first. Table 6
defines the 18 data-word bits for AD5544.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new data to the target
DAC register, determined by the decoding of address Bits A1
and A0. For AD5544, Table 5, Table 7, Table 9, and Figure 4
define the characteristics of the software serial interface. For
AD5554, Table 6, Table 8, Table 9, and Figure 5 define the
characteristics of the software serial interface. Figure 29 and
Figure 30 show the equivalent logic interface for the key digital
control pins for the AD5544. AD5554 has a similar configuration, except it has 14 data bits. Two additional pins, RS and
MSB, provide hardware control over the preset function and
DAC register loading.
Table 7 defines the 16 data-word bits for AD5554. Data is placed
on the SDI pin, and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the interface timing specifications.
data can only be clocked in while the CS chip select pin is active
low. For AD5544, only the last 18 bits clocked into the serial
register will be interrogated when the CS pin returns to the
logic high state, extra data bits are ignored. For AD5554, only
the last 16 bits clocked into the serial register will be interrogated when the CS pin returns to the logic high state. Since
most microcontrollers output serial data in 8-bit bytes, three
right justified data bytes can be written to the AD5544. Keeping
VREFA B C D
CS
EN
AD5544
VDD
CLK
SDO
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
RFBA
16
INPUT
REGISTER R
DAC A
REGISTER R
DAC A
IOUTA
AGNDA
RFBB
INPUT
REGISTER R
DAC B
REGISTER R
DAC B
IOUTB
AGNDB
DAC A
B
C
D
2:4
DECODE
RFBC
INPUT
REGISTER R
DAC C
REGISTER R
DAC C
IOUTC
AGNDC
RFBD
INPUT
REGISTER R
DAC D
REGISTER R
SET
MSB
SET
MSB
DAC D
IOUTD
AGNDD
AGNDF
POWERON
RESET
DGND
MSB
LDAC
Figure 29. System Level Digital Interfacing
Rev. A | Page 16 of 20
RS
VSS
00943-0-029
SDI
AD5544/AD5554
If these functions are not needed, the RS pin can be tied to logic
high. The asynchronous input RS pin forces all input and DAC
registers to either the zero-code state (MSB = 0) or the halfscale state (MSB = 1).
TO INPUT REGISTER
AD5544/AD5554
A
B
C
D
VDD
C3
10µF
+
VDD
C1
0.1µF
AGNDX
EN
C4
10µF
SHIFT REGISTER
CLK
C2
0.1µF
VSS
19TH/17TH
CLOCK
SDO
VSS
00943-0-030
SDI
DGND
00943-0-033
ADDRESS
DECODER
CS
electrolytic capacitors should also be applied at VDD to minimize
any transient disturbance and filter any low frequency ripple
(see Figure 32). Users should not apply switching regulators for
VDD due to the power supply rejection ratio degradation over
frequency.
Figure 32. Power Supply Bypassing and Grounding Connection
Figure 30. AD5544/AD5554 Equivalent Logic Interface
Grounding
POWER ON RESET
When the VDD power supply is turned on, an internal reset
strobe forces all the input and DAC registers to the zero-code
state or half-scale state, depending on the MSB pin voltage. The
VDD power supply should have a smooth positive ramp without
drooping in order to have consistent results, especially in the
region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on
the power-on reset performance. The DAC register data will
stay at a zero or half-scale setting until a valid serial register
data load takes place.
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zeners
connected to ground (DGND) and VDD, as shown in Figure 31.
VDD
5kΩ
Figure 31. Equivalent ESD Production Circuits
Power Supply Sequence
As standard practice, it is recommended to power VDD, VSS, and
ground prior to any reference. The ideal power up sequence is
AGNDX, DGND, VDD, VSS, VREFX, and digital inputs. A noncompliance power up sequence may elevate the reference current, but
the devices resume normal operation once VDD and VSS are
powered-up.
APPLICATIONS
The AD5544/AD5554 are inherently 2-quadrant multiplying
D/A converters. That is, they can be easily set up for unipolar
output operation. The full-scale output polarity is the inverse of
the reference-input voltage.
In some applications it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an additional external amplifier (A2) configured as a summing amplifier (see Figure 33). In
this circuit the first and second amplifiers (A1 and A2) provide
a total gain of 2 which increases the output voltage span to 20 V.
Biasing the external amplifier with a 10 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The
transfer equation of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = −10 V) to midscale
(VOUT = 0 V) to full-scale (VOUT = 10 V).
D
(3)
VOUT ⎛⎜
− 1⎞⎟ × − VREF (For AD5544 )
⎝ 32768
⎠
D
(4)
VOUT ⎛⎜
− 1⎞⎟ × − VREF (For AD5554 )
⎝ 8192
⎠
10kΩ
10kΩ
10V
Layout and Power Supply Bypassing
It is good practice to employ a compact, minimum-lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disc or chip
ceramic capacitors. Low-ESR 1 µF to 10 µF tantalum or
5kΩ
VREF
A2
VOUT
AD588
–10V < VOUT < +10V
VDD
VREFX
ONE CHANNEL
RFBX
IOUTX
AD5544
VSS
AGNDF
A1
AGNDX
DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.
Figure 33. Four-Quadrant Multiplying Application Circuit
Rev. A | Page 17 of 20
00943-0-033
DGND
00943-0-031
DIGITAL
INPUTS
The DGND and AGNDX pins of the AD5544/AD5554 refer as
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 32).
AD5544/AD5554
OUTLINE DIMENSIONS
10.50
10.20
9.90
28
15
5.60
5.30
5.00
8.20
7.80
7.40
14
1
1.85
1.75
1.65
2.00 MAX
0.10
COPLANARITY
0.25
0.09
0.05
MIN
0.38
0.22
0.65
BSC
SEATING
PLANE
8°
4°
0°
0.95
0.75
0.55
COMPLIANT TO JEDEC STANDARDS MO-150AH
Figure 34. 28-Lead SSOP
(RS-28)
Dimensions Shown in Inches and (Millimeters)
ORDERING GUIDE
Model
AD5544ARS
AD5554BRS
AD5544EVAL
RES Bit
16
14
INL LSB
±4
±1
DNL LSB
±1.5
±1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Rev. A | Page 18 of 20
Package Description
SSOP-28
SSOP-28
Evaluation Board
Package Option
RS-28
RS-28
AD5544/AD5554
NOTES
Rev. A | Page 19 of 20
AD5544/AD5554
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00943-0-12/04(A)
Rev. A | Page 20 of 20
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