Maxim DS8005 Smart card intergace Datasheet

19-5257; Rev 0; 4/10
Smart Card Interface
Features
The DS8005 dual smart card interface is a low-cost,
dual analog front-end for an IC card reader interface
that needs to communicate with two smart cards in a
mutually exclusive fashion. The analog interface is
designed for use in ISO 7816, EMV®, and B-CAS applications. The device is functionally similar to two
DS8024s with external multiplexing to select the active
interface, but also includes low power and 1.8V card
support. Additionally, the device is designed for applications where the C4/C8 (AUX1/AUX2) contacts are not
required on either card interface.
♦ Analog Interface and Level Shifting for IC Card
Communication
The device is provided in a 28-pin SO package. The
pinout is backwards compatible with the DS8313,
allowing applications to use the same footprint and
PCB for applications that communicate with either one
or two smart cards.
The device is designed to be used with microcontrollers that contain an ISO 7816 UART, or have the
bandwidth to run this protocol in software by bit-banging IO ports. If the microcontroller does not have the
capability of running the ISO 7816 UART, the DS8007 is
the more appropriate product selection.
♦ Automatic Card Activation and Deactivation
Controlled by Dedicated Internal Sequencer
Applications
Set-Top Box Conditional Access
Telecommunications
♦ ±8kV (min) ESD (HBM) Protection on Card Interfaces
♦ Ultra-Low Stop-Mode Current, Less than 10nA
Typical
♦ Internal IC Card Supply-Voltage Generation
5.0V ±5%, 80mA (max)
3.0V ±8%, 65mA (max)
1.8V ±10%, 30mA (max)
♦ I/O Lines from Host Directly Level Shifted for
Smart Card Communication
♦ Flexible Card Clock Generation, Supporting
External Crystal Frequency Divided by 1, 2, 4, or 8
♦ High-Current, Short-Circuit and High-Temperature
Protection
♦ Low Active-Mode Current
♦ Internal Multiplexing Allows One ISO 7816 UART
Implementation to Control Two Smart Card
Sockets
Ordering Information
Pay Television
Access Control
Financial Terminals
PART
DS8005-RRX+
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
28 SO
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
PART
DS8005-RRX+
CARD VOLTAGES
SUPPORTED
LOW STOP-MODE
POWER
LOW ACTIVEMODE POWER
PRES_ POLARITY
VDDA INPUTS
1.8V, 3V, 5V
Yes
Yes
Positive
2
Typical Application Circuit appears at end of data sheet.
EMV is a registered trademark of EMVCo LLC.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS8005
General Description
DS8005
Smart Card Interface
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD Relative to GND ...............-0.5V to +6.5V
Voltage Range on VDDA Relative to GND .............-0.5V to +6.5V
Voltage Range on CLKA, RSTA, I/OA ......-0.5V to (VCCA + 0.5V)
Voltage Range on CLKB, RSTB, I/OB ......-0.5V to (VCCB + 0.5V)
Voltage Range on All Other Pins
Relative to GND.......................................-0.5V to (VDD + 0.5V)
Maximum Junction Temperature .....................................+125°C
Maximum Power Dissipation Range (TA = -25°C to +85°C)..700mW
Storage Temperature Range ............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in
the CONDITIONS column.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Digital Supply Voltage
VDD
2.7
6.0
V
Card Voltage-Generator Supply Voltage
VDDA
Must be VDD
4.75
6.0
V
VTH2
Threshold voltage (falling)
2.20
2.45
2.65
V
50
100
200
mV
80.75
85
mA
0.75
5
mA
65.75
70
mA
0.75
5
mA
30.75
40
mA
Reset Voltage Thresholds
VHYS2
Hysteresis
Active VDD Current 5V Cards
(Including 80mA Draw from 5V Card)
IDD_50V
ICC = 80mA, f XTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V
Active VDD Current 5V Cards (Current
Consumed by Device Only)
IDD_IC
ICC = 80mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2)
Active VDD Current 3V Cards
(Including 65mA Draw from 3V Card)
IDD_30V
ICC = 65mA, f XTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V
Active VDD Current 3V Cards (Current
Consumed by Device Only)
IDD_IC
ICC = 65mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2)
Active VDD Current 1.8V Cards
(Including 30mA Draw from 1.8V Card)
IDD_18V
ICC = 30mA, f XTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V
Active VDD Current 1.8V Cards (Current
Consumed by Device Only)
IDD_IC
ICC = 30mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2)
0.75
5
mA
IDD
Card inactive, active-high PRES_,
device not in stop mode
50
400
μA
IDD_STOP
Device in ultra-low-power stop
mode (CMDVCC, 5V/3V, and 1_8V
set to logic 1) (Note 3)
0.01
2
μA
CURRENT CONSUMPTION
Inactive-Mode Current
Stop-Mode Current
2
_______________________________________________________________________________________
Smart Card Interface
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in
the CONDITIONS column.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK SOURCE
Crystal Frequency
XTAL1 Operating Conditions
f XTAL
External crystal (Note 1)
0
20
MHz
f XTAL1
(Note 1)
0
20
MHz
Low-level input on XTAL1
-0.3
0.3 x
VDD
High-level input on XTAL1
0.7 x
VDD
VDD +
0.3
VIL_XTAL1
VIH_XTAL1
External Capacitance for Crystal
Internal Oscillator
CXTAL1,
CXTAL2
f INT
2.2
2.7
V
15
pF
3.4
MHz
SHUTDOWN TEMPERATURE
Shutdown Temperature
T SD
+150
°C
RSTA AND RSTB PINS
Card-Inactive Mode
Card-Active Mode
Output Low Voltage
VOL_RST1
I OL_RST = 1mA
0.3
V
Output Current
I OL_RST1
VOL_RST = 0V
-1
mA
Output Low Voltage
VOL_RST2
I OL_RST = 200μA
0.3
V
Output High
Voltage
VOH_RST2
I OH_RST = -200μA
VCC 0.5
V
Rise Time
tR_RST
CL = 30pF (Note 1)
0.1
Fall Time
tF_RST
CL = 30pF (Note 1)
0.1
μs
+20
mA
2
μs
0.3
V
Current Limitation
IRST(LIMIT)
RSTIN to RST Delay
tD(RSTIN-RST)
-20
μs
CLKA AND CLKB PINS
Card-Inactive Mode
Output Low Voltage
VOL_CLK1
I OLCLK = 1mA
Output Current
I OL_CLK1
VOLCLK = 0V
-1
mA
Output Low Voltage
VOL_CLK2
I OLCLK = 200μA
0.3
V
Output High
Voltage
Card-Active Mode
VOH_CLK2
I OHCLK = -200μA
VCC 0.5
V
Rise Time
tR_CLK
CL = 30pF (Notes 1, 4)
8
Fall Time
tF_CLK
CL = 30pF (Notes 1, 4)
8
ns
ns
-75
+75
mA
Current Limitation
ICLK(LIMIT)
Clock Frequency
fCLK
Operational
0
10
MHz
CL = 30pF
45
55
%
CL = 30pF (Note 1)
0.2
Duty Factor
Slew Rate
SR
V/ns
VCCA AND VCCB PINS
Card-Inactive Mode
Output Low Voltage
VCC1
ICC = 1mA
Output Current
ICC1
VCC = 0V
0
0.3
V
-1
mA
_______________________________________________________________________________________
3
DS8005
RECOMMENDED DC OPERATING CONDITIONS (continued)
DS8005
Smart Card Interface
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in
the CONDITIONS column.) (Note 1)
PARAMETER
Output Low Voltage
SYMBOL
VCC2
Card-Active Mode
CONDITIONS
MIN
TYP
MAX
Device: ICC(5V) < 30mA,
VDDA = 4.75V (Note 1)
4.65
5
5.25
Device: ICC(5V) < 80mA
4.75
5
5.25
Device: ICC(3V) < 65mA
2.78
3
3.24
Device: ICC(1.8V) < 30mA
1.64
1.8
1.98
5V card; current pulses of 40nC
with I < 200mA, t < 400ns,
f < 20MHz
4.6
5.4
3V card; current pulses of 24nC
with I < 200mA, t < 400ns,
f < 20MHz
2.75
3.25
1.8V card; current pulses of 12nC
with I < 200mA, t < 400ns,
f < 20MHz
1.62
1.98
VCC(5V) = 0 to 5V
Output Current
ICC2
-65
VCC(1.8V) = 0 to 1.8V
-30
ICC(SD)
(Note 1)
Slew Rate
VCCSR
Up/down; C < 300nF (Note 5)
V
-80
VCC(3V) = 0 to 3V
Shutdown Current
Threshold
UNITS
120
0.05
0.16
mA
mA
0.22
V/μs
DATA LINES (I/O_ AND I/OIN)
I/O_ I/OIN Falling Edge Delay
Pullup Pulse Active Time
Maximum Frequency
Input Capacitance
tD(IO-IOIN)
(Note 1)
200
ns
t PU
(Note 1)
100
ns
f IOMAX
1
MHz
CI
10
pF
I/OA AND I/OB PINS
Card-Inactive Mode
Output Low Voltage
VOL_IO1
I OL_IO = 1mA
Output Current
I OL_IO1
VOL_IO = 0V
0
Internal Pullup
Resistor
RPU_IO
To VCC
6
Output Low Voltage
VOL_IO2
I OL_IO = 1mA
Output High
Voltage
Card-Active Mode
4
Output Rise/Fall
Time
VOH_IO2
t OT
11
I OH_IO = < -20μA
0.8 x VCC
I OH_IO = < -40μA (3V/5V)
0.75 x VCC
CL = 30pF (Note 1)
0.3
V
-1
mA
19
k
0.3
V
V
0.1
Input Low Voltage
VIL_IO
-0.3
+0.8
Input High Voltage
VIH_IO
1.5
VCC
_______________________________________________________________________________________
μs
V
Smart Card Interface
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in
the CONDITIONS column.) (Note 1)
PARAMETER
Card-Active Mode
SYMBOL
CONDITIONS
Input Low Current
I IL_IO
VIL_IO = 0V
Input High Current
I IH_IO
VIH_IO = VCC
Input Rise/Fall Time
MIN
TYP
-20
t IT
UNITS
700
μA
+20
μA
1.2
μs
+15
mA
0.3
V
VDD +
0.1
V
0.1
μs
I IO(LIMIT)
CL = 30pF
Output Low Voltage
VOL
I OL = 1mA
Output High Voltage
VOH
I OH < -40μA
Output Rise/Fall Time
t OT
CL = 30pF, 10% to 90%
Input Low Voltage
VIL
-0.3
+0.3 x
VDD
V
Input High Voltage
VIH
0.7 x
VDD
VDD +
0.3
V
Input Low Current
I IL_IO
700
μA
Input High Current
I IH_IO
VIH = VDD
+10
μA
t IT
VIL to VIH
Current Limitation
-15
MAX
I/OIN PIN
Input Rise/Fall Time
Integrated Pullup Resistor
RPU
0.75 x
VDD
VIL = 0V
Pullup to VDD
-10
6
11
1.2
μs
19
k
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V, 1_8V)
Input Low Voltage
VIL
-0.3
+0.3 x
VDD
V
Input High Voltage
VIH
0.7 x
VDD
VDD +
0.3
V
Input Low Current
I IL_IO
0 < VIL < VDD
-5
+5
μA
Input High Current
I IH_IO
0 < VIH < VDD
-5
+5
μA
0.3
V
INTERRUPT OUTPUT PINS (OFF AND OFF2)
Output Low Voltage
VOL
I OL = 2mA
Output High Voltage
VOH
I OH = -15μA
0.75 x
VDD
Integrated Pullup Resistor
RPU
Pullup to VDD
12
V
24
38
k
0.3 x
VDD
V
PRESA AND PRESB PINS
Input Low Voltage
VIL_PRES
Input High Voltage
VIH_PRES
0.7 x
VDD
Input Low Current
I IL_PRES
VIL_PRES = 0V
Input High Current
I IH_PRES
VIH_PRES = VDD
-5
V
+5
μA
10
μA
_______________________________________________________________________________________
5
DS8005
RECOMMENDED DC OPERATING CONDITIONS (continued)
DS8005
Smart Card Interface
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in
the CONDITIONS column.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
50
160
220
μs
μs
TIMING
Activation Time
tACT
Deactivation Time
CLK_ to Card Start
Time
PRES Debounce Time
tDEACT
50
80
100
Window Start
t3
50
95
130
Window End
t5
140
160
220
tDEBOUNCE
5
8
11
μs
ms
Operation guaranteed at -40°C and +85°C but not tested.
IDD_IC measures the amount of current used by the device to provide the smart card current minus the load.
Stop mode is enabled by setting CMDVCC, 5V/3V, and 1_8V to a logic-high.
Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maximum
rise and fall time is 10ns.
Note 5: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimum
slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.
Note 1:
Note 2:
Note 3:
Note 4:
6
_______________________________________________________________________________________
Smart Card Interface
TOP VIEW
CLKDIV1 1
28 SEL_AB
CLKDIV2 2
27 OFF2
5V/3V 3
26 I/OIN
1_8V 4
25 XTAL2
VCCB 5
VDDA 6
DS8005
RSTB 7
24 XTAL1
23 OFF
22 GND
CLKB 8
21 VDD
CGND 9
20 RSTIN
PRESA 10
19 CMDVCC
I/OA 11
18 VDDA2
I/OB 12
17 VCCA
PRESB 13
16 RSTA
CGND 14
15 CLKA
SO
Pin Description
PIN
NAME
FUNCTION
1, 2
CLKDIV1,
CLKDIV2
3
5V/3V
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high
selects 5V operation; logic-low selects 3V operation. The 1_8V pin overrides the setting on this pin if
active. See Table 3 for a complete description of choosing card voltages.
4
1_8V
1.8V Operation Selection. This active-high input puts the device into 1.8V smart card communication
mode. The selected interface (when activated) powers a card with a 1.8V supply and all I/O lines
operate at 1.8V.
5
VCCB
Smart Card Supply Voltage, Interface B. Decouple to CGND (card ground) with 2 x 100nF or 100 +
200nF capacitors (ESR < 100m).
6
VDDA
Smart Card Interface Supply. 5V power supply for powering the card interface.
7
RSTB
Smart Card Reset, Interface B. Card reset output from contact C2.
Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
crystal at XTAL1 and XTAL2) on the CLK_ output pin. Dividers of 1, 2, 4, and 8 are available.
8
CLKB
Smart Card Clock, Interface B. Card clock, contact C3.
9, 14
CGND
Smart Card Ground
10
PRESA
Interface A Card Presence Indicator. Active-high card presence input for the first card interface.
When the presence indicator becomes active, a debounce timeout begins. After 8ms (typ), the OFF
signal becomes active if the first card interface is selected (SEL_AB low), else the OFF2 signal
becomes active.
11
I/OA
Smart Card Data-Line Output, Interface A. Card data communication line, contact C7. This pin is
only active if the first card interface is selected (SEL_AB low) and the interface has gone through an
activation sequence.
_______________________________________________________________________________________
7
DS8005
Pin Configuration
Smart Card Interface
DS8005
Pin Description (continued)
PIN
12
I/OB
FUNCTION
Smart Card Data-Line Output, Interface B. Card data communication line, contact C7. This pin is
only active if the second card interface is selected (SEL_AB high) and the interface has gone
through an activation sequence.
13
PRESB
Interface B Card Presence Indicator. Active-high card presence input for the second card interface.
When the presence indicator becomes active, a debounce timeout begins. After 8ms (typ), the OFF
signal becomes active if the second card interface is selected (SEL_AB high), else the OFF2 signal
becomes active.
15
CLKA
Smart Card Clock, Interface A. Card clock, contact C3.
16
RSTA
Smart Card Reset, Interface A. Card reset output from contact C2.
17
VCCA
Smart Card Supply Voltage, Interface A. Decouple to CGND (card ground) with 2 x 100nF or 100 +
220nF capacitors (ESR < 100m).
18
VDDA2
Smart Card Interface Supply. 5V power supply for powering the card interface. While this pin is not
required to be connected to 5V (it can be left not connected (N.C.)), it is recommended for the best
performance when delivering power to a 5V smart card.
19
CMDVCC
20
RSTIN
Activation Sequence Initiate. Active-low input from host.
Card Reset Input. Reset input from the host.
21
VDD
Supply Voltage
22
GND
Digital Ground
23
OFF
Status Output for Selected Interface. Active-low interrupt output to the host. Includes a 20k
integrated pullup resistor to VDD. This pin reflects fault events and PRES_ events on the currently
selected interface only (behaving as if it were a DS8024 with only one interface). The OFF2 pin
should be used to monitor presence events on the nonselected interface.
24, 25
XTAL1,
XTAL2
26
I/OIN
I/O Input. Host-to-interface chip data I/O line.
OFF2
Status Output for Nonselected Interface. This pin passes through the presence signal for the
nonselected interface. If SEL_AB is low (the A interface is selected), this pin reflects the state of the
PRESB input. If SEL_AB is high (the B interface is selected), this pin reflects the state of the PRESA
input.
SEL_AB
Interface Selection. This pin selects the interface the input pins (I/OIN, RSTIN, etc.) communicate
with and control. If SEL_AB is low, the A interface is selected. Activation sequences power up VCCA
and communication occurs with CLKA, I/OA, and RSTA. If SEL_AB is high, the B interface is
selected. Both interfaces can be powered and clocking at the same time. See the Switching A/B
Interfaces section for more information.
27
28
8
NAME
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2.
_______________________________________________________________________________________
Smart Card Interface
REGULATOR
CLKDIV1
CLKDIV2
XTAL1
XTAL2
CLOCK
GENERATION
RSTIN
I/OIN
SEL_AB
CMDVCC
CARD
INTERFACE A
CARD
INTERFACE B
I/O
XCVR
CONTROL
SEQUENCER
DS8005
1_8V
5V/3V
VDDA
VDDA2
CGND
I/OA
VCCA
RSTA
CLKA
PRESA
I/OB
VCCB
RSTB
CLKB
PRESB
QSEL_AB
QSEL_AB
DS8005
OFF
OFF2
INTERRUPT
GENERATION
FAULT
DETECTION
POWER
SUPPLY
VDD
GND
Figure 1. Functional Diagram
Detailed Description
The DS8005 is an analog front-end for communicating
with 1.8V, 3V, and 5V dual smart cards. It is a dual
input-voltage device, requiring one supply to match
that of a host microcontroller and a separate +5V supply for generating correct smart card supply voltages.
The device translates all communication lines to the
correct voltage level and provides power for smart card
operation. It is a low-power device, consuming very little current in active-mode operation (during a smart
card communication session), and is suitable for use in
battery-powered devices such as laptops and PDAs,
consuming only 10nA in stop mode. The device is
designed for applications that do not require communication using the C4 and C8 card contacts (AUX1 and
AUX2). It is suitable for SIM/SAM interfacing, as well as
for applications where only the I/O line is used to communicate with a smart card.
Power Supply
The device has dual supplies. The supply pins for the
device are VDD, GND, and VDDA. VDD should be in the
2.7V to 6.0V range, and is the supply for signals that
interface with the host controller. It should, therefore, be
the same supply as used by the host controller. All
smart card contacts remain inactive during power-on or
power-off. The internal circuits are kept in the reset
state until VDD reaches VTH2 + VHYS2 and for the duration of the internal power-on reset pulse, tW. A deactivation sequence is executed when V DD falls below
VTH2.
An internal regulator generates the 1.8V, 3V, or 5V card
supply voltage (VCC_). The regulator should be supplied separately by VDDA. VDDA should be connected
to a minimum 4.75V supply to provide the correct supply voltage for 5V smart cards.
_______________________________________________________________________________________
9
DS8005
Smart Card Interface
Voltage Supervisor
The voltage supervisor monitors the V DD supply. A
220µs reset pulse (tW) is used internally to keep the
device inactive during power-on or power-off of the
VDD supply. See Figure 2.
The IC card interface remains inactive regardless of the
levels on the command lines until duration tW after VDD
has reached a level higher than VTH2 + VHYS2. When
V DD falls below V TH2 , the device executes a card
deactivation sequence if the card interface is active.
Clock Circuitry
The card clock signal (CLKA/CLKB) is derived from a
clock signal input to XTAL1 or from a crystal operating
at up to 20MHz connected between XTAL1 and XTAL2.
The output clock frequency of CLK_ is selectable
through inputs CLKDIV1 and CLKDIV2. The CLK signal
frequency can be fXTAL, fXTAL/2, fXTAL/4, or fXTAL/8.
See Table 1 for the frequency generated on the CLK_
signal given the inputs to CLKDIV1 and CLKDIV2.
Note that CLKDIV1 and CLKDIV2 must not be changed
simultaneously; a delay of 10ns minimum between
changes is needed. The minimum duration of any state
of CLK_ is eight periods of XTAL1.
Table 1. Clock Frequency Selection
CLKDIV1
CLKDIV2
fCLK
0
0
f XTAL/8
0
1
f XTAL/4
1
1
f XTAL/2
1
0
f XTAL
The frequency change is synchronous: during a transition of the clock divider, no pulse is shorter than 45% of
the smallest period, and the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change
is effective for only eight periods of XTAL1 after the
command.
The fXTAL duty factor depends on the input signal on
XTAL1. To reach a 45% to 55% duty factor on CLK_,
XTAL1 should have a 48% to 52% duty factor with transition times less than 5% of the period.
With a crystal, the duty factor on CLK_ can be 45% to
55% depending on the circuit layout and on the crystal
characteristics and frequency. In other cases, the duty
factor on CLK_ is guaranteed between 45% and 55% of
the clock period.
I/O Transceivers
I/O_ and I/OIN are pulled high with an 11kΩ resistor
(I/O_ to VCC_ and I/OIN to VDD) in the inactive state.
The first side of the transceiver to receive a falling edge
becomes the master. When a falling edge is detected
(and the master is decided), the detection of falling
edges on the line of the other side is disabled; that side
then becomes a slave. After a time delay tD(EDGE), an n
transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay tPU
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high transitions. After the duration of tPU, the output voltage
depends only on the internal pullup resistor and the
VTH2 + VHYS2
VTH2
VDD
ALARM
(INTERNAL SIGNAL)
tW
tW
POWER ON
SUPPLY DROPOUT
Figure 2. Voltage Supervisor Behavior
10
______________________________________________________________________________________
POWER OFF
Smart Card Interface
Inactive Mode
The device powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
• All card contacts are inactive (approximately 200Ω to
GND).
If the card is in the reader (if PRES_ is active), the host
microcontroller can begin an activation sequence (start
a card session) by pulling CMDVCC low. The following
events form an activation sequence (Figure 3):
1) CMDVCC is pulled low.
2) The internal oscillator changes to high frequency (t0).
3) The voltage generator is started (between t0 and t1).
Table 2. Card Presence Indication
SEL_AB
OFF
CMDVCC
Low
High
High
Low
Low
High
Card A not present.
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
High
High
High
Card B present.
High
Low
High
Card B not present.
• The internal oscillator is running at its low frequency.
SEL_AB
OFF2
CMDVCC
Low
High
High
Low
Low
High
Card B not present.
High
High
High
Card A present.
High
Low
High
Card A not present.
• The I/OIN pin in the high-impedance state (11kΩ
pullup resistor to VDD).
• Voltage generators are stopped.
Activation Sequence
After power-on and the reset delay, the host microcontroller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
STATUS
Card A present.
STATUS
Card B present.
CMDVCC
VCC_
ATR
I/O_
CLK_
RSTIN
RST_
I/OIN
t0 t1
t2
t3
t4
t5 = tACT
Figure 3. Activation Sequence Using RSTIN and CMDVCC
______________________________________________________________________________________
11
DS8005
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
DS8005
Smart Card Interface
4) VCC_ rises from 0 to 5V, 3V, or 1.8V with a controlled
slope (t2 = t1 + 1.5 × T). T is 64 times the internal
oscillator period (approximately 25µs).
5) I/O_ pin is enabled (t3 = t1 + 4T) (they were previously pulled low).
6) The CLK_ signal is applied to the C3 contact (t4).
7) RST_ is enabled (t5 = t1 + 7T).
To apply the clock to the card interface:
1) Set RSTIN high.
2) Set CMDVCC low.
3) Set RSTIN low between t3 and t5; CLK_ now starts.
4) RST_ stays low until t5, then RST becomes the copy
of RSTIN.
5) RSTIN has no further effect on CLK_ after t5.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK_ starts at t3 (minimum
200ns after the transition on I/O; see Figure 4); after t5,
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform activation with RSTIN held permanently high.
Active Mode
When the activation sequence is completed, the card
interface is in active mode. The host microcontroller
and the smart card exchange data on the I/O lines.
Deactivation Sequence
When a session is completed, the host microcontroller
sets the CMDVCC line high to execute an automatic
deactivation sequence and returns the card interface to
the inactive mode (Figure 5).
1) RST_ goes low (t10).
2) CLK_ is held low (t12 = t10 + 0.5 × T) where T is 64
times the period of the internal oscillator (approximately 25µs).
3) I/O_ pin is pulled low (t13 = t10 + T).
4) VCC starts to fall (t14 = t10 + 1.5 × T).
5) When VCC_ reaches its inactive state, the deactivation sequence is complete (at tDE).
6) All card contacts become low impedance to GND;
I/OIN remains at VDD (pulled up through an 11kΩ
resistor).
7) The internal oscillator returns to its lower frequency.
VCC Generator
Each VCC_ generator has a capacity to supply up to
80mA continuously at 5V, 65mA at 3V, and 30mA at
12
1.8V. An internal overload detector triggers at approximately 120mA. Current samples to the detector are filtered. This allows spurious current pulses (with a
duration of a few µs) up to 200mA to be drawn without
causing deactivation. The average current must stay
below the specified maximum current value. To maintain VCC voltage accuracy, a 100nF capacitor (with an
ESR < 100mΩ) should be connected to CGND and
placed near the V CC_ pin, and a 100nF or 220nF
capacitor (220nF is the best choice) with the same ESR
should be connected to CGND and placed near the
smart card reader’s C1 contact.
Fault Detection
The following fault conditions are monitored:
• Short-circuit or high current on VCC_
• Removal of a card during a transaction
• VDD dropping
• Card voltage generator operating out of the specified
values (V DDA too low or current consumption too
high)
• Overheating
There are two different cases (Figure 6):
• CMDVCC High Outside a Card Session. Output
OFF_ is low if a card is not in the card reader and
high if a card is in the reader. The VDD supply is monitored—a decrease in input voltage generates an
internal power-on reset pulse but does not affect the
OFF_ signal. Short-circuit and temperature detection
is disabled because the card is not powered up.
• CMDVCC Low Within a Card Session. Output OFF_
goes low when a fault condition is detected, and an
emergency deactivation is performed automatically
(Figure 7). When the system controller resets CMDVCC to high, it may sense the OFF_ level again after
completing the deactivation sequence. This distinguishes between a card extraction and a hardware
problem (OFF_ goes high again if a card is present).
Depending on the connector’s card-present switch
(normally closed or normally open) and the mechanical characteristics of the switch, bouncing can occur
on the PRES_ signals at card insertion or withdrawal.
The device has a debounce feature with an 8ms typical
duration (Figure 6). When a card is inserted, output
OFF_ goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES_ and output OFF_ goes low.
______________________________________________________________________________________
Smart Card Interface
DS8005
CMDVCC
VCC_
ATR
I/O_
CLK_
200ns
RSTIN
RST_
I/OIN
t0 t1
t2
t3 t4
t5 = tACT
Figure 4. Activation Sequence at t3
CMDVCC
RST_
CLK_
I/O_
VCC_
t10
t12
t13
t14
t15
tDE
Figure 5. Deactivation Sequence
______________________________________________________________________________________
13
DS8005
Smart Card Interface
PRES_
OFF_
CMDVCC
DEBOUNCE
DEBOUNCE
VCC_
DEACTIVATION CAUSED
BY CARD WITHDRAWAL
DEACTIVATION CAUSED
BY SHORT CIRCUIT
Figure 6. Behavior of PRES_, OFF_, CMDVCC, and VCC_
OFF_
PRES_
RST_
CLK_
I/O_
VCC_
t10
t12
t13
t14
t15
tDE
Figure 7. Emergency Deactivation Sequence (Card Extraction)
14
______________________________________________________________________________________
Smart Card Interface
A low-power state, stop mode, can be entered by forcing the CMDVCC, 5V/3V, and 1_8V input pins to a
logic-high state. Stop mode can only be entered when
the smart card interface is inactive. In stop mode, all
internal analog circuits are disabled. The OFF_ pin follows the status of the PRES_ pin. To exit stop mode,
change the state of one or more of the three control
pins to a logic-low. An internal 220µs (typ) power-up
delay and the 8ms PRES_ debounce delay are in effect
and OFF_ is asserted to allow the internal circuitry to
stabilize. This prevents smart card access from occurring after leaving stop mode. Figure 8 shows the control
sequence for entering and exiting stop mode. Note that
an in-progress deactivation sequence always finishes
before the device enters low-power stop mode.
DEACTIVATE INTERFACE
CMDVCC
1_8V
ACTIVATE
STOP MODE
DEACTIVATE
STOP MODE
5V/3V
220μs DELAY
8ms DEBOUNCE
STOP MODE
OFF_ ASSERTED TO
WAIT FOR DELAY
OFF_
OFF_ FOLLOWS
PRES IN STOP MODE
PRES_
VCC_
Figure 8. Stop-Mode Sequence
______________________________________________________________________________________
15
DS8005
Stop Mode (Low-Power Mode)
DS8005
Smart Card Interface
Smart Card Power Select
logic-low state. Care must be exercised when switching
from one VCC power selection to the other. If both 1_8V
and 5V/3V are high with CMDVCC high at the same
time, the device enters stop mode. To avoid accidental
entry into stop mode, the state of 1_8V and 5V/3V must
not be changed simultaneously. A minimum delay of
100ns should be observed between changing the
states of 1_8V and 5V/3V. See Figure 9 for the recommended sequence of changing the VCC range.
The device supports three smart card VCC voltages:
1.8V, 3V, and 5V. The power select is controlled by the
1_8V and 5V/3V signals as shown in Table 3. The 1_8V
signal has priority over 5V/3V. When 1_8V is asserted
high, 1.8V is applied to VCC when the smart card is
active. When 1_8V is deasserted, 5V/3V dictates VCC
power range. VCC is 5V if 5V/3V is asserted to a logichigh state, and V CC is 3V if 5V/3V is pulled to a
Table 3. VCC Select and Operation Mode
1_8V
5V/3V
CMDVCC
VCC SELECT (V)
0
0
0
3
Activated
0
0
1
3
Inactivated
0
1
0
5
Activated
0
1
1
5
Inactivated
1
0
0
1.8
Activated
1
0
1
1.8
Inactivated
1
1
0
1.8
Reserved (Activated)
1
1
1
1.8
Not Applicable—Stop Mode
VCC SELECT
1.8V
3V
5V
CARD INTERFACE STATUS
3V
1.8V
STOP MODE
CMDVCC
1_8V
5V/3V
Figure 9. Smart Card Power Select
16
______________________________________________________________________________________
Smart Card Interface
One of the device’s key features is the ability to manage two card slots at the same time. The multiplexing
control signal SEL_AB is used to determine which interface is active for communication, though it is possible
to leave both interfaces powered at the same time.
When switching between interfaces, the device preserves the state of control signals CLKDIV1, CLKDIV2,
1.8V, 5V/3V, CMDVCC, and RSTIN by latching the pin
states. This allows the now inactive interface to stay
powered while the other interface is activated for communication, and it also allows for fast switching
between card interfaces without the need for a card
deactivation and activation sequence. After switching
SEL_AB, the control signals CLKDIV1, CLKDIV2, 1.8V,
5V/3V, CMDVCC, and RSTIN must not be changed for
78µs while the device latches the state of the pins for
the inactive interface. After the control signals are
latched, a 42µs window is provided to change the control
inputs.
Note that the behavior of the OFF and OFF2 pins is
dependent on the SEL_AB pin. OFF always refers to
the active interface, and OFF2 always reports events
on the inactive interface. This allows the device to
monitor for card insertion and removal on both interfaces simultaneously. See Figure 10 for details on the
behavior of the SEL_AB, OFF, and OFF2 pins with
regard to card presence.
TRANSPARENT
LATCH A
1_8V, 5V/3V, CLKDIV1,
CLKDIV2, RST, I/O
REG A
VCCA
CLKA DIV
CLKA
RSTA, I/OA, GNDA
ENA
SEL_AB
TRANSITION
SENSOR
TRANSPARENT
LATCH B
REG B
VCCB
CLKB DIV
CLKB
RSTB, I/OB, GNDB
DELAY
ENA
1
SMART CARD
STATUS 1
PRESA
0
SMART CARD
STATUS 2
PRESB
OFF
1
OFF2
0
DS8005
Figure 10. Switching A/B Interfaces
______________________________________________________________________________________
17
DS8005
Switching A/B Interfaces
DS8005
Smart Card Interface
Applications Information
Performance can be affected by the layout of the application. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST_) and C3
(CLK_) or C2 (RST_) and C7 (I/O_) can cause contact
C2 to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
Application recommendations include the following:
• Ensure there is ample ground area around the device
and the connector; place the device very near to the
connector; decouple the VDD and VDDA lines separately. These lines are best positioned under the connector.
• The device and the host microcontroller must use the
same VDD supply. Pins CLKDIV1, CLKDIV2, RSTIN,
PRES_, I/OIN, 5V/3V, 1_8V, CMDVCC, and OFF are
referenced to VDD; if pin XTAL1 is to be driven by an
external clock, also reference this pin to VDD.
18
• Trace C3 (CLK) should be placed as far as possible
from the other traces.
• The trace connecting CGND to C5 (GND) should be
straight (the two capacitors on C1 (VCC_) should be
connected to this ground trace).
• Avoid ground loops between CGND and GND.
• Decouple VDDA and VDD separately. If two supplies
are the same in the application, they should be connected in a star on the main trace
With all these layout precautions, noise should be kept to
an acceptable level and jitter on C3 (CLK_) should be
less than 100ps. Reference layouts are available on
request.
Technical Support
For technical support, go to https://support.maximic.com/micro.
______________________________________________________________________________________
Smart Card Interface
VDD
100nF
33pF
33pF
+3.3V
100nF
+3.3V
10μF
XTAL1
XTAL2
GND
VDD VDDA2
100kΩ
VDDA
PRES
VCCA
MAXQ1103
GPIO
CLKDIV1
CLKDIV2
...
RSTA
5V/3V
INTERFACE A
1_8V
...
GPIO
ISO_DATA
CLKA
100nF*
220nF*
100nF*
220nF*
I/OA
RSTIN
PRESA
CMDVCC
CGND
I/OIN
VCCB
GPIO
SEL_AB
INTERFACE B
GPIO
GPIO
RSTB
CLKB
OFF
I/OB
OFF2
PRESB
PRESB
DS8005
100kΩ
+3.3V
*PLACE A 100nF CAPACITOR CLOSE TO THE DS8005 AND PLACE A 220nF CAPACITOR CLOSE TO CARD CONTACT.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 SO
W28+1
21-0042
______________________________________________________________________________________
19
DS8005
Typical Application Circuit
DS8005
Smart Card Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
4/10
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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