Cypress CY2300SI Phase-aligned clock multiplier Datasheet

CY2300
Phase-Aligned Clock Multiplier
Features
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Benefits
4-multiplier configuration
Single phase-locked loop architecture
Phase Alignment
Low jitter, high accuracy outputs
Output enable pin
3.3V operation
5V Tolerant input
Internal loop filter
8-pin 150-mil SOIC package
Commercial and Industrial Temperature available
• 1/2x, 1x, 1x, 2x Ref
• 10 MHz to 166.67 MHz operating range (reference input
from 20 MHz to 83.33 MHz)
• All outputs will have a consistent phase relationship
with each other and the reference input
• Meets critical timing requirements
• Enables design flexibility and lower power
consumption
• Supports industry standard design platforms
• Allows flexibility on Reference input
• Alleviates the need for external components
• Industry standard packaging saves on board space
• Suitable for wide spectrum of applications
Selector Guide
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY2300SC
4
20 MHz–83.33 MHz
10 MHz–166.67 MHz
Commercial Temperature
CY2300SI
4
20 MHz–83.33 MHz
10 MHz–166.6 7MHz
Industrial Temperature
Block Diagram
Pin Configuration
FBK
8-pin SOIC
Top View
1/2xREF
GND
REFIN
REF
1/2xREF
REFIN
/2
PLL
REF
Divider
Logic
1
2
3
4
8
7
6
5
OE
VDD
2xREF
REF
REF
2xREF
OE
Cypress Semiconductor Corporation
Document #: 38-07252 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised July 26, 2004
CY2300
Pin Definitions
Signal[1]
Pin
Description
1
1/2xREF
Clock output, 1/2x Reference
2
GND
Ground
3
REFIN
Input Reference frequency, 5V tolerant input
4
REF
Clock output Reference
5
REF
Clock output Reference
6
2xREF
Clock output, 2x Reference
7
VDD
3.3V Supply
8
OE
Output Enable (weak pull-up)
Functional Description
The CY2300 is available in commercial and industrial temperature ranges.
The CY2300 is a 4-output 3.3V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
Maximum Ratings
The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN
output frequencies on respective output pins.
DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V
The part has an on-chip PLL which locks to an input clock
presented on the REFIN pin. The input-to-output skew is guaranteed to be less than ±200 ps, and output-to-output skew is
guaranteed to be less than 200 ps.
Multiple CY2300 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Input Voltage REF ........................................... –0.5 to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature.................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions for CY2300SC Commercial Temperature Devices
Parameter
Description
Min.
Max.
Unit
3.0
3.6
V
0
70
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, Fout < 133.33 MHz
18
pF
Load Capacitance,133.33 MHz < Fout < 166.67 MHz
12
pF
CIN
Input Capacitance
7
pF
tPU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
50
ms
Max.
Unit
0.8
V
100
µA
0.05
Electrical Characteristics for CY2300SC Commercial Temperature Devices
Parameter
Description
Min.
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
50
µA
VOL
Output LOW Voltage[2]
IOL = 8 mA
0.4
V
VOH
[2]
Output HIGH Voltage
IOH = –8 mA
IDD
Supply Current
Unloaded outputs, REFIN = 66 MHz
45
mA
Unloaded outputs, REFIN = 33 MHz
32
mA
Unloaded outputs, REFIN = 20 MHz
18
mA
2.0
V
2.4
V
Notes:
1. Weak pull-down on all outputs.
2. Parameter is guaranteed by design and characterization. It is not 100% tested in production.
Document #: 38-07252 Rev. *B
Page 2 of 7
CY2300
Switching Characteristics for CY2300SC Commercial Temperature Devices
Parameter
1/t1
Name
Test Conditions
Output Frequency
Min.
18-pF load
Typ.
10
12-pF load
[3]
= t2 ÷ t1
40
50
Unit
133.33
MHz
166.67
MHz
60
%
t3
Rise Time[3]
Measured between 0.8V and 2.0V
1.20
ns
t4
Fall Time[3]
Measured between 0.8V and 2.0V
1.20
ns
t5
Output to Output Skew on rising
edges[3]
All outputs equally loaded
Measured at VDD/2
200
ps
t6
Delay, REFIN Rising Edge to Out- Measured at VDD/2 from REFIN to any
put Rising Edge[3]
output
±200
ps
t7
Device to Device Skew[3]
Measured at VDD/2 on the 1/2xREF pin of
devices (pin 1)
400
ps
tJ
Period Jitter[3]
Measured at Fout=133.33 MHz, loaded
outputs, 18-pF load
±175
ps
tLOCK
PLL Lock Time[3]
Stable power supply, valid clocks presented on REFIN
1.0
ms
Duty Cycle
Measured at VDD/2
Max.
Operating Conditions for CY2300SI Industrial Temperature Devices
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
–40
85
°C
CL
Load Capacitance, Fout < 133.33 MHz
15
pF
Load Capacitance,133.33 MHz < Fout < 166.67MHz
10
pF
CIN
Input Capacitance
tPU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
7
pF
50
ms
Max.
Unit
0.8
V
Electrical Characteristics for CY2300SI Industrial Temperature Devices
Parameter
Description
Test Conditions
Min.
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
100
µA
IIH
Input HIGH Current
VIN = VDD
50
µA
VOL
Output LOW Voltage[2]
IOL = 8 mA
0.4
V
VOH
Output HIGH
Voltage[2]
IDD
Supply Current
2.0
IOH = –8 mA
V
2.4
V
Unloaded outputs, REFIN = 66 MHz
48
mA
Unloaded outputs, REFIN = 33 MHz
35
mA
Unloaded outputs, REFIN = 20 MHz
20
mA
Note:
3. All parameters are specified with equally loaded outputs.
Document #: 38-07252 Rev. *B
Page 3 of 7
CY2300
Switching Characteristics for CY2300SI Industrial Temperature Devices
Parameter
Name
Test Conditions
Output Frequency
1/t1
Max.
Unit
133.33
MHz
166.67
MHz
60
%
Measured between 0.8V and 2.0V
1.20
ns
Measured between 0.8V and 2.0V
15-pF load
Min.
Typ.
10
10-pF load
[3]
Duty Cycle
Rise Time
t3
= t2 ÷ t1
Measured at VDD/2
[3]
[3]
40
50
t4
Fall Time
1.20
ns
t5
Output to Output Skew on ris- All outputs equally loaded
ing edges[3]
Measured at VDD/2
200
ps
t6
Delay, REFIN Rising Edge to
Output Rising Edge[3]
Measured at VDD/2 from REFIN to any
output
±200
ps
t7
Device to Device Skew[3]
Measured at VDD/2 on the 1/2xREF pin of
devices (pin 1)
400
ps
tJ
Period Jitter[3]
Measured at Fout=133.33 MHz, loaded
outputs, 15-pF load
±175
ps
tLOCK
PLL Lock Time[3]
Stable power supply, valid clocks presented on REFIN
1.0
ms
Switching Waveforms
Duty Cycle Timing
t1
t2
VDD/2
All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
t3
3.3V
0V
t4
Output-Output Skew
OUTPUT
VDD/2
VDD/2
OUTPUT
t5
Document #: 38-07252 Rev. *B
Page 4 of 7
CY2300
Switching Waveforms
Input-Output Propagation Delay
REFIN
VDD/2
VDD/2
OUTPUT
t6
Device-Device Skew
1/2xREF, Device1
VDD/2
VDD/2
1/2xREF, Device2
t7
Test Circuits
Test Circuit # 1
VDD
0.1 µF
OUTPUTS
CLK OUT
C LOAD
GND
Document #: 38-07252 Rev. *B
Page 5 of 7
CY2300
Ordering Information
Ordering Code
Package Type
Operating Range
CY2300SC
8-pin 150-mil SOIC
Commercial
CY2300SC
8-pin 150-mil SOIC - Tape and Reel
Commercial
CY2300SI
8-pin 150-mil SOIC
Industrial
CY2300SI
8-pin 150-mil SOIC - Tape and Reel
Industrial
CY2300SXC
8-pin 150-mil SOIC
Commercial
CY2300SXCT
8-pin 150-mil SOIC - Tape and Reel
Commercial
CY2300SXI
8-pin 150-mil SOIC
Industrial
CY2300SXIT
8-pin 150-mil SOIC - Tape and Reel
Industrial
Lead Free
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
8 Lead (150 Mil) SOIC - S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 38-07252 Rev. *B
Page 6 of 7
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2300
Document Title: CY2300 Phase-Aligned Clock Multiplier
Document Number: 38-07252
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110517
01/07/02
SZV
Change from Spec number: 38-01039 to 38-07252
*A
121854
12/14/02
RBI
Power up requirements added to Operating Conditions Information
*B
246829
See ECN
RGL
Added Lead Free Devices
Document #: 38-07252 Rev. *B
Page 7 of 7
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