Cypress CY7C1021CV33-10VI 64k x 16 static ram Datasheet

CY7C1021CV33
64K x 16 Static RAM
Features
• Pin- and function-compatible with CY7C1021BV33
• High speed
— tAA = 8, 10, 12, and 15 ns
• CMOS for optimum speed/power
• Low active power
— 360 mW (max.)
• Data retention at 2.0V
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA
Functional Description
The CY7C1021CV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021CV33 is available in standard 44-pin TSOP
Type II 400-mil-wide SOJ packages, as well as a 48-ball
FBGA.
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
Top View
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
64K x 16
RAM Array
512 X 2048
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
I/O1–I/O8
I/O9–I/O16
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CY7C1021CV33-8
8
CY7C1021CV33-10
10
CY7C1021CV33-12
12
CY7C1021CV33-15
15
Unit
ns
95
90
85
80
mA
5
5
5
5
mA
Cypress Semiconductor Corporation
Document #: 38-05132 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised October 30, 2002
CY7C1021CV33
Pin Configuration
48-ball FBGA
Document #: 38-05132 Rev. *C
(Top View)
4
3
1
2
BLE
OE
A0
I/O8
BHE
I/O9
5
6
A1
A2
NC
A
A3
A4
CE
I/O0
B
I/O10
A5
A6
I/O2
I/O1
C
VSS
I/O11
NC
A7
I/O3
VCC
D
VCC
I/O12
NC
NC
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Page 2 of 12
CY7C1021CV33
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[1] ......................................–0.5V to VCC+0.5V
DC Input
Voltage[1]
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
3.3V ± 10%
–40°C to +85°C
3.3V ± 10%
Commercial
Industrial
...................................–0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test
Conditions
1021CV33-8
1021CV33-10
1021CV33-12
1021CV33-15
Min.
Min.
Min.
Min.
Max.
Max.
Max.
VOH
Output HIGH
Voltage
VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW
Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
VIL
Input LOW
Voltage[1]
–0.3
0.8
−0.3
0.8
–0.3
IIX
Input Load Current GND < VI < VCC
−1
+1
−1
+1
IOZ
Output Leakage
Current
−1
+1
−1
+1
IOS
Output Short Circuit VCC = Max.,
Current[2]
VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
2.4
0.4
GND < VI < VCC,
Output Disabled
2.4
2.4
0.4
Max. Unit
2.4
0.4
V
0.4
V
2.0
VCC
+ 0.3
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
-300
−300
–300
–300
mA
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
95
90
85
80
mA
Automatic CE
Power-Down
Current —TTL
Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL,
f = fMAX
15
15
15
15
mA
Automatic CE
Power-Down
Current —CMOS
Inputs
Max. VCC,
CE > VCC – 0.3V, VIN >
VCC – 0.3V,
or VIN < 0.3V, f = 0
5
5
5
5
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
8
pF
8
pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05132 Rev. *C
Page 3 of 12
CY7C1021CV33
AC Test Loads and Waveforms[4]
8-ns devices:
10-, 12-, 15-ns devices:
Z = 50Ω
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317Ω
3.3V
OUTPUT
30 pF*
OUTPUT
R2
351Ω
30 pF
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
3.0V
90%
GND
3.3V
ALL INPUT PULSES
90%
10%
Rise Time: 1 V/ns
10%
(c)
Fall Time: 1 V/ns
OUTPUT
R2
351Ω
5 pF
(d)
Note:
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05132 Rev. *C
Page 4 of 12
CY7C1021CV33
Switching Characteristics Over the Operating Range[5]
Parameter
Description
1021CV33-8
1021CV33-10
1021CV33-12
1021CV33-15
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
8
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
8
10
12
15
ns
tDOE
OE LOW to Data Valid
5
5
6
7
ns
[6]
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[6, 7]
Low-Z[6]
tLZCE
CE LOW to
tHZCE
CE HIGH to High-Z[6, 7]
tPU[8]
tPD[8]
CE LOW to Power-Up
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
10
8
3
10
3
0
3
5
0
0
6
0
5
ns
ns
15
ns
7
ns
0
6
ns
ns
7
12
5
0
4
3
0
10
ns
7
6
ns
ns
0
3
0
8
15
6
5
ns
3
0
3
0
12
5
4
15
3
0
4
CE HIGH to Power-Down
12
ns
7
ns
Write Cycle[9]
tWC
Write Cycle Time
8
10
12
15
ns
tSCE
CE LOW to Write End
7
8
9
10
ns
tAW
Address Set-Up to Write End
7
8
9
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
10
ns
tSD
Data Set-Up to Write End
5
5
6
8
ns
tHD
Data Hold from Write End
0
0
0
0
ns
Low-Z[6]
tLZWE
WE HIGH to
tHZWE
WE LOW to High-Z[6, 7]
tBW
Byte Enable to End of Write
3
3
4
6
3
5
7
3
6
8
ns
7
9
ns
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05132 Rev. *C
Page 5 of 12
CY7C1021CV33
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
IICC
CC
50%
IISB
SB
Notes:
10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
11. WE is HIGH for Read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05132 Rev. *C
Page 6 of 12
CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [13, 14]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
t BW
BHE, BLE
tSD
tHD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes:
13. Data I/O is high impedance if OE or BHE and/or BLE= VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05132 Rev. *C
Page 7 of 12
CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read – All bits
Active (ICC)
L
H
Data Out
High-Z
Read – Lower bits only
Active (ICC)
H
L
High-Z
Data Out
Read – Upper bits only
Active (ICC)
L
L
Data In
Data In
Write – All bits
Active (ICC)
L
H
Data In
High-Z
Write – Lower bits only
Active (ICC)
H
L
High-Z
Data In
Write – Upper bits only
Active (ICC)
L
X
L
I/O1–I/O8
I/O9–I/O16
Mode
Power
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05132 Rev. *C
Page 8 of 12
CY7C1021CV33
Ordering Information
Speed
(ns)
8
Ordering Code
CY7C1021CV33-8VC
CY7C1021CV33-8ZC
10
Package
Name
Package Type
V34
44-lead (400-Mil) Molded SOJ
Z44
44-lead TSOP Type II
CY7C1021CV33-8BAC
BA48A
CY7C1021CV33-10VC
V34
44-lead (400-Mil) Molded SOJ
Z44
44-lead TSOP Type II
CY7C1021CV33-12VC
BA48A
48-ball FBGA
V34
44-lead (400-Mil) Molded SOJ
Z44
44-lead TSOP Type II
CY7C1021CV33-15VC
BA48A
48-ball FBGA
V34
44-lead (400-Mil) Molded SOJ
CY7C1021CV33-15BAI
Document #: 38-05132 Rev. *C
Commercial
Industrial
Z44
44-lead TSOP Type II
CY7C1021CV33-15ZI
CY7C1021CV33-15BAC
Commercial
Industrial
CY7C1021CV33-15VI
CY7C1021CV33-15ZC
Commercial
Industrial
CY7C1021CV33-12BAI
15
Commercial
Industrial
CY7C1021CV33-12ZI
CY7C1021CV33-12BAC
Commercial
Industrial
CY7C1021CV33-12VI
CY7C1021CV33-12ZC
Commercial
Industrial
CY7C1021CV33-10BAI
12
Commercial
Industrial
CY7C1021CV33-10ZI
CY7C1021CV33-10BAC
Commercial
48-ball FBGA
CY7C1021CV33-10VI
CY7C1021CV33-10ZC
Operating
Range
Commercial
Industrial
BA48A
48-ball FBGA
Commercial
Industrial
Page 9 of 12
CY7C1021CV33
Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
Document #: 38-05132 Rev. *C
Page 10 of 12
CY7C1021CV33
Package Diagrams (continued)
44-Lead (400-Mil) Molded SOJ V34
51-85082-*B
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05132 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1021CV33
Document History Page
Document Title: CY7C1021CV33 64K x 16 Static RAM
Document Number: 38-05132
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
109472
12/06/01
HGK
New Data Sheet
*A
115044
05/08/02
HGK
Ram7 version C4K x 16 Async.
Remove “Preliminary”
*B
115808
06/25/02
HGK
ISB1 and ICC values changed
*C
120413
10/31/02
DFP
Updated BGA pin E4 to NC.
Document #: 38-05132 Rev. *C
Page 12 of 12
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