Cypress CY7C1011DV33-10ZSXI 2-mbit (128k x 16)static ram Datasheet

CY7C1011DV33
2-Mbit (128K x 16)Static RAM
Features
Functional Description
• Pin-and function-compatible with CY7C1011CV33
• High speed
The CY7C1011DV33 is a high-performance CMOS Static
RAM organized as 128K words by 16 bits.
— tAA = 10 ns
• Low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
— ICC = 90 mA @ 10 ns (Industrial)
• Low CMOS standby power
•
•
•
•
•
— ISB2 = 10 mA
Data Retention at 2.0 V
Automatic power-down when deselected
Independent control of upper and lower bits
Easy memory expansion with CE and OE features
Available in Lead-Free 44-pin TSOP II, and 48-ball VFBGA
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011DV33 is available in standard Lead-Free
44-pin TSOP II with center power and ground pinout, as well
as 48-ball fine-pitch ball grid array (VFBGA) packages
.
Pin Configuration
Logic Block Diagram
TSOP II
Top View
128K X 16
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
I/O0–I/O7
I/O8–I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
COLUMN
DECODER
BHE
WE
CE
OE
BLE
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com
Cypress Semiconductor Corporation
Document #: 38-05609 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 14, 2006
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CY7C1011DV33
Selection Guide
–10
10
90
10
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Unit
ns
mA
mA
Pin Configurations
48-Ball VFBGA
(Top View)
Document #: 38-05609 Rev. *C
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11 NC
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Page 2 of 11
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CY7C1011DV33
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage............. ...............................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current...................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[3] .... –0.3V to +4.6V
Range
DC Voltage Applied to Outputs
in High-Z State[3] .....................................–0.3V to VCC +0.3V
Industrial
DC Input Voltage[3] ..................................–0.3V to VCC +0.3V
Ambient
Temperature
VCC
–40°C to +85°C
3.3V ± 0.3V
DC Electrical Characteristics Over the Operating Range
Parameter
Description
–10
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage[2]
–0.3
0.8
V
IIX
Input Leakage Current
–1
+1
µA
IOZ
Output Leakage Current
GND < VOUT < VCC, Output Disabled
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
2.4
GND < VI < VCC
V
+1
µA
100 MHz
90
mA
83 MHz
80
66 MHz
70
40 MHz
60
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
20
mA
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
8
pF
8
pF
Notes
2. VIL (min.) = –2.0V and VIH(max) = VCC +2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05609 Rev. *C
Page 3 of 11
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CY7C1011DV33
Thermal Resistance[3]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
TSOP II
VFBGA
Unit
50.66
27.89
°C/W
17.17
14.74
°C/W
AC Test Loads and Waveforms[4]
Z = 50Ω
ALL INPUT PULSES
3.0V
90%
OUTPUT
50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
GND
90%
10%
10%
1.5V
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
R2
351Ω
5 pF
(c)
AC Switching Characteristics Over the Operating Range[5]
Parameter
Description
–10
Min.
Max.
Unit
Read Cycle
tpower[6]
VCC(typical) to the first access
100
µs
tRC
Read Cycle Time
10
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
10
ns
tDOE
OE LOW to Data Valid
5
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[7, 8]
5
ns
tLZCE
CE LOW to Low-Z[8]
10
3
tHZCE
CE HIGH to
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
ns
0
ns
3
High-Z[7, 8]
ns
ns
5
ns
10
ns
0
ns
Notes
4. AC characteristics (except High-Z) are tested using the load conditions shown in (a). High-Z characteristics are tested for all speeds using the test load shown
in (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
7. tHZOE, tHZCE, tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a
high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any
given device.
Document #: 38-05609 Rev. *C
Page 4 of 11
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CY7C1011DV33
AC Switching Characteristics Over the Operating Range[5] (continued)
Parameter
–10
Description
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
Min.
5
Write Cycle
ns
0
ns
Byte Disable to High-Z
tHZBE
Unit
Max.
6
ns
[9, 10]
tWC
Write Cycle Time
10
ns
tSCE
CE LOW to Write End
7
ns
tAW
Address Set-up to Write End
7
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
7
ns
tSD
Data Set-up to Write End
5
ns
tHD
Data Hold from Write End
0
ns
Low-Z[8]
tLZWE
WE HIGH to
tHZWE
WE LOW to High-Z[7, 8]
3
tBW
Byte Enable to End of Write
ns
5
ns
7
ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data Retention
Time
[3]
tR[13]
Operation Recovery Time
Conditions[12]
Min.
Max.
Unit
10
mA
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
V
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
tCDR
VDR > 2V
3.0V
tR
CE
Notes
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
10. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. No input may exceed VCC + 0.3V.
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs
Document #: 38-05609 Rev. *C
Page 5 of 11
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CY7C1011DV33
Switching Waveforms
Read Cycle No. 1[11, 14]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2(OE Controlled)[14, 15]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
IICC
CC
50%
IISB
SB
Notes
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05609 Rev. *C
Page 6 of 11
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CY7C1011DV33
Switching Waveforms (continued)
Write Cycle No. 1(CE Controlled)[16, 17]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATAI/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes
16. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05609 Rev. *C
Page 7 of 11
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CY7C1011DV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[16, 17]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
BHE, BLE
t
SD
DATA I/O
NOTE 18
tHD
DATAIN VALID
t
HZOE
Write Cycle No. 4 (WE Controlled, OE LOW)
tWC
BHE, BLE
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
DATA I/O
tSD
tHD
NOTE 18
tLZWE
Note
18. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05609 Rev. *C
Page 8 of 11
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CY7C1011DV33
Truth Table
CE
OE
WE
BLE
BHE
I/O0–I/O7
I/O8–I/O15
Mode
Power
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High-Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High-Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High-Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High-Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
Ordering Code
Package
Diagram
CY7C1011DV33-10ZSXI
51-85087
CY7C1011DV33-10BVI
51-85150
CY7C1011DV33-10BVXI
Package Type
44-pin TSOP II (Pb-Free)
Operating
Range
Industrial
48-ball VFBGA
48-ball VFBGA (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts
Package Diagrams
Figure 1. 44-Pin TSOP II (51-85087)
51-85087-*A
Document #: 38-05609 Rev. *C
Page 9 of 11
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CY7C1011DV33
Package Diagrams (continued)
Figure 2. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
4
5
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.15(4X)
0.10 C
0.21±0.05
0.25 C
B
51-85150-*D
C
1.00 MAX
0.26 MAX.
SEATING PLANE
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05609 Rev. *C
Page 10 of 11
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1011DV33
Document History
Document Title: CY7C1011DV33 2-Mbit (128K x 16)Static RAM
Document Number: 38-05609
REV.
ECN NO.
Issue Date
Orig. of
Change
**
250650
See ECN
RKF
New Data Sheet
*A
399070
See ECN
NXR
Changed from Advance to Preliminary
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed TQFP Package from product offering
Removed –15 speed bin
Corrected DC voltage limits in maximum ratings section from –0.5 to –0.3V
and VCC +0.5V to VCC +0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 100, 80 and 70 mA to 90, 80 and 75 mA for 8, 10
and 12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 70 mA to 90 and 85 mA for 10 and 12ns
speed bins respectively
Modified Note# 4 on AC Test Loads
Added Static Discharge Voltage and latch-up current spec
Added VIH(max) spec in Note# 2
Changed reference voltage level for measurement of Hi-Z parameters from
±500 mV to ±200 mV
Added Data Retention Characteristics Table and footnote on tR
Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram
Changed package name for 44-pin TSOP II from Z to ZS
Added 8 ns parts in the Ordering Information table
Shaded Ordering Information Table
*B
459073
See ECN
NXR
Converted Preliminary to Final.
Removed –8 and –12 Speed bins
Removed Commercial Operating Range from product offering.
Changed the description of IIX from “Input Load Current” to “Input Leakage
Current”
Updated the Thermal Resistance table.
Changed tHZBE from 5 ns to 6 ns.
Updated footnote #7 on High-Z parameter measurement
Added footnote #12.
Updated the Ordering Information and replaced Package Name column with
Package Diagram in the Ordering Information table.
*C
480177
See ECN
VKN
Added -10BVI product ordering code in the Ordering Information table.
Document #: 38-05609 Rev. *C
Description of Change
Page 11 of 11
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