Cypress CY2308SXC-4 3.3 v zero delay buffer Datasheet

CY2308
3.3 V Zero Delay Buffer
3.3 V Zero Delay Buffer
Features
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table Select Input Decoding
on page 3. If all output clocks are not required, Bank B is
three-stated. The input clock is directly applied to the output for
chip and system testing purposes by the select inputs.
■
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
■
Multiple configurations, see Available CY2308 Configurations
on page 4 for more details
■
Multiple low skew outputs
■
Two banks of four outputs, three-stateable by two select inputs
■
10 MHz to 133 MHz operating range
■
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
■
Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
■
3.3 V operation
The CY2308 is available in five different configurations as shown
in the table Available CY2308 Configurations on page 4.
■
Industrial temperature available
■
The CY2308-1 is the base part where the output frequencies
equal the reference if there is no counter in the feedback path.
The CY2308-1H is the high drive version of the -1 and rise and
fall times on this device are much faster.
■
The CY2308-2 enables the user to obtain 2x and 1x frequencies
on each output bank. The exact configuration and output
frequencies depend on the user’s selection of output that drives
the feedback pin.
■
The CY2308-3 enables the user to obtain 4x and 2x frequencies
on the outputs.
■
The CY2308-4 enables the user to obtain 2x clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
■
The CY2308-5H is a high drive version with REF/2 on both
banks.
The CY2308 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 25 A
of current draw. The PLL shuts down in two additional cases as
shown in the table Select Input Decoding on page 3.
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
Functional Description
The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven from
external FBK pin, so user has flexibility to choose any one of the
outputs as feedback input and connect it to FBK pin. The
input-to-output skew is less than 250 ps and output-to-output
skew is less than 200 ps.
Logic Block Diagram
/2
REF
PLL
FBK
MUX
/2
CLKA1
CLKA2
Extra Divider (–3, –4)
CLKA3
Extra Divider (–5H)
CLKA4
S2
Select Input
Decoding
S1
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –3)
Cypress Semiconductor Corporation
Document Number: 38-07146 Rev. *M
•
198 Champion Court
CLKB4
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 11, 2011
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CY2308
Contents
Pinouts .............................................................................. 3
Pin Definitions - 16-pin SOIC ........................................... 3
Select Input Decoding ...................................................... 3
Available CY2308 Configurations ................................... 4
Zero Delay and Skew Control .......................................... 4
Maximum Ratings ............................................................. 5
Operating Conditions for
Commercial Temperature Devices .................................. 5
Electrical Characteristics for
Commercial Temperature Devices .................................. 5
Switching Characteristics for
Commercial Temperature Devices .................................. 6
Operating Conditions for
Industrial Temperature Devices ...................................... 7
Electrical Characteristics for
Industrial Temperature Devices ...................................... 7
Switching Characteristics for
Industrial Temperature Devices ...................................... 8
Document Number: 38-07146 Rev. *M
Switching Waveforms ...................................................... 9
Typical Duty Cycle and IDD Trends .............................. 10
Typical Duty Cycle and IDD Trends .............................. 11
Test Circuits .................................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC Solutions ......................................................... 18
Page 2 of 18
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CY2308
Pinouts
Figure 1. Pin Diagram - 16-pin SOIC (Top View)
REF
CLKA1
1
16
2
15
CLKA2
VDD
3
14
4
13
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Pin Definitions - 16-pin SOIC
Pin
Signal
[1]
Description
1
REF
2
CLKA1 [2]
Clock output, Bank A
3
CLKA2
[2]
Clock output, Bank A
4
VDD
5
GND
6
7
8
9
Input reference frequency
Power supply voltage
Power supply ground
CLKB1
[2]
Clock output, Bank B
CLKB2
[2]
Clock output, Bank B
S2
[3]
S1
[3]
Select input, bit 2
Select input, bit 1
CLKB3
[2]
11
CLKB4
[2]
12
GND
Power supply ground
13
VDD
Power supply voltage
14
CLKA3 [2]
Clock output, Bank A
15
CLKA4
[2]
Clock output, Bank A
16
FBK
10
Clock output, Bank B
Clock output, Bank B
PLL feedback input
Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
0
Tri-state
Tri-state
PLL
Y
0
1
Driven
Tri-state
PLL
N
1
0
Driven [4]
Driven [4]
Reference
Y
1
1
Driven
Driven
PLL
N
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. Outputs inverted and PLL bypass mode for 2308-2 and 2308-3, S2 = 1 and S1 = 0.
Document Number: 38-07146 Rev. *M
Page 3 of 18
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CY2308
Available CY2308 Configurations
Feedback From [5]
Device
Bank A Frequency
Bank B Frequency
CY2308-1
Bank A or Bank B
Reference
Reference
CY2308-1H
Bank A or Bank B
Reference
Reference
CY2308-2
Bank A
Reference
Reference / 2
CY2308-2
Bank B
2 × Reference
Reference
CY2308-3
Bank A
2 × Reference
Reference [6]
CY2308-3
Bank B
4 × Reference
2 × Reference
CY2308-4
Bank A or Bank B
2 × Reference
2 × Reference
CY2308-5H
Bank A or Bank B
Reference / 2
Reference / 2
Zero Delay and Skew Control
Figure 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK Pin and CLKA/CLKB Pins
To close the feedback loop of the CY2308, the user has to
connect any one of the eight available output pins to FBK pin.
The output driving the FBK pin drives a total load of 7 pF plus
any additional load that it drives. The relative loading of this
output to the remaining outputs adjusts the input-output delay as
shown in the Figure 2.
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
If input-output delay adjustments are required, use the Zero
Delay and Skew Control graph to calculate loading differences
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
CY2308: Zero Delay Buffer-AN1234.
Notes
5. User has to select one of the available outputs that drive the feedback pin and need to connect selected output pin to FBK pin externally.
6. Output phase is indeterminant (0 ° or 180 ° from input clock). If phase integrity is required, use CY2308-2.
Document Number: 38-07146 Rev. *M
Page 4 of 18
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CY2308
Maximum Ratings
DC input voltage REF .......................................–0.5 V to 7 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage to ground potential ..............–0.5 V to +7.0 V
DC input voltage (except REF) ........... –0.5 V to VDD + 0.5 V
Storage temperature ................................ –65 °C to +150 °C
Junction temperature ................................................. 150 °C
Static discharge voltage
(MIL-STD-883, Method 3015) .................................. >2000 V
Operating Conditions for Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
3.0
3.6
V
VDD
Supply voltage
TA
Operating temperature (ambient temperature)
0
70
°C
CL
Load capacitance, below 100 MHz
–
30
pF
Load capacitance, from 100 MHz to 133 MHz
–
15
pF
CIN
Input capacitance [7]
–
7
pF
tPU
Power up time for all VDD’s to reach minimum specified voltage (power ramps
must be monotonic)
0.05
50
ms
Min
Max
Unit
–
0.8
V
Electrical Characteristics for Commercial Temperature Devices
Parameter
Description
VIL
Input LOW voltage
VIH
Input HIGH voltage
IIL
Input LOW current
IIH
VOL
VOH
Test Conditions
2.0
–
V
VIN = 0 V
–
50.0
A
Input HIGH current
VIN = VDD
–
100.0
A
Output LOW voltage [8]
IOL = 8 mA (-1, -2, -3, -4)
IOL = 12 mA (-1H, -5H)
–
0.4
V
Output HIGH voltage [8]
IOH = –8 mA (-1, -2, -3, -4)
IOH = –12 mA (-1H, -5H)
2.4
–
V
12.0
A
IDD (PD mode) Power down supply current
REF = 0 MHz
–
IDD
Unloaded outputs, 100 MHz REF, select
inputs at VDD or GND
–
45.0
mA
–
70.0 (-1H, -5H)
mA
Unloaded outputs, 66 MHz REF (-1, -2, -3, -4)
–
32.0
mA
Unloaded outputs, 33 MHz REF (-1, -2, -3, -4)
–
18.0
mA
Supply current
Notes
7. Applies to both Ref clock and FBK.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07146 Rev. *M
Page 5 of 18
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CY2308
Switching Characteristics for Commercial Temperature Devices
Parameter [9]
Min Typ
Max
Unit
Fin
Input frequency
–
10
–
133.3
MHz
t1
Output frequency
30 pF load
10
–
t1
Output frequency
20 pF load, -1H, -5H devices
10
–
133.3 (-1H)
66.67 (-5H)
MHz
t1
Output frequency
15 pF load, -1, -2, -3, -4 devices
10
–
133.3
MHz
tPD
Duty cycle [9] = t2 t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT = 66.66 MHz, 30 pF load 40.0 50.0
60.0
%
tPD
Duty cycle [9] = t2 t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT < 50 MHz, 15 pF load 45.0 50.0
55.0
%
t3
Rise time [9] (-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V, 30 pF load
–
–
2.20
ns
t3
Rise time
[9] (-1,
Measured between 0.8 V and 2.0 V, 15 pF load
–
–
1.50
ns
Rise time
[9] (-1H,
t3
t4
Name
Test Conditions
-2, -3, -4)
100 (-1, -2, -3, -4) MHz
66.67 (-5H)
-5H)
Measured between 0.8 V and 2.0 V, 30 pF load
–
–
1.50
ns
Fall time
[9] (-1,
-2, -3, -4)
Measured between 0.8 V and 2.0 V, 30 pF load
–
–
2.20
ns
-2, -3, -4)
Measured between 0.8 V and 2.0 V, 15 pF load
–
–
1.50
ns
Measured between 0.8 V and 2.0 V, 30 pF load
–
–
1.25
ns
Fall time
[9] (-1,
t4
Fall time
[9] (-1H,
t5
Output to output skew on
same Bank [9] (-1, -2, -3, -4)
All outputs equally loaded
–
–
200
ps
Output to output skew (-1H,
-5H)
All outputs equally loaded
–
–
200
ps
Output Bank A to output Bank All outputs equally loaded
B skew (-1, -4, -5H)
–
–
200
ps
Output Bank A to output Bank All outputs equally loaded
B skew (-2, -3)
–
–
400
ps
t6
Delay, REF rising edge to
FBK rising edge [9]
Measured at VDD/2
–
0
±250
ps
t7
Device to device skew [9]
Measured at VDD/2 on the FBK pins of devices
–
0
700
ps
Measured between 0.8 V and 2.0 V on -1H, -5H
device using Test Circuit 2
1
–
–
V/ns
Measured at 66.67 MHz, loaded outputs, 15 pF
load
–
75
200
ps
Measured at 66.67 MHz, loaded outputs, 30 pF
load
–
–
200
ps
Measured at 133.3 MHz, loaded outputs, 15 pF
load
–
–
100
ps
Cycle to cycle Jitter [9] (-2, -3) Measured at 66.67 MHz, loaded outputs, 30 pF
load
–
–
400
ps
Measured at 66.67 MHz, loaded outputs, 15 pF
load
–
–
400
ps
Stable power supply, valid clocks presented on
REF and FBK pins
–
–
1.0
ms
t4
-5H)
[9]
t8
Output slew rate
tJ
Cycle to cycle Jitter [9] (-1,
-1H, -4, -5H)
tJ
tLOCK
PLL lock time [9]
Note
9. All parameters are specified with loaded outputs.
Document Number: 38-07146 Rev. *M
Page 6 of 18
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CY2308
Operating Conditions for Industrial Temperature Devices
Min
Max
Unit
VDD
Parameter
Supply voltage
Description
3.0
3.6
V
TA
Operating temperature (ambient temperature)
–40
85
°C
CL
Load capacitance, below 100 MHz
–
30
pF
Load capacitance, from 100 MHz to 133 MHz
–
15
pF
–
7
pF
0.05
50
ms
Min
Max
Unit
[10]
CIN
Input capacitance
tPU
Power up time for all VDDs to reach minimum specified voltage (power ramps
must be monotonic)
Electrical Characteristics for Industrial Temperature Devices
Parameter
Description
Test Conditions
VIL
Input LOW voltage
–
0.8
V
VIH
Input HIGH voltage
2.0
–
V
IIL
Input LOW current
VIN = 0 V
–
50.0
A
IIH
Input HIGH current
VIN = VDD
–
100.0
A
IOL = 8 mA (-1, -2, -3, -4)
IOL = 12 mA (-1H, -5H)
–
0.4
V
2.4
–
V
[11, 12]
VOL
Output LOW voltage
VOH
Output HIGH voltage [11, 12]
IOH = –8 mA (-1, -2, -3, -4)
IOH = –12 mA (-1H, -5H)
IDD (PD mode) Power down supply current
REF = 0 MHz
–
25.0
A
IDD
Unloaded outputs, 100 MHz, Select inputs at
VDD or GND
–
45.0
mA
–
70 (-1H, -5H)
mA
Unloaded outputs, 66 MHz REF (-1, -2, -3, -4)
–
35.0
mA
Unloaded outputs, 66 MHz REF (-1, -2, -3, -4)
–
20.0
mA
Supply current
Notes
10. Applies to both Ref clock and FBK.
11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
12. All parameters are specified with loaded outputs.
Document Number: 38-07146 Rev. *M
Page 7 of 18
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CY2308
Switching Characteristics for Industrial Temperature Devices
Parameter [13]
Name
Test Conditions
Min Typ
Max
Unit
133.3
MHz
Fin
Input frequency
–
10
–
t1
Output frequency
30 pF load
10
–
t1
Output frequency
20 pF load, -1H, -5H devices
10
–
133.3 (-1H)
66.67 (-5H)
MHz
t1
Output frequency
15 pF load, -1, -2, -3, -4 devices
10
–
100 (-1,-2,-3,-4) MHz
66.67 (-5H)
133.3
MHz
Duty cycle
= t2 t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT = 66.66 MHz, 30 pF
load
40.0 50.0
60.0
%
tPD
Duty cycle [13, 14] = t2 t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT < 50 MHz, 15 pF load 45.0 50.0
55.0
%
t3
Rise time [13, 14] (-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V, 30 pF load
–
–
2.50
ns
t3
Rise time
[13, 14] (-1,
Measured between 0.8 V and 2.0 V, 15 pF load
–
–
1.50
ns
Rise time
[13, 14] (-1H,
–
–
1.50
ns
tPD
t3
t4
t4
[13, 14]
-2, -3, -4)
-5H)
Measured between 0.8 V and 2.0 V, 30 pF load
Fall time
[13, 14] (-1,
-2, -3, -4)
Measured between 0.8 V and 2.0 V, 30 pF load
–
–
2.50
ns
Fall time
[13, 14] (-1,
-2, -3, -4)
Measured between 0.8 V and 2.0 V, 15 pF load
–
–
1.50
ns
Fall time
[13, 14] (-1H,
Measured between 0.8 V and 2.0 V, 30 pF load
–
–
1.25
ns
All outputs equally loaded
–
–
200
ps
Output to output skew (-1H, -5H) All outputs equally loaded
–
–
200
ps
Output Bank A to output Bank B All outputs equally loaded
skew (-1, -4, -5H)
–
–
200
ps
Output Bank A to output Bank B All outputs equally loaded
skew (-2, -3)
–
–
400
ps
t6
Delay, REF rising edge to FBK Measured at VDD/2
rising edge [13, 14]
–
0
250
ps
t7
Device to device skew [13, 14]
Measured at VDD/2 on the FBK pins of devices
–
0
700
ps
Measured between 0.8 V and 2.0 V on -1H, -5H
device using Test Circuit 2
1
–
–
V/ns
Measured at 66.67 MHz, loaded outputs, 15 pF
load
–
75
200
ps
Measured at 66.67 MHz, loaded outputs, 30 pF
load
–
–
200
ps
Measured at 133.3 MHz, loaded outputs, 15 pF
load
–
–
100
ps
Measured at 66.67 MHz, loaded outputs, 30 pF
load
–
–
400
ps
Measured at 66.67 MHz, loaded outputs, 15 pF
load
–
–
400
ps
Stable power supply, valid clocks presented on
REF and FBK pins
–
–
1.0
ms
t4
t5
-5H)
Output to output skew on same
Bank [13, 14] (-1, -2, -3, -4)
[13, 14]
t8
Output slew rate
tJ
Cycle to cycle Jitter [13, 14] (-1,
-1H, -4, -5H)
tJ
tLOCK
Cycle to cycle Jitter [13, 14] (-2,
-3)
PLL lock time [13, 14]
Notes
13. All parameters are specified with loaded outputs.
14. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07146 Rev. *M
Page 8 of 18
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CY2308
Switching Waveforms
Figure 3. Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
Figure 4. All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
3.3V
0V
t4
t3
Figure 5. Output-Output Skew
1.4V
OUTPUT
1.4V
OUTPUT
t5
Figure 6. Input-Output Propagation Delay
VDD/2
INPUT
VDD/2
FBK
t6
Figure 7. Device-Device Skew
VDD/2
FBK, Device 1
VDD/2
FBK, Device 2
t7
Document Number: 38-07146 Rev. *M
Page 9 of 18
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CY2308
Typical Duty Cycle and IDD Trends
For CY2308-1, 2, 3, 4 [15, 16]
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
58
56
56
54
52
33 MHz
50
66 MHz
48
100 MHz
46
Duty Cycle (% )
Duty Cycle (% )
Duty Cycle Vs VD D
(for 30 pF Loads over Frequency - 3.3V, 25C)
54
66 MHz
50
100 MHz
48
133 MHz
46
44
44
42
42
40
33 MHz
52
40
3
3.1
3.2
3.3
3.4
3.5
3.6
3
3.1
3.2
VDD (V)
3.4
3.5
3.6
Duty C ycle Vs Fre que ncy
(for 15 pF Loads ov e r T e mpe rature - 3.3V)
Duty Cycle Vs Fre que ncy
(for 30 pF Loads ov e r T e mpe rature - 3.3V)
60
60
58
58
56
54
-40C
52
0C
50
25C
48
70C
46
85C
Duty Cycle (%)
56
Duty Cycle (%)
3.3
VDD (V)
54
-40C
52
0C
50
25C
48
70C
46
85C
44
44
42
42
40
40
20
40
60
80
100
120
140
20
40
60
Fre que ncy (M Hz)
80
100
120
140
Fre que ncy (M Hz)
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
140
140
120
120
100
100
80
33 M Hz
66 M Hz
60
80
33 M Hz
60
66 M Hz
100 M Hz
40
40
20
20
100 M Hz
0
0
0
2
4
6
N umb er o f Lo ad ed Out p ut s
8
0
2
4
6
8
N umb er o f Lo ad ed Out p ut s
Notes
15. Duty cycle is taken from typical chip measured at 1.4 V.
16. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current.
(n = number of outputs; C = Capacitance load per output (F); V = Voltage supply (V); f = frequency (Hz).
Document Number: 38-07146 Rev. *M
Page 10 of 18
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CY2308
Typical Duty Cycle and IDD Trends
For CY2308-1H, 5H [17, 18]
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
60
60
58
58
56
56
54
52
33 MHz
50
66 MHz
48
100 MHz
46
Duty Cycle (% )
Duty Cycle (% )
Duty Cycle Vs VD D
(for 30 pF Loads over Frequency - 3.3V, 25C)
54
33 MHz
52
66 MHz
50
100 MHz
48
133 MHz
46
44
44
42
42
40
40
3
3.1
3.2
3.3
3.4
3.5
3
3.6
3.1
3.2
Duty C ycle Vs Fre que ncy
(for 30 pF Loads ov e r T e mpe rature - 3.3V)
3.4
3.5
3.6
Duty Cycle Vs Fre que ncy
(for 15 pF Loads ov e r T e mpe rature - 3.3V)
60
60
58
58
56
56
54
-40C
52
0C
50
25C
48
70C
46
85C
Duty Cycle (%)
Duty Cycle (%)
3.3
VDD (V)
VDD (V)
54
-40C
52
0C
50
25C
48
70C
46
85C
44
44
42
42
40
40
20
40
60
80
100
120
140
20
40
60
Fre que ncy (M Hz)
80
100
120
140
Fre que ncy (M Hz )
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
140
140
120
120
100
100
80
60
33 MHz
80
66 MHz
60
100 MHz
40
33 MHz
66 MHz
100 MHz
40
20
20
0
0
0
2
4
6
N u m b e r o f L o a d e d Ou t p u t s
8
0
2
4
6
8
N u m b e r o f L o a d e d Ou t p u t s
Notes
17. Duty cycle is taken from typical chip measured at 1.4 V.
18. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current.
(n = number of outputs; C = Capacitance load per output (F); V = Voltage supply (V); f = frequency (Hz).
Document Number: 38-07146 Rev. *M
Page 11 of 18
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CY2308
Test Circuits
Test Circuit 1
Test Circuit 2
VDD
V DD
0.1 F
Outputs
CLK OUT
0.1 F
GND
Test Circuit for all parameters except t8
Document Number: 38-07146 Rev. *M
CLK out
10 pF
V DD
V DD
GND
Outputs
1 k
C LOAD
0.1 F
1 k
0.1 F
GND
GND
Test Circuit for t8, Output slew rate on -1H, -5H device
Page 12 of 18
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CY2308
Ordering Information
Ordering Code
Package Type
Operating Range
CY2308SI-1T
[19]
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308ZI-1H
[19]
16-pin 4.4 mm TSSOP
Industrial
16-pin 4.4 mm TSSOP - Tape and Reel
Industrial
16-pin 150 mil SOIC
Industrial
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308ZI-1HT
CY2308SI-2
[19]
[19]
CY2308SI-2T
[19]
Pb-free
CY2308SXC-1
16-pin 150 mil SOIC
Commercial
CY2308SXC-1T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI-1
16-pin 150 mil SOIC
Industrial
CY2308SXI-1T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SXC-1H
16-pin 150 mil SOIC
Commercial
CY2308SXC-1HT
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI-1H
16-pin 150 mil SOIC
Industrial
CY2308SXI-1HT
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308ZXC-1H
16-pin 4.4 mm TSSOP
Commercial
CY2308ZXC-1HT
16-pin 4.4 mm TSSOP - Tape and Reel
Commercial
CY2308ZXI-1H
16-pin 4.4 mm TSSOP
Industrial
CY2308ZXI-1HT
16-pin 4.4 mm TSSOP - Tape and Reel
Industrial
CY2308SXC-2
16-pin 150 mil SOIC
Commercial
CY2308SXC-2T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI-2
16-pin 150 mil SOIC
Industrial
CY2308SXI-2T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SXC-3
16-pin 150 mil SOIC
Commercial
CY2308SXC-3T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI-3
16-pin 150 mil SOIC
Industrial
CY2308SXI-3T
16-pin 150 mil SOIC - Tape and Reel
Industrial
CY2308SXC-4
16-pin 150 mil SOIC
Commercia
CY2308SXC-4T
16-pin 150 mil SOIC - Tape and Reel
Commercial
CY2308SXI-4
16-pin 150 mil SOIC
Industrial
CY2308SXI-4T
16-pin 150 mil SOIC - Tape and Reel
Industrial
Note
19. Not recommended for new designs.
Document Number: 38-07146 Rev. *M
Page 13 of 18
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CY2308
Ordering Code Definitions
CY 2308
X
X
X - X
X
X = T or blank
T = Tape and Reel; blank = Tube
Dash or Variant Code
Temperature Range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free, blank = leaded
Package Type: X = S or Z
S = 16-pin SOIC, Z = 16-pin TSSOP
Part Identifier
Company ID: CY = Cypress
Document Number: 38-07146 Rev. *M
Page 14 of 18
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CY2308
Package Diagrams
Figure 8. 16-pin SOIC (150 Mil) S16.15 Package Outline, 51-85068
51-85068 *D
Figure 9. 16-pin TSSOP 4.40 mm Body Z16.173 Package Outline, 51-85091
51-85091 *D
Document Number: 38-07146 Rev. *M
Page 15 of 18
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CY2308
Acronyms
Table 1. Acronyms Used in this Document
Acronym
Description
FBK
feedback
PLL
phase locked loop
MUX
multiplexer
Document Conventions
Units of Measure
Table 2. Units of Measure
Symbol
°C
Unit of Measure
Symbol
Unit of Measure
degrees Celsius
µW
microwatt
dB
decibels
mA
milliampere
fC
femtocoulomb
mm
millimeter
fF
femtofarad
ms
millisecond
Hz
hertz
mV
millivolt
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolt
k
kilohm

ohm
MHz
megahertz
pA
picoampere
M
megaohm
pF
picofarad
µA
microampere
pp
peak-to-peak
µF
microfarad
ppm
parts per million
µH
microhenry
ps
picosecond
µs
microsecond
sps
samples per second
µV
microvolt

sigma: one standard deviation
µVrms
microvolts root-mean-square
Document Number: 38-07146 Rev. *M
Page 16 of 18
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CY2308
Document History Page
Document Title: CY2308, 3.3 V Zero Delay Buffer
Document Number: 38-07146
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
**
110255
SZV
12/17/01
Changed from Specification number: 38-00528 to 38-07146
*A
118722
RGL
10/31/02
Added Note 4.
*B
121832
RBI
12/14/02
Power up requirements added to Operating Conditions Information
*C
235854
RGL
06/24/04
Added Pb-free Devices
*D
310594
RGL
02/09/05
Removed obsolete parts in the ordering information table
Specified typical value for cycle-to-cycle jitter
*E
1344343
KVM / VED
08/20/07
Brought the Ordering Information Table up to date: removed three obsolete
parts and added two parts
Changed titles to tables that are specific to commercial and industrial
temperature ranges
*F
2568575
AESA
09/19/08
Updated template. Added Note 19 “Not recommended for new designs.”
Changed IDD (PD mode) from 12.0 to 25.0 A for Commercial and Industrial
Temperature Devices
Deleted Duty Cycle parameters for Fout <50 MHz
Removed CY2308SI-4, CY2308SI-4T and CY2308SC-5HT.
*G
2632364
KVM
01/08/09
Corrected TSSOP package size (from 150 mil to 4.4 mm) in Ordering
Information table
*H
2673353
KVM /
PYRS
03/13/09
Reverted IDD (PD mode) and Duty Cycle parameters back to the values in
revision *E:
Changed IDD (PD mode) from 25 to 12 A for commercial temperature devices
Added Duty Cycle parameters for Fout <50 MHz for commercial and industrial
devices.
*I
2897373
CXQ
03/22/10
Updated Ordering Information.
Updated Package Diagrams.
Updated copyright section.
*J
2971365
BASH
07/06/10
Updated input to output skew and power down current number in Functional
Description, page 1
Update pin descriptions in ‘Pin Description’ column, Table1, page 2
Added ‘Input Frequency’ parameter and output frequency for -1H and -5H in
‘Switching Characteristics Table’ and removed footnote, page 4, 5, and 7.
Modified Description on page 1 and page 3 to make clear that user has to select
one of the outputs to drive feedback.
Added footnote in ‘Available CY2308 Configurations’ Table, page 3, for
clarification.
*K
3047133
CXQ
10/04/2010
Sunset Review. No change to data sheet from last revision.
*L
3055192
CXQ
10/11/2010
Updated Ordering Information (Removed part CY2308SXI-5H and
CY2308SXI-5HI).
*M
3402187
BASH
10/11/2011
Updated Ordering Information (Removed prune part numbers CY2308SI-1H
and CY2308SI-1HT).
Updated Package Diagrams.
Updated in new template.
Document Number: 38-07146 Rev. *M
Page 17 of 18
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CY2308
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07146 Rev. *M
Revised October 11, 2011
Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
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