BSI BS616LV2019AC Very low power/voltage cmos sram 128k x 16 bit Datasheet

BSI
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
„ FEATURES
BS616LV2019
• Easy expansion with CE and OE options
• Vcc operation voltage range : 2.7V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 23mA (@55ns) operating current
I -grade: 25mA (@55ns) operating current
C-grade: 15mA (@70ns) operating current
I -grade: 16mA (@70ns) operating current
0.3uA(Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• I/O Configuration x8/x16 selectable by LB and UB pin
„ DESCRIPTION
The BS616LV2019 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V /25oC and maximum access time of 55ns at 2.7V / 85oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2019 is available in DICE form , JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
BS616LV2019DC
BS616LV2019TC
BS616LV2019AC
BS616LV2019DI
BS616LV2019TI
BS616LV2019AI
Vcc
RANGE
SPEED
( ICCSB1, Max )
( ICC, Max )
55ns: 2.7~3.6V
70ns: 2.7~3.6V
Vcc=3.0V
Vcc=3.0V
55/70
3.0uA
23mA
15mA
-40 O C to +85 O C
2.7V ~ 3.6V
55/70
5.0uA
25mA
16mA
9
10
BS616LV2019TC
BS616LV2019TI
37
27
24
25
1
A
LB
2
OE
3
A0
DICE
TSOP1-48
BGA-48-0608
DICE
TSOP1-48
BGA-48-0608
„ BLOCK DIAGRAM
48
47
46
16
17
70ns
2.7V ~3.6V
O
1
13
55ns
PKG TYPE
+0 C to +70 C
O
„ PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
POWER DISSIPATION
STANDBY
Operating
( ns )
4
A1
5
A2
A16
NC
VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
VSS
/CE
A0
A8
A13
A15
Address
A16
A14
A12
Input
Buffer
A7
A6
A5
A4
16
DQ0
.
.
.
.
N.C.
.
.
.
.
UB
A3
A4
CE
D0
C
D9
D10
A5
A6
D1
D2
Memory Array
Decoder
1024 x 2048
Data
Input
Buffer
16
Column I/O
Write Driver
Sense Amp
16
Data
Output
Buffer
DQ15
D8
1024
Row
2048
6
B
20
128
16
Column Decoder
14
CE2 ,CE
WE
D
VSS
D11
N.C.
A7
D3
VCC
OE
UB
E
VCC
D12
N.C.
A16
D4
VSS
LB
F
D14
D13
A14
A15
D5
D6
G
D15
N.C.
A12
A13
WE
D7
H
N.C.
A8
A9
A10
A11
N.C.
Control
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Vcc
Gnd
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2019
1
Revision 1.2
May
2004
BSI
BS616LV2019
„ PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected. (48B BGA ignore CE2 pin)
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
„ TRUTH TABLE
MODE
CE2 (1)
WE
OE
LB
UB
D0~D7
D8~D15
X
X
X
X
X
High Z
High Z
ICCSB , I CCSB1
X
L
X
X
X
X
High Z
ICCSB , I CCSB1
Output Disabled
X
L
X
H
X
H
X
H
H
X
H
X
High Z
High Z
High Z
High Z
L
L
Dout
Dout
ICC
Read
L
H
H
L
H
L
High Z
Dout
ICC
L
H
Dout
High Z
ICC
L
L
Din
Din
ICC
Not selected
(Power Down)
Write
CE
H
L
H
L
X
High Z
Vcc CURRENT
ICCSB , I CCSB1
ICC
H
L
X
Din
ICC
L
H
Din
X
ICC
1. 48B BGA ignore CE2 condition.
R0201-BS616LV2019
2
Revision 1.2
May
2004
BSI
BS616LV2019
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
PARAMETER
V TERM
Terminal Voltage with
Respect to GND
V cc
Power Supply
„ OPERATING RANGE
RATING
UNITS
-0.5 to
Vcc+0.5
-0.5 to
Vcc+0.5
V
V
T BIAS
Temperature Under Bias
-40 to +85
O
C
T STG
Storage Temperature
-60 to +150
O
C
PT
Power Dissipation
1.0
W
I OUT
DC Output Current
20
mA
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0 O C to +70 O C
2.7V ~ 3.6V
Industrial
-40 O C to +85 O C
2.7V ~ 3.6V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
6
pF
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
„ DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER
NAME
PARAMETER
IIL
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current
ILO
VIL
VIH
TEST CONDITIONS
MIN.
TYP. (1) MAX.
Vcc =3.0V
-0.3
--
0.8
Vcc =3.0V
UNITS
V
2.0
--
Vcc+0.3
V
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
Output Leakage Current
Vcc = Max,CE = VIH or CE2 (4) = VIL or OE = VIH,
VI/O = 0V to Vcc
--
--
1
uA
VOL
Output Low Voltage
Vcc = Max, IOL = 2.0mA
Vcc =3.0V
--
--
0.4
V
VOH
Output High Voltage
Vcc = Min, IOH = -1.0mA
Vcc =3.0V
2.4
--
--
V
(4)
ICC(6)
Operating Power Supply
Current
CE = VIL, CE2 = VIH
IDQ = 0mA, F = Fmax(3)
ICCSB
Standby Current-TTL
CE=VIH or CE2 =VIL
IDQ = 0mA
Standby Current-CMOS
CE≧Vcc-0.2V or CE2(4)≦0.2V,
VIN≧Vcc-0.2V or VIN≦0.2V
3.0 V
70ns
16
--
--
Vcc =3.0V
--
--
0.5
mA
Vcc =3.0V
--
0.3
5.0
uA
55ns
mA
25
(4)
ICCSB1(5)
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. 48B BGA ignore CE2 condition.
5.IccsB1_Max. is 3.0uA at Vcc=3.0V and TA=70oC.
3. Fmax = 1/tRC.
6. Icc_Max. is 23mA(@55ns) / 15mA(@70ns) at Vcc=3.0V/ 0~70oC.
„ DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
Vcc for Data Retention
CE ≧ Vcc - 0.2V or CE2 ≦ 0.2V(3),
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
1.5
--
--
V
Data Retention Current
CE ≧ Vcc - 0.2V or CE2 ≦ 0.2V(3),
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
--
0.1
1.0
uA
--
--
ns
--
--
ns
SYMBOL
VDR
ICCDR
tCDR
tR
(4)
PARAMETER
Chip Deselect to Data
Retention Time
See Retention Waveform
Operation Recovery Time
1. Vcc = 1.5V, TA = + 25OC
3. 48B BGA ignore CE2 condition.
R0201-BS616LV2019
0
TRC
(2)
2. tRC = Read Cycle Time
4. IccDR is 0.7uA at TA=70oC.
3
Revision 1.2
May
2004
BSI
BS616LV2019
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
Vcc
tR
t CDR
CE ≥ Vcc - 0.2V
VIH
CE
VIH
„ KEY TO SWITCHING WAVEFORMS
„AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
WAVEFORM
Input and Output
Timing Reference Level
0.5Vcc
Output Load
CL = 100pF+1TTL
CL = 30pF+1TTL
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE (48B BGA ignore CE2 condition)
JEDEC
PARAMETER
NAME
PARAMETER
NAME
tAVAX
tRC
Read Cycle Time
55
--
--
70
--
--
ns
tAVQV
tAA
Address Access Time
--
--
55
--
--
70
ns
tELQV
tACS1 , 2
Chip Select Access Time
tBA
tBA (1)
Data Byte Control Access Time
CYCLE TIME : 55ns
DESCRIPTION
CYCLE TIME : 70ns
(Vcc = 2.7~3.6V)
(Vcc = 2.7~3.6V)
MIN. TYP. MAX.
UNIT
MIN. TYP. MAX.
(CE,CE2)
--
--
55
--
--
70
ns
(LB,UB)
--
--
30
--
--
35
ns
--
--
30
--
--
35
ns
tGLQV
tOE
Output Enable to Output Valid
t E1LQX
tCLZ
Chip Select to Output Low Z
(CE,CE2)
10
--
--
10
--
--
ns
tBE
tBE
Data Byte Control to Output Low Z
(LB,UB)
10
--
--
10
--
--
ns
tGLQX
tOLZ
Output Enable to Output in Low Z
5
--
--
5
--
--
ns
tEHQZ
tCHZ
Chip Deselect to Output in High Z
(CE,CE2)
--
--
30
--
--
35
ns
tBDO
tBDO
Data Byte Control to Output High Z
(LB,UB)
tGHQZ
tOHZ
Output Disable to Output in High Z
tAXOX
tOH
Data Hold from Address Change
--
--
30
--
--
35
ns
--
--
25
--
--
30
ns
10
--
--
10
--
--
ns
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
R0201-BS616LV2019
4
Revision 1.2
May
2004
BSI
BS616LV2019
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t RC
ADDRESS
t
t
t OH
AA
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
tACS2(6)
t
ACS1
CE
t
t CHZ(5,6)
(5,6)
CLZ
D OUT
READ CYCLE3 (1,4)
t RC
ADDRESS
t
AA
OE
t
CE2
t
t
CE
t
t
t
OE
OH
ACS2(6)
OLZ
t
ACS1
(5,6)
t
CLZ
OHZ
(5)
(1,5,6)
CHZ
LB,UB
t
t
BE
t
BDO
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
6. 48B BGA ignore this parameters related to CE2 .
R0201-BS616LV2019
5
Revision 1.2
May
2004
BSI
BS616LV2019
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE (48B BGA ignore CE2 condition)
JEDEC
PARAMETER
NAME
PARAMETER
NAME
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
tWLQZ
tDVWH
tWHDX
tGHQZ
t WC
t CW
t AS
t AW
t WP
t WR
t BW (1)
t WHZ
t DW
t DH
t OHZ
tWHOX
t OW
CYCLE TIME : 55ns
CYCLE TIME : 70ns
MIN. TYP. MAX.
MIN. TYP. MAX.
(Vcc = 2.7~3.6V)
(Vcc = 2.7~3.6V)
DESCRIPTION
UNIT
55
--
--
70
--
--
ns
55
--
--
70
--
--
ns
0
--
--
0
--
--
ns
Address Valid to End of Write
55
--
--
70
--
--
ns
Write Pulse Width
30
--
--
35
--
--
ns
0
--
--
0
--
--
ns
25
--
--
30
--
--
ns
--
--
25
--
--
30
ns
Data to Write Time Overlap
25
--
--
30
--
--
ns
Data Hold from Write Time
0
--
--
0
--
--
ns
Output Disable to Output in High Z
--
--
25
--
--
30
ns
End of Write to Output Active
5
--
--
5
--
--
ns
Write Cycle Time
Chip Select to End of Write
(CE,CE2)
Address Setup Time
Write recovery Time
(CE,CE2,WE)
Date Byte Control to End of Write
(LB,UB)
Write to Output in High Z
NOTE :
1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
(3)
t WR
OE
CE2
(5,12)
(11)
t CW
(5)
CE
t
BW
(5)
LB,UB
t AW
WE
(3)
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t DH
t DW
D IN
R0201-BS616LV2019
6
Revision 1.2
May
2004
BSI
BS616LV2019
WRITE CYCLE2 (1,6)
t WC
ADDRESS
(5,12)
CE2
(11)
t
(5)
CE
t
BW
(5)
LB,UB
t
WE
CW
AW
t WR
t WP
(3)
(2)
t AS
(4,10)
t WHZ
D OUT
t
OW
t
DH
(7)
(8)
t DW
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE going low to the end of write.
12. 48B BGA ignore this parameters related to CE2 .
R0201-BS616LV2019
7
Revision 1.2
May
2004
BSI
BS616LV2019
„ ORDERING INFORMATION
BS616LV2019 X X
Z
YY
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
T: TSOP1-48
A: BGA-48-0608
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
„ PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
1.4 Max.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
E1
e
D1
VIEW A
48 mini-BGA (6 x 8)
R0201-BS616LV2019
8
Revision 1.2
May
2004
BSI
BS616LV2019
„ PACKAGE DIMENSIONS
48
24
25
12°(2X)
b
E
1
UNIT
SYMBOL
e
12°(2X)
HD
Seating Plane
12°(2x)
y
"A"
MM
1.10±0.10
0.10±0.05
1.00±0.05
0.22±0.05
0.20±0.03
0.10 ~ 0.21
0.10 ~ 0.16
16.40±0.10
11.80±0.10
0.50±0.10
18.00±0.20
0.60±0.15
0.80±0.10
0.1 Max.
0°~ 8°
A
A2
D
INCH
0.0433±0.004
A
A1 0.004±0.002
A2 0.039±0.002
b
0.009±0.002
b1 0.008±0.001
c
0.004 ~ 0.008
c1 0.004 ~ 0.006
D
0.645±0.004
E
0.472±0.004
0.020±0.004
e
HD 0.708±0.008
L
0.0236±0.006
L1 0.0315±0.004
y
0.004 Max.
0°~ 8°
θ
GAUGE PLANE
24
25
0
SEATING PLANE
A
12°(2x)
b
WITH PLATING
"A" DETAIL VIEW
0.254
A1
A
L
L1
c c1
b1
BASE METAL
SECTION A-A
1
48
TSOP1-48PIN
R0201-BS616LV2019
9
Revision 1.2
May
2004
BSI
BS616LV2019
REVISION HISTORY
Revision Description
Date
1.1
Initial release
Jan., 05, 2004
1.2
Change Vcc_min
from 2.4V to 2.7V
May, 03, 2004
R0201-BS616LV2019
10
Note
Revision 1.2
May
2004
Similar pages