Anpec APU0063 80ch driver for dot matrix lcd Datasheet

APU0063
PRELIMINARY
80 CH Driver for Dot Matrix LCD
FEATURES
GENERAL DESCRIPTION
Display driving bias ; static-1/5
The APU0063 is a LCD driver LSI that is fabricated
by low power CMOS technology. Basically this LSI
consists of 40 × 2bit bi-directional shift register, 40
•
Power supply voltage ; +5V ± 10%
+3V ± 10%
•
•
× 2bit data latch and 40 × 2bit driver.
Supply voltage range for display : ≤ 10V
Negative display voltage :
APPLICATIONS
0 ≥ VEE ≥ VDD-10V
•
•
CMOS Process
•
•
•
Interface
Driver (cascade connection) Controller
Other APU0065
APU0066
Dot matrix LCD driver with 80-channel output.
Input / Output signal
Output ; 40 × 2 channel waveform for LCD
driving
•
Input ; - Serial display data and control pulse
from controller LSI .
ORDERING INFORMATION
APU0063
E
Package Type
Q : QFP
Y : Chip
Handling Code
Handling Code
TY : Tray
Package Type
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
1
www.anpec.com.tw
APU0063
PRELIMINARY
SC1~SC40
End Stage
Output Voltage
Multiplexor
Part1
SC41~SC80
V1 V2 V3 V4
V 1S
V 2S
Pre-Stage
Output Voltage
Multiplexor
Part1
V 1S
V 2S
End Stage
Output Voltage
Multiplexor
Part2
PART 1
PART 2
latch clock
LATCH part 2
LATCH part1
register clock
DL1
SHIFT part 2
SHIFT part 1
SHL1
DR1
CL1
M
CL2
DL2
DR2
SHL2
Figure 1.Block diagram of APU0063
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
2
www.anpec.com.tw
PRELIMINARY
APU0063
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
78
50 NC
79
S71 81
49 NC
80
S72 82
41 NC
S33 98
S34 97
S35 96
S36 95
S37 94
S38 93
S39 92
32 V 1
33 V 2
34 V 3
35 V 4
36 GND
37 CL1
38 SHL1
39 SHL2
40 NC
S32 99
31 V E E
21
22
23
24
25
26
S4
27
S3
28
S2
29
S1
30
18
S5
17
S6
16
S7
15
S8
14
S9
13
S31 100
S40 91
S80 90
48 M
20
S73 83
APU0063
19
47 DR2
12
S74 84
11
46 DL2
10
S75 85
9
45 DR1
8
S76 86
7
44 DL1
6
S77 87
5
43 CL2
4
S78 88
3
42 V D D
2
S19 S18 S17 S16 S15 S14 S13 S12 S11 S10
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3
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
S79 89
1
S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20
Figure 2. QFP100 Top View
APU0063
PRELIMINARY
PIN DESCRIPTION-QFP100
PIN(NO.)
INPUT ¡þ
OUTPUT
DESCRIPTION
NAME
V E E (31)
Power
Negative Supply
Voltage
V D D (42)
Power
V S S (36)
INTERFACE
For LCD driver circuit
(0 ≥ V E E ≥ V D D -10V)
Power Supply
Operating Voltage
For logic circuit
(+5V 10% ,+3V 10%)
Power Supply
Power
Operating Voltage
0 V ( G N D)
Power Supply
V 1 ~ V 4 (32 ~ 35)
Input
Bias Voltage
Bias Voltage level for LCD drive
Power Supply
M(48)
Input
CL1(37)
Input
Data Latch Clock
The signal enable the latch, it is
negative senstive latched.
Controller
CL2(43)
Input
Data Shift Clock
The signal enable the shift
register, it is negative edge-trigger.
Controller
Input
Shifting Direction
Control Signal of
Part1
SHL1(38)
Altemated Signal for
This is the signal for LCD twisting
LCD Driver Output
DL1, DR1
(44, 45)
Input
Output
Data Interface
S C 1 ~ SC 40
Output
LCD Driver
SHL2(39)
Input
Selection of the shift directon of
Part1 shift register
Input
Output
Data Interface
S C 41 ~ SC 80
Output
LCD Driver
SHL1
DL1
DR1
VDD
Output
Input
V SS
Input
Output
Data input / output pf Part1 shift
register
LCD driver output of Part1
Controller
Controller
or
APU0066
LCD
Selection of the shift directon of
Part2 shift register
Shifting Direction
Control Signal of
Part2
DL2, DR2
(46, 47)
Controller
SHL2
DL2
DR2
VDD
Output
Input
V SS
Input
Output
Data input / output pf Part2 shift
register
LCD driver output of Part2
Controller
Controller
or
APU0066
LCD
NOTE : Input pin can not be floated,or it will cause large leakage current.
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
4
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APU0063
PRELIMINARY
DRIVER OUTPUT VOLTAGE
A signal of driving pin is the one of V1,V2,V3 or V4.These selecting are following.
D a ta o f la tc h
H ig h
H ig h
Low
Low
M
H ig h
Low
H ig h
Low
O u tp u t v o lta g e
V1
V2
V3
V4
SHIFT DRIRECTION SPECIFICATION
Part1
Part2
When Part1 shift direction control signal ,
When Part2 shift direction control signal,
SHL1, is set to VSS.
SHL2, is set to VSS.
Now the Part1 register shift direction is
Now the Part2 register shift direction is
DL1 → SC1 → SC2 → . . . → SC39 → SC40
DL2 → SC41 → SC42 → . . . → SC79 →
→ DR1
SC80 → DR2
Otherwise,when SHL1 is set to VDD.Its
Otherwise,when SHL2 is set to VDD.Its
direction is
direction is
DL1 ← SC1 ← SC2 ← . . . ← SC39 ← SC40
DL2 ← SC41 ← SC42 ← . . . ← SC79 ←
← DR1
SC80 ← DR2
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
5
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APU0063
PRELIMINARY
MAXIMUM ABSOLUTE LIMIT (Ta = 25 °C)
Symbol
Value
Unit
Operating Voltage
V DD
- 0.3 ~ + 7.0
V
Driver Supply Voltage
V LCD
V DD - 13.5 ~ VDD + 0.3
V
Input Voltage 1
V IN1
- 0.3 ~ VDD + 0.3
V
Input Voltage 2 (V1~ V 4 )
V IN2
V DD + 0.3 ~ VE E - 0.3
V
Operating Temperature
TO P R
- 30 ~ + 85
o
C
Storage Temperature
TS T G
- 55 ~ + 125
o
C
Characteristic
∗ Voltage greater than above may damage to the circuit
ELECTRICAL CHARACTERISTICS
DC characteristics (VDD = 2.7 ~ 5.5V, 0 ≥ VEE ≥ VDD - 10V, VSS = 0V, Ta = - 30 ~ + 85 °C )
Characteristic
Symbol
Test condition
Min
Max
Unit
Operating Current*
ID D
f CL2 = 4 0 0 K H z
_
1
mA
10
µA
Supply Current*
IE E
f CL1 = 1 KHz
_
Input High Voltage
V IH
_
0.7 V D D
V DD
Input Low Voltage
V IL
0
0.3 V D D
Input Leakage Current
I LKC
Output High Voltage
V OH
Output Low Voltage
V OL
V D1
Voltage Descending
V D2
Leakage Current
IV
-5
5
V DD - 0.4
_
I OL = +0.4 mA
_
0.4
I O N = 0.1mA for one of SC1-SC80
_
1.1
ION = 0 . 0 5 m A f o r e a c h S C 1 - S C 8 0
_
1.5
-10
10
V IN = 0 - V D D
I O H = -0.4 mA
V IN = V DD ~ V E E
(Output SC1 ~ SC80 : floating)
V
µA
Applicable pin
_
CL1, CL2, DR1, DR2,
DR1, DR2, SHL1, SHL2,
M, FCS
DL1, DL2, DR1, DR2
V
V (V 1 ~ V 4 ) SC (SC1 ~ SC80)
µA
V1 ~ V4
AC CHARACTERISTICS (VDD = 2.7 ~ 5.5V, 0 ≥ VEE ≥ VDD - 10V, VSS = 0V, Ta= - 30 ~ + 85 °C )
Characteristic
Data shift Frequency
Clock High Level Width
Clock Low Level Width
Symbol
Test condition
Min
Max
Unit
Applicable pin
fCL
_
_
400
KHz
CL2
tW C K H
_
800
_
tW C K L
_
_
800
_
tSL
from CL2 to CL1
500
_
tLS
from CL1 to CL2
500
_
Clock Rise/Fall Time
tR / tF
_
_
200
Data Set-up Time
tS U
_
300
_
Data Hold Time
tD H
_
Data Delay Time
tD
CL1=15pF
Clock Set-up Time
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
300
_
6
CL1, CL2
CL2
CL1, CL2
ns
_
DL1, DL2, DR1, DR2, FLM
500
DL1, DL2, DR1, DR2
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APU0063
PRELIMINARY
TIMING CHARACTERISTICS
V IH
V IH
tWCKL
CL2
V IL
V IL
tW C K H
tR
tF
tD H
tS U
Data in
(DL1,DL2)
(DR1,DR2)
V IH
V IL
tSL
tD
Data out
(DR1,DR2)
(DL1,DL2)
tLS
tLS
V OH
V OL
V IH
V IL
CL1
tR
tSU
tW C K H
tF
V IH
FLM
V IL
Figure 3.Timing diagram of signals
M
Latch
CL1
Shift
CL2
DL1 / DR1
DL2 / DR2
SC1 SC2
OUTPUT OF
LATCH (SC)
SC79 SC80
SC1~SC80
Figure 4.timing diagram
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
7
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APU0063
PRELIMINARY
OUTPUT OF
LATCH (DATA)
M
V2
V4
V3
S C 1 ~ S C 80
V1
Figure 5.SC1~SC80 output waveform
APPLCATION CIRCUIT
COM1
~
COM16
APU0066
(controller)
M
CLK2
CLK1
LCD
common signal
D
SHL1
SHL2
FCS
DL1
DR1
DL2
S C 1~ S C 80
APU0063
(seg driver)
CL1
CL2
SHL1
SHL2
FCS
DR2
DL1
DR1
M
DL2
S C 1~ S C 80
APU0063
(seg driver)
CL1
CL2
DR2
M
OPEN
Figure 6.Connection between APU0063 and Controller
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
8
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S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
78
77
76
75
74
73
72
71
70
69
68
67
66
65
S16 S17
64
63
S18
S19
S20
S21 S22
62
61
60
59
58
S23
S24
S25
S26
S27
S28
S29
S30
S31
57
56
55
54
53
52
51
50
49
S1
79
48
S32
V
80
47
S33
46
S34
82
45
S35
83
44
S36
43
S37
GND 85
42
S38
CL1
86
41
S39
SHL1 87
40
S40
39
S80
89
38
S79
CL2
90
37
S78
DL1
91
36
S77
35
S76
34
S75
33
S74
EE
V
V
V
V
1
2
3
4
81
APU0063
84
Y
X
(0,0)
SHL2 88
PRELIMINARY
V
DD
Chip size : 3438 x 2476
Pad size : 80 x 80
DR1 92
DL2
Pad Pitch : 100 ~ 125
Unit : µm
93
APU0063
DR2 94
M
95
32
S73
S41
96
31
S72
1
2
S42 S43
3
4
S44 S45
5
6
7
8
9
S46
S47
S48
S49
S50
10
11
S51 S52
12
13
14
15
16
S53
S54
S55
S56 S57
17
18
19
20
21
S58
S59
S60
S61 S62
22
23
24
25
26
S63
S64
S65
S66 S67
27
28
29
30
S68
S69
S70
S71
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S5
9
S4
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
S3
Note : ( 0 , 0 ) is center in the chip
Button left corner coordination is ( -1719 , -1238 )
Top right corner coordination is ( 1719 , 1238 )
Figure 7.Chip pad arrangement
S2
APU0063
PRELIMINARY
PAD LOCATION (1/2)
PAD NUMBER PAD NAME
COORDINATE
X
Y
PAD NUMBER PAD NAME
COORDINATE
X
Y
1
SC42
-1645
-1132
33
SC74
1609
-680
2
SC43
-1520
-1132
34
SC75
1609
-560
3
SC44
-1395
-1132
35
SC76
1609
-450
4
SC45
-1270
-1132
36
SC77
1609
-350
5
SC46
-1145
-1132
37
SC78
1609
-250
6
SC47
-1020
-1132
38
SC79
1609
-150
7
SC48
-900
-1132
39
SC80
1609
-50
8
SC49
-780
-1132
40
SC40
1609
50
9
SC50
-660
-1132
41
SC39
1609
150
10
SC51
-550
-1132
42
SC38
1609
250
11
SC52
-450
-1132
43
SC37
1609
350
12
SC53
-350
-1132
44
SC36
1609
450
13
SC54
-250
-1132
45
SC35
1609
560
14
SC55
-150
-1132
46
SC34
1609
680
15
SC56
-50
-1132
47
SC33
1609
800
16
SC57
50
-1132
48
SC32
1609
920
17
SC58
150
-1132
49
SC31
1645
1132
18
SC59
250
-1132
50
SC30
1520
1132
19
SC60
350
-1132
51
SC29
1395
1132
20
SC61
450
-1132
52
SC28
1270
1132
21
SC62
550
-1132
53
SC27
1145
1132
22
SC63
660
-1132
54
SC26
1020
1132
23
SC64
780
-1132
55
SC25
900
1132
24
SC65
900
-1132
56
SC24
780
1132
25
SC66
1020
-1132
57
SC23
660
1132
26
SC67
1145
-1132
58
SC22
550
1132
27
SC68
1270
-1132
59
SC21
450
1132
28
SC69
1395
-1132
60
SC20
350
1132
29
SC70
1520
-1132
61
SC19
250
1132
30
SC71
1645
-1132
62
SC18
150
1132
31
SC72
1609
-920
63
SC17
50
1132
32
SC73
1609
-800
64
SC16
-50
1132
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
10
www.anpec.com.tw
APU0063
PRELIMINARY
PAD LOCATION (2/2)
PAD NUMBER PAD NAME
COORDINATE
X
Y
PAD NUMBER PAD NAME
COORDINATE
X
Y
65
SC15
-150
1132
81
V1
-1609
680
66
SC14
-250
1132
82
V2
-1609
560
67
SC13
-350
1132
83
V3
-1609
450
68
SC12
-450
1132
84
V4
-1609
350
69
SC11
-550
1132
85
GND
-1609
250
70
SC10
-660
1132
86
CL1
-1609
150
71
SC9
-780
1132
87
SHL1
-1609
50
72
SC8
-900
1132
88
SHL2
-1609
-50
73
SC7
-1020
1132
89
V DD
-1609
-150
74
SC6
-1145
1132
90
CL2
-1609
-250
75
SC5
-1270
1132
91
DL1
-1609
-350
76
SC4
-1395
1132
92
DR1
-1609
-450
77
SC3
-1520
1132
93
DL2
-1609
-560
78
SC2
-1645
1132
94
DR2
-1609
-680
79
SC1
-1609
920
95
M
-1609
-800
80
V EE
-1609
800
96
S41
-1609
-920
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
11
www.anpec.com.tw
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