Cypress CY7C1069AV33-12ZC 2m x 8 static ram Datasheet

CY7C1069AV33
2M x 8 Static RAM
Features
• High speed
— tAA = 8, 10, 12 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
Functional Description
The CY7C1069AV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE1
LOW and CE2 HIGH) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) as well as forcing the Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE1 LOW, CE2 HIGH, and WE
LOW).
The CY7C1069AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
Pin Configuration
TSOP II
Top View
NC
VCC
NC
I/O6
VSS
I/O7
A4
A3
A2
A1
A0
NC
CE1
VCC
WE
CE2
A19
A18
A17
A16
A15
I/O0
VCC
I/O1
NC
VSS
NC
2M x 8
ARRAY
4096 x 4096
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O0–I/O7
WE
CE2
OE
CE1
A10
A11
A 12
A 13
A 14
A15
A16
A17
A18
A19
A20
COLUMN
DECODER
1
54
53
2
3
4
52
51
5
6
50
49
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
VSS
NC
I/O5
VCC
I/O4
A5
A6
A7
A8
A9
NC
OE
VSS
DNU
A20
A10
A11
A12
A13
A14
I/O3
VSS
I/O2
NC
VCC
NC
Selection Guide
–8
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document #: 38-05255 Rev. *D
•
–10
–12
Unit
8
10
12
ns
Commercial
300
275
260
mA
Industrial
300
275
260
Commercial/Industrial
50
50
50
3901 North First Street
•
mA
San Jose, CA 95134
•
408-943-2600
Revised February 10, 2003
CY7C1069AV33
Pin Configurations
48-ball FBGA
(Top View)
4
3
5
6
OE
A0
A1
A2
CE2
A
NC
NC
A3
A4
CE1
NC
B
I/O0
NC
A5
A6
NC
I/O4
C
VSS I/O1 A17
A7
I/O 5 V
CC
D
1
2
NC
VCC I/O2
A18
A16 I/O6
VSS
E
NC
A14
A15
NC
I/O7
F
DNU A12
A13
WE NC
G
A10
A11
H
I/O3
NC
A19
Document #: 38-05255 Rev. *D
A8
A9
A20
Page 2 of 9
CY7C1069AV33
Maximum Ratings
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 0.3V
Industrial
–40°C to +85°C
–8
Parameter
Description
Test Conditions
Min.
–10
Max.
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[1]
IIX
Input Load Current
IOZ
Output Leakage Current GND < VOUT < VCC, Output
Disabled
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX Commercial
= 1/tRC
Industrial
300
300
ISB1
Automatic CE
Power-down Current
—TTL Inputs
CE2 < VIL,
Max. VCC, SCE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
CE2 < 0.3V
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
2.4
Min.
2.4
0.4
GND < VI < VCC
Commercial/
Industrial
–12
Max.
Min.
Max.
Unit
2.4
0.4
V
0.4
V
V
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
–1
+1
–1
+1
–1
+1
µA
–1
+1
–1
+1
–1
+1
µA
275
260
mA
275
260
mA
70
70
70
mA
50
50
50
mA
Capacitance[2]
Parameter
CIN
Package
Z54
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
BA48
COUT
Z54
I/O Capacitance
BA48
Max.
Unit
6
pF
8
pF
8
pF
10
pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05255 Rev. *D
Page 3 of 9
CY7C1069AV33
AC Test Loads and Waveforms[3]
50Ω
VTH = 1.5V
OUTPUT
Z0 = 50Ω
R1 317 Ω
3.3V
OUTPUT
30 pF*
R2
351Ω
5 pF*
(a)
All input pulses
3.3V
*Capacitive Load consists of all
components of the test environment
GND
Rise time > 1V/ns
90%
10%
90%
10%
[4]
–8
Parameter
Description
Min.
(b)
Fall time:
> 1V/ns
(c)
AC Switching Characteristics Over the Operating Range
*Including
jig and
scope
–10
Max.
Min.
–12
Max.
Min.
Max.
Unit
Read Cycle
tpower
VCC(typical) to the First Access[5]
1
1
1
ms
tRC
Read Cycle Time
8
10
12
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW/CE2 HIGH to Data Valid
8
10
12
ns
tDOE
OE LOW to Data Valid
5
5
6
ns
10
Low-Z[6]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[6]
10
3
1
[6]
CE1 LOW/CE2 HIGH to Low-Z
tHZCE
CE1 HIGH/CE2 LOW to High-Z[6]
Power-up[7]
tPU
CE1 LOW/CE2 HIGH to
tPD
CE1 HIGH/CE2 LOW to Power-down[7]
3
3
3
0
8
ns
6
5
ns
ns
6
0
10
ns
ns
1
5
5
0
12
3
1
5
tLZCE
Write
3
ns
ns
12
ns
Cycle[8, 9]
tWC
Write Cycle Time
8
10
12
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
6
7
8
ns
tAW
Address Set-up to Write End
6
7
8
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
ns
tSD
Data Set-up to Write End
5
5.5
6
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low-Z[6]
3
3
3
ns
tHZWE
High-Z[6]
WE LOW to
5
5
6
ns
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD , normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
5. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation
is started.
6. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV
from steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal Write time of the memory is defined by the overlap of CE1 LOW / CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of
the signal that terminates the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05255 Rev. *D
Page 4 of 9
CY7C1069AV33
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
VDR > 2V
3.0V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS
tRC
CE1
CE2
tASCE
OE
tHZOE
tDOE
tHZSCE
tLZOE
DATA OUT
HIGH IMPEDANCE
tLZSCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes:
10. Device is continuously selected. CE1 = VIL, CE2 = VIH.
11. WE is HIGH for Read cycle.
Document #: 38-05255 Rev. *D
Page 5 of 9
CY7C1069AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 Controlled)[13, 14, 15]
tWC
ADDRESS
tSA
CE
tSCE
tAW
tHA
tPWE
WE
t BW
tSD
tHD
DATAI/O
Write Cycle No. 2 (WE Controlled, OE LOW) [13, 14, 15]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE1
CE2
OE
WE
I/O0–I/O7
Mode
Power
H
X
X
X
High-Z
Power-down
Standby (ISB)
X
L
X
X
High-Z
Power-down
Standby (ISB)
L
H
L
H
Data Out
Read All Bits
Active (ICC)
L
H
X
L
Data In
Write All Bits
Active (ICC)
L
H
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Notes:
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. Data I/O is high-impedance if OE = VIH.
14. If CE1 goes HIGH / CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state.
15. CE above is defined as a combination of CE1 and CE2. It is active low.
Document #: 38-05255 Rev. *D
Page 6 of 9
CY7C1069AV33
Ordering Information
Speed
(ns)
8
10
12
Ordering Code[16]
CY7C1069AV33-8ZC
CY7C1069AV33-8ZI
CY7C1069AV33-8BAC
CY7C1069AV33-8BAI
CY7C1069AV33-10ZC
CY7C1069AV33-10ZI
CY7C1069AV33-10BAC
CY7C1069AV33-10BAI
CY7C1069AV33-12ZC
CY7C1069AV33-12ZI
CY7C1069AV33-12BAC
CY7C1069AV33-12BAI
Package
Name
Z54
BA48
Z54
BA48
Z54
BA48
Package Type
54-pin TSOP II
48-ball Mini BGA
54-pin TSOP II
48-ball Mini BGA
54-pin TSOP II
48-ball Mini BGA
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Package Diagrams
54-lead Thin Small Outline Package, Type II Z54-II
51-85160-**
Note:
16. Contact a Cypress Representative for availability of the 48-ball Mini BGA (BA48) package.
Document #: 38-05255 Rev. *D
Page 7 of 9
CY7C1069AV33
Package Diagrams (continued)
48-ball (8 mm x 20 mm x 1.2 mm) FBGA BA48G
51-85162-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05255 Rev. *D
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1069AV33
Document History Page
Document Title: CY7C1069AV33 2M x 8 Static RAM
Document Number: 38-05255
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
113724
03/27/02
NSL
New Data Sheet
*A
117060
07/31/02
DFP
Removed 15-ns bin
*B
117990
08/30/02
DFP
Added 8-ns bin
Changing ICC for 8, 10, 12 bins
tpower changed from 1 µs to 1 ms
Load Cap Comment changed (for Tx line load)
tSD changed to 5.5 ns for the 10-ns bin
Changed some 8-ns bin #’s (tHZ, tDOE, tDBE)
Removed hz < lz comments
*C
120385
11/13/02
DFP
Final Data Sheet
Added note 4 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd
Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin
TSOP to 6/8 pf
*D
124441
2/25/03
MEG
Changed ISB1 from 100 mA to 70 mA
Shaded the 48fBGA product offering information
Document #: 38-05255 Rev. *D
Page 9 of 9
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