FREESCALE MC33397DW/R2

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33397/D
Rev 2.0, 03/2003
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33397
Dual/Hex Low-Side Switch with
Both SPI and Parallel Input Control
Freescale Semiconductor, Inc...
The 33397 is a low-side switch that is user configurable to be either two
333 mΩ outputs (dual mode) or six 900 mΩ outputs (hex mode). Each output
is internally current limited and short-circuit protected. Output fault detection
capability includes “off state” open loads and “on state” short-to-battery
conditions. Faults for each output are latched into the fault register and serially
shifted out during serial communication.
DUAL/HEX LOW-SIDE SWITCH
Features
• User Configurable to be Either Two 333 mΩ Outputs (Dual Mode) or Six
900 mΩ Outputs (Hex Mode)
• Output Inductive Energy Clamps
• Parallel Input (3.3 V and 5.0 V Compatible) or Serial Peripheral Interface
(SPI) Control
• 8-Bit SPI Control and Fault Diagnostics
• Short-to-Battery Detection and Shutdown with Automatic Retry
• OFF-State Open-Circuit Detection
• Programmable Overvoltage Shutdown (VPWR Pin)
• Undervoltage Shutdown (VDD Pin)
• Sleep Mode—IDD ≤ 25 µA (1.0 µA Typical)
DW SUFFIX
PLASTIC PACKAGE
CASE 751E
24-LEAD SOICW
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33397DW/R2
-40 to 125°C
24 SOICW
33397 Simplified Application Diagram
EN
VDD 13
33397
VPWR 24
+VBAT
A0
23
Microcontroller
with Bus
EN
15
CS
10
SCLK
3
SI
4
A1
14
CMOS
Input
Logic
CMOS
Serial
Shift
Registers
and
Latches
Output
Switches
and
Sense
Circuits
A2
12
A3
11
A4
2
SO
9
A5
1
GND
5-8, 17-20
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2003
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CS SI
A0
SO SCLK
8-Bit SPI Interface
3.0 V +
Sleep Mode
40 µA
50 V
A1
+
- 3.0 V
Sleep Mode
40 µA
1.2 Ω
50 V
1.2 Ω
Logic
Logic
Dual Mode
Dual Mode
ILIMIT
ILIMIT
Freescale Semiconductor, Inc...
A4
3.0 V +
Sleep Mode
40 µA
50 V
40 µA
1.2 Ω
1.2 Ω
Logic
Logic
Dual Mode
Dual Mode
3.0 V +
Sleep Mode
+
- 3.0 V
1.2 Ω
A3
Sleep Mode
40 µA
40 µA
50 V
50 V
ILIMIT
ILIMIT
A5
A2
+ 3.0 V
Sleep Mode
Logic
50 V
1.2 Ω
Logic
ILIMIT
ILIMIT
Parallel Gate Control
and
Mode Control Logic
P0
10 µA
10 µs Filter
P2
10 µA
+
0.75 VDD 0.25 VDD +
-
S Q
R
P1
VPWR
10 µA
30 V
Overvoltage
Shutdown
Low VDD Detect
and POR Timer
+
-
3.0 V
VDD
VDD
EN
Figure 1. 33397 Simplified Block Diagram
33397
2
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A5
1
24
VPWR
A4
2
23
A0
SCLK
3
22
P2
SI
4
21
P1
GND
5
20
GND
GND
6
19
GND
GND
7
18
GND
GND
8
17
GND
SO
9
16
P0
CS
10
15
EN
A3
11
14
A1
A2
12
13
VDD
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Description
1, 2, 11, 12,
14, 23
A0–A5
Power outputs
3
SCLK
SPI clock input
4
SI
SPI serial input
5–8, 17–20
GND
9
SO
SPI serial output
10
CS
SPI chip select
13
VDD
Supply input pin
15
EN
Enable
16
P0
In hex mode, P0 controls output A0. In dual mode, P0 controls outputs A0, A4, and A5 simultaneously
21
P1
In hex mode, P1 controls output A1. In dual mode, P2 controls outputs A1, A2, and A3 simultaneously
22
P2
In hex mode, P2 controls output A2. P2 is also the mode control pin. If 0.25*VDD<P2<0.75*VDD for more than
10 µs, the 33397 will change to dual mode
24
VPWR
Power and signal ground
Overvoltage threshold shutdown monitoring pin (not a power supply pin for the IC)
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Power Supply Voltage
VPWR
50
V
Logic Supply Voltage
VDD
-0.3 to 7.0
V
Input Pin Voltage
VIN
-0.3 to VDD+0.3
V
Human Body Model (Note 1)
VESD1
±2000
Machine Model (Note 2)
VESD2
±200
V
ESD Voltage
mJ
Freescale Semiconductor, Inc...
Single Pulse Output Clamp Energy
IO =500 mA, TJ =150°C (Hex Mode)
JCLAMP1
50
IO =1.5 A, TJ =150°C (Dual Mode)
JCLAMP1
100
fOP
3.5
MHz
TSTG
-55 to 150
°C
TJ
-40 to 150
°C
TSOLDER
260
°C
RθJ-L
15
°C/W
Recommended SPI Operating Frequency
Storage Temperature
Operating Junction Temperature
Soldering Temperature (for 10 Seconds)
Thermal Resistance, Junction-to-Lead (Note 3)
Notes
1. ESD1 performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 Ω).
2.
ESD2 performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω).
3.
Leads 5, 6, 7, 8, 17, 18, 19, and 20 are soldered to a heat-sinking ground plane. See Figure 14.
33397
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
IPWR(ON)
–
1.0
50
µA
IPWR(SS)
–
1.0
10
VP(OV)
30
33
38
V
VP(OV)Hys
0.3
0.5
1.5
V
IDD
–
1.20
5.0
mA
IDDSS
–
1.0
25
µA
VDD(LVI)
2.5
3.0
3.5
V
High
VIH
0.8
–
–
Low
VIL
–
–
0.2
Upper Threshold
VDMH
0.7
0.75
0.8
Lower Threshold
VDML
0.2
0.25
0.3
IINPD
10
20
30
POWER INPUT
VPWR Supply Current (All Outputs ON)
µA
VPWR Sleep State Supply Current
VPWR =17 V, SPI Bit 7=1, EN=5.0 V
Overvoltage Shutdown
Freescale Semiconductor, Inc...
Overvoltage Shutdown Hysteresis
Logic Supply Current (All Outputs ON)
Logic Supply Current (Sleep State: EN=5.0 V, SPI Bit 7=1)
Logic Supply Undervoltage Inhibit Threshold
INPUT
Input Voltage (P0, P1, P2, EN, SI, SCLK, CS)
Dual Mode Threshold (P2)
VDD
VDD
µA
Input Current
Pull-Down (P0, P1)-VIN =VDD
IINPD
5.0
10
30
IINPU
-20
-10
-5.0
IINPU
-100
–
-10
IINPU
-10
0
10
IO =0.35 A, TJ =-40°C
0.39
0.5
1.2
IO =0.35 A, TJ =25°C
0.51
0.7
1.2
IO =0.35 A, TJ =150°C
0.51
1.0
1.2
IDS =20 mA, Output Off
50
55
60
IDS =200 mA, Output Off
50
56
60
0
–
10
Pull-Down (P2)-VIN =VDD
Pull-Up (CS)-VIN =0 V
Pull-Up (EN)-VIN =0 V
Pull-Up (SCLK, SI)-VIN =2.5 V
OUTPUT
Output Drain to Source ON Resistance (Hex Mode) (Note 4)
Output Voltage Clamp
RDS(ON)
BVDSS
Output Leakage Current (Hex Mode)
IO(SS)
EN=H, bit 7=1, VDRAIN =24 V
Output Logic Voltage (SO), ILOAD =1.0 mA
Ω
V
µA
High
VOH
0.8
–
–
Low
VOL
–
–
0.2
ISOT
-10
–
10
Output Tristate Leakage (SO), VSO =2.5 V
VDD
µA
Notes
4. This parameter is specified for hex mode. In dual mode, the parameter will be three times smaller.
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
1.0
1.5
2.0
Unit
FAULT DETECTION
Output Self-Limiting Current (Hex Mode) (Note 5)
IO(LIM)
Outputs Programmed ON
Output Fault Detect Threshold Voltage
0.5
0.6
0.7
20
40
80
µA
IO(OFF)
Output Programmed OFF, EN=0
Freescale Semiconductor, Inc...
VDD
VOF(TH)
Outputs Programmed OFF, EN=0
Output OFF Open Load Detect Current
A
Notes
5. This parameter is specified for hex mode. In dual mode, the parameter will be three times smaller.
33397
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
1.0
1.2
10
Unit
OUTPUT TIMING
Output Rise Time
Output Fall Time
µs
tF
VPWR =14 V, RLOAD =25 Ω, 80–20%
Freescale Semiconductor, Inc...
µs
tR
VPWR =14 V, RLOAD =25 Ω, 20–80%
1.0
2.0
10
Output Turn-On Propagation Delay
tPON
1.0
4.0
10
µs
Output Turn-Off Propagation Delay
tPOFF
1.0
4.0
10
µs
Output Short-to-Battery Fault Filter Time
tSS
30
50
90
µs
Output Refresh Timer
tREF
3.0
4.1
6.0
ms
D
0.2
1.56
3.0
%
tOOF
30
50
90
µs
–
80
110
–
80
110
–
30
50
–
30
50
–
65
80
–
100
140
–
0
50
FAULT TIMING
Output Refresh Timer Duty Cycle
Output Off-State Open Circuit Fault Filter Time
SPI/MISCELLANEOUS TIMING
SO Disable Time (10 K Pull-Up Resistor on SO)
tSODIS
CS=0.8 V to SO > 0.8*VDD
SO Enable Time (10 K Pull-Up Resistor on SO)
ns
tSOEN
CS=0.8 V to SO Low Impedance
SO Rise Time
ns
ns
tSORISE
CL < 200 pF
SO Fall Time
ns
tSOFALL
CL < 200 pF
SO Valid Time
ns
tVALID
Falling Edge of SCLK to SO Valid
Required Time Between Falling Edge of CS to Rising Edge of
SCLK
tLEAD
Required TIme Between Rising Edge of CS to Falling Edge of
SCLK
tLAG
Required Time Between SI to Rising Edge of SCLK
tSU
–
25
45
ns
POR/EN Wake-Up Timer
tPOR
20
40
60
µs
Mode Change Timer (P2)
tMODE
5.0
10
25
µs
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
ns
ns
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Timing Diagrams
CS
tLEAD
tLAG
SCLK
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SI
tSU
SO
tSOEN
tSODIS
tVALID
Figure 2. SPI Timing Diagram
CS
SCLK
SI
HIZ
SO
PO
P1
P2
EN
A0
tPON
A1
A2
tFALL
tRISE
tPOFF
A3-A5
Note: In hex mode, the outputs are controlled by the SPI or by the parallel inputs. However, P0, P1, and P2 only control A0,
A1, and A2, respectively. When EN goes high, the part is disabled.
Figure 3. Operation Waveforms for Hex Control
33397
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VDD
0.8 VDD
P0, P1
0.2 VDD
tPON
0V
tR
tF
tPOFF
Freescale Semiconductor, Inc...
80%
20%
VDS
0V
Figure 4. Response Times
Short-to-Battery
Period
VDD
VIN
(P0, P1)
VDS
ILIMIT
ILOAD
ILOAD
tREF
tREF
tSS
Figure 5. Short-to-Battery Fault
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VDDLV1
VDD
tPOR
Power On Reset
(Internal Signal)
2.5 V
P2
tMODE
tMODE
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Hex
Mode
A2
Dual
Mode
Figure 6. Power On Reset and Mode Select
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TYPICAL CHARACTERISTICS
0.2
1.2
0.18
1
CURRENT (µA)
0.16
RDS(ON) (Ω)
0.8
0.6
0.4
0.14
0.12
0.1
0.08
0.06
0.04
0.2
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (DEG C)
TA, AMBIENT TEMPERATURE (DEG C)
Figure 7. Output on Resistance versus Temperature
Figure 10. IVPWR versus Temperature
1.4
58
1.3
57.6
5V SUPPLY CURRENT (µA)
DRAIN TO CLAMP (V)
57.8
57.4
57.2
57
56.8
56.6
56.4
56.2
-50
-25
0
25
50
75
100
1.2
1.1
1
0.9
0.8
-50
125 150
TA, AMBIENT TEMPERATURE (DEG C)
-25
0
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (DEG C)
Figure 8. Drain to Source Clamp versus Temperature
Figure 11. IDD versus Temperature
1.74
3
1.72
2.5
CURRENT (µA)
1.7
CURRENT (A)
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0.02
0
-50
1.68
1.66
1.64
2
1.5
1
1.62
0.5
1.6
1.58
-50
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (DEG C)
Figure 9. Current Limit versus Temperature
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
150
0
-50
-25
0
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (DEG C)
Figure 12. IDD Sleep State versus Temperature
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SPI Output Word Definition
SPI Input Word Definition
MSB
MSB
7
6
5
4
3
2
1
0
7
6
5
3
2
1
0
<-DIN
A0 Fault
A1 Fault
A0 Enable
A1 Enable
A2 Enable
A3 Enable
A2 Fault
A3 Fault
A4 Enable
A4 Fault
A5 Fault
A5 Enable
Not Used (Don’t Care)
Zero
Sleep Mode Feedback (1=Sleep Mode Enabled)
Enable Sleep Mode
Freescale Semiconductor, Inc...
4
<DOUT
<-DIN
The device will power up with sleep mode enabled.
In dual mode, input bits 0, 4, and 5 must all be high to turn on combinational output A0, A4, and A5 via the SPI.
In dual mode, input bits 1, 2, and 3 must all be high to turn on combinational output A1, A2, and A3 via the SPI.
Figure 13. SPI Input/Output Word Definition
Table 1. Truth Table
Inputs
Outputs
EN
SPI
Bit7
A0
A1
A2
A3
A4
A5
Comments
P0
P1
P2
0
0
0
0
X
OFF
OFF
OFF
*
*
*
HEX MODE
0
0
1
0
X
OFF
OFF
ON
*
*
*
* = Outputs A3, A4, and A5 are SPI controlled only.
0
1
0
0
X
OFF
ON
OFF
*
*
*
0
1
1
0
X
OFF
ON
ON
*
*
*
1
0
0
0
X
ON
OFF
OFF
*
*
*
1
0
1
0
X
ON
OFF
ON
*
*
*
1
1
0
0
X
ON
ON
OFF
*
*
*
1
1
1
0
X
ON
ON
ON
*
*
*
0
0
0
1
0
OFF
OFF
OFF
OFF
OFF
OFF
HEX MODE
0
0
1
1
0
OFF
OFF
ON
OFF
OFF
OFF
Outputs A3, A4, and A5 are always OFF.
0
1
0
1
0
OFF
ON
OFF
OFF
OFF
OFF
0
1
1
1
0
OFF
ON
ON
OFF
OFF
OFF
Outputs A0, A1, and A2 are only controlled via inputs P0, P1,
and P2.
1
0
0
1
0
ON
OFF
OFF
OFF
OFF
OFF
Sleep mode disabled.
1
0
1
1
0
ON
OFF
ON
OFF
OFF
OFF
1
1
0
1
0
ON
ON
OFF
OFF
OFF
OFF
1
1
1
1
0
ON
ON
ON
OFF
OFF
OFF
0
0
2.5 V
0
X
OFF
OFF
OFF
OFF
OFF
OFF
DUAL MODE
0
1
2.5 V
0
X
OFF
ON
ON
ON
OFF
OFF
Outputs are also controlled via SPI. SPI fully functional.
1
0
2.5 V
0
X
ON
OFF
OFF
OFF
ON
ON
1
1
2.5 V
0
X
ON
ON
ON
ON
ON
ON
0
0
2.5 V
1
0
OFF
OFF
OFF
OFF
OFF
OFF
DUAL MODE
0
1
2.5 V
1
0
OFF
ON
ON
ON
OFF
OFF
1
0
2.5 V
1
0
ON
OFF
OFF
OFF
ON
ON
Outputs are not controlled via SPI. Outputs are controlled via
inputs P0 and P1. Sleep mode disabled.
1
1
2.5 V
1
0
ON
ON
ON
ON
ON
ON
X
X
X
1
1
OFF
OFF
OFF
OFF
OFF
OFF
33397
12
X = Don't care.
Outputs A0, A1, and A2 are controlled either via SPI or inputs
P0, P1, and P2.
Outputs are not controlled via SPI.
All outputs disabled. SPI is reset and ignored. No fault
detection.
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65
°C/W
60
PCB
Heat Sink
Flag 1
55
PCB
Heat Sink
Flag 2
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50
45
0
1
2
3
4
5
6
7
8
Total Square Inches of Heat Sink Flag Area (Flag 1 + Flag 2)
9
10
Figure 14. Approximate Thermal Resistance Using PCB Heat Sinking
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33397 is a versatile dual-mode low-side switch that can
be output-configured as two 333 mΩ open drain outputs in the
dual mode or as six 900 mΩ open drain outputs in the hex mode
(RDS(ON) @ 25°C).
Each open drain output has internal current limit and shortcircuit protection. Current limit is typically 1.5 A, with 2.0 A
maximum. The outputs can be input controlled via parallel
inputs or the SPI. Three inputs provide parallel control, while a
serial 8-bit word provides SPI control of the outputs. Output fault
detection capability includes OFF-state open loads and ONstate short-to-battery conditions. Individual output faults are
latched into the fault register and serially shifted out during
serial communication to the 33397. The 33397 has both
overvoltage and undervoltage shutdown.
A low quiescent current sleep slate feature can be enabled
or disabled on command via the SPI port.
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FUNCTIONAL PIN DESCRIPTION
VDD
In hex mode, P2 is the parallel input to control output A2. It is
OR'd with SPI bit 2 to enable output A2. Either one will enable
output A2.
Logic power supply pin.
A0–A5
A0–A5 are the drains of the 1.2 Ω (max.) MOSFETs. They
each have an internal voltage clamp of 50 V (min.) to clamp
inductive loads during turn-off. When enabled, they are each
internally current limited to a maximum of 2.0 A. If any output is
in current limit (output voltage >3.0 V) for a time greater than
tSS, the output will be disabled for a time tREF and then try to
turn on again. When disabled, open circuits are detected if the
output is less than 3.0 V for a time of tSS. Either type of fault is
reported as a fault on the SPI output word. If EN input is high
and SPI bit 7=1, the pull-down current sources on the outputs
are disabled to minimize VDD supply current.
In hex mode, all six outputs are independent. Outputs A0,
A1, and A2 are controlled by either the SPI input word bits 0, 1,
and 2, respectively, or parallel inputs P0, P1, and P2. Outputs
A3, A4, and A5 are controlled only by SPI input word bits 3, 4,
and 5, respectively.
In dual mode, outputs A0, A4, and A5 are all controlled
simultaneously by input P0 or by SPI bits 0, 4, and 5. All three
bits must be high to enable this output via the SPI. Outputs A1,
A2, and A3 are all controlled simultaneously by input P1 or by
SPI bits 1, 2, and 3. All three bits must be high to enable this
output via the SPI.
P0–P2
In hex mode, P0 is the parallel input to control output A0. It is
OR'd with SPI bit 0 to enable output A0. Either one will enable
output A0. In dual mode, P0 controls outputs A0, A4, and A5
simultaneously. P0 has a pull down current of 10 µA. It is
ignored when EN is high and bit 7=1.
In hex mode, P1 is the parallel input to control output A1. It is
OR'd with SPI bit 1 to enable output A1. Either one will enable
output A1. In dual mode, P1 controls outputs A1, A2, and A3
simultaneously. P1 has a pull-down current of 10 µA. It is
ignored when EN is high and bit 7=1.
33397
14
P2 also is used to program the 33397 to either a dual or hex
output device. The 33397 will be the hex mode if P2 is biased
above 0.75*VDD (typical) or below 0.25*VDD (typical). Normal
5.0 V control logic on this parallel input will maintain the 33397
in hex mode and allow control of output A2. If 0.25*VDD
<P2<0.75*VDD for more than 10 µs, the 33397 will switch to
dual mode. P2 has a pull-down current of 10 µA. It is ignored
when EN is high and bit 7=1.
VPWR
VPWR is used to sense an overvoltage condition on the
supply pin. When the voltage on VPWR exceeds VOV, all outputs
are disabled for the duration of the overvoltage condition. If
VPWR is grounded, overvoltage shutdown is disabled. VPWR
threshold can be modified with an external resistor divider if
higher thresholds are desired.
SCLK
SCLK is the clock for the serial interface.
SI
SI is the serial input for the SPI port. When CS is low, SI is
read on the positive edge of SCLK and SO is updated on the
falling edge. When CS is high, SI is ignored. SI has a pull-down
current source to pull it low in the event of an open circuit.
SO
SO is the serial output of the SPI port. When CS goes low,
SO outputs bit 7 of the output word. On each falling edge of
SCLK, SO will shift the next SPI output bit until on the eighth
SCLK falling edge the bit present on SI during the first rising
edge will appear. In this way devices can be daisy-chained to
operate on a common CS. When CS is high, SO is high
impedance.
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CS
CS is the chip select to enable the SPI interface. When CS is
high, no SPI communication is possible. When CS goes low, SI
will be read on each rising SCLK edge and SO will shift on each
SCLK falling edge. When CS goes high, the bits present in the
SPI input register will be interpreted as the SPI input command.
Also when CS goes high, all faults that were latched into the SPI
output register are cleared. If faults are still present on outputs,
they will be re-latched after tSS.
EN
or when the IC is powered up from VDD, a power-up timer of
40 µs is started to allow the 33397 to determine which mode it
is in (hex or dual). During this time all parallel inputs and serial
control SPI bits will be ignored and all outputs will remain off. If
EN transitions low when not in the sleep mode, this “dead” time
will not occur.
If a one was written to bit 7, the 33397 will be in the sleep
mode when EN goes high. In this mode all SPI registers are
reset to zero and all faults are cleared. No fault detection is
possible. The standby supply current on VDD and VPWR is
minimized.
Freescale Semiconductor, Inc...
EN must be low for complete IC functionality in either the dual
or hex mode. When EN transitions low while in the sleep mode
APPLICATIONS
A voltage on the P2 input pin determines the mode. All six
outputs can operate either independently (hex mode)
(Figure 15) or in paralleled groups of three (dual mode)
(Figure 16). In the dual mode, outputs A0, A1, and A2 are
controlled by parallel inputs P0, P1, and P2, respectively, and
they are also controlled by the SPI port with which they are
OR’d. On the other hand, outputs A3, A4, and A5 are controlled
only through the SPI port. When the voltage on P2 is between
VBAT VBAT
VBAT
VBAT
0.25 VDD and 0.75 VDD (i.e., when P2 is held at an intermediate
voltage, neither high nor low), the 33397 operates in the dual
mode. However, the P2 pin must stay at that level for a
minimum specified time. In this mode, outputs A0, A4, and A5
are all controlled in parallel by input P0. Outputs A1, A2, and A3
are all controlled in parallel by input P1. Both outputs can also
be controlled via the SPI port as well, but only if the three
outputs are commanded ON at the same time.
VBAT
33397
To Microprocessor
VBAT VBAT
VBAT
33397
A5
VPWR
A5
VPWR
A4
A0
A4
A0
SCLK
P2
SCLK
P2
SI
P1
SI
P1
GND
GND
GND
GND
GND
GND
GND
GND
SO
P0
CS
EN
A3
A1
A2
VDD
Parallel Inputs
(Optional)
To Microprocessor
VBAT
From Microprocessor
VDD
VBAT
Figure 15. Hex Mode Application Circuit
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
GND
GND
GND
GND
GND
GND
GND
GND
SO
P0
CS
EN
A3
A1
A2
VDD
VDD
Parallel Inputs
(Optional)
From Microprocessor
VDD
Figure 16. Dual Mode Application Circuit
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33397
15
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PACKAGE DIMENSIONS
DW SUFFIX
(24-LEAD SOIC WIDE BODY)
PLASTIC PACKAGE
CASE 751E-04
ISSUE E
-A24
13
-B-
12X
P
0.010 (0.25)
Freescale Semiconductor, Inc...
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
C
-TSEATING
PLANE
33397
16
M
22X
G
K
X 45 °
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0×
8×
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0×
8×
0.395
0.415
0.010
0.029
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
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33397
17
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
33397
18
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33397
19
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