TC59LM914/06AMG-37,-50
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
512Mbits Network FCRAM1 (SSTL_18 / HSTL_Interface)
− 4,194,304-WORDS × 8 BANKS × 16-BITS
− 8,388,608-WORDS × 8 BANKS × 8-BITS
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle
Random Access Memory (Network FCRAMTM) containing 536,870,912 memory cells. TC59LM914AMG is organized
as 4,194,304-words × 8 banks × 16 bits, TC59LM906AMG is organized as 8,388,608-words × 8 banks × 8 bits.
TC59LM914/06AMG feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM914/06AMG can operate fast core cycle compared with regular DDR SDRAM.
TC59LM914/06AMG is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
CL = 3
tCK
Clock Cycle Time (min)
CL = 4
CL = 5
tRC
Random Read/Write Cycle Time (min)
tRAC Random Access Time (max)
IDD1S Operating Current (single bank) (max)
lDD2P Power Down Current (max)
lDD6 Self-Refresh Current (max)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TC59LM914/06
-37
5.5 ns
4.5 ns
3.75 ns
22.5 ns
22.0 ns
280 mA
90 mA
20 mA
-50
6.0 ns
5.5 ns
5.0 ns
27.5 ns
24.0 ns
240 mA
80 mA
20 mA
Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 3.75 ns minimum
Clock: 266 MHz maximum
Data: 533 Mbps/pin maximum
Fast cycle and Short Latency
Eight independent banks operation
When BA2 input assign to A14 input, TC59LM914/06AMG can function as 4 bank device
(Keep backward compatibility to 256Mb)
Bidirectional differential data strobe signal : TC59LM906AMG
Bidirectional data strobe signal per byte
: TC59LM914AMG
Distributed Auto-Refresh cycle in 3.9 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 3, 4, 5
Burst Length = 2, 4
Organization: TC59LM914AMG : 4,194,304 words × 8 banks × 16 bits
TC59LM906AMG : 8,388,608 words × 8 banks × 8 bits
Power Supply Voltage
VDD:
2.5 V ± 0.125V
VDDQ: 1.4 V ∼ 1.9 V
1.8 V CMOS I/O comply with SSTL_18 and HSTL
Package:
60Ball BGA, 1mm × 1mm Ball pitch (P−BGA64−1317−1.00AZ)
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
Rev 1.0
2004-08-20
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TC59LM914/06AMG-37,-50
TC59LM906AMG
PIN NAMES
PIN
NAME
PIN
NAME
A0~A13
Address Input
DQS / DQS
Write/Read Data Strobe
BA0~BA2
Bank Address
VDD
Power (+2.5 V)
DQ0~DQ7
Data Input / Output
VSS
Ground
CS
Chip Select
VDDQ
Power (+1.5 V / +1.8 V)
(for I/O buffer)
FN
Function Control
VSSQ
Ground (for I/O buffer)
PD
Power Down Control
VREF
Reference Voltage
CLK, CLK
Clock Input
NC
Not Connected
4 bank operation can be performed using BA2 as A14.
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
x8
1
2
5
6
VSS
DQ7
DQ0
VDD
B
NC
VSSQ
VDDQ
NC
C
DQ6
VDDQ
VSSQ
DQ1
D
NC
DQ5
DQ2
NC
E
NC
VSSQ
VDDQ
NC
DQ4
VDDQ
VSSQ
DQ3
G
NC
VSSQ
VDDQ
NC
H
NC
DQS
DQS
NC
J
VREF
VSS
VDD
BA2
CLK
CLK
FN
A13
L
A12
PD
CS
NC
M
A11
A9
BA1
BA0
N
A8
A7
A0
A10
P
A5
A6
A2
A1
R
VSS
A4
A3
VDD
A
F
K
Index
NC
NC
3
4
NC
NC
: Depopulated ball
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TC59LM914/06AMG-37,-50
TC59LM914AMG
PIN NAMES
PIN
NAME
PIN
NAME
A0~A13
Address Input
UDQS/LDQS Write/Read Data Strobe
BA0~BA2
Bank Address
VDD
Power (+2.5 V)
DQ0~DQ15
Data Input / Output
VSS
Gorund
CS
Chip Select
VDDQ
Power (+1.5 V / +1.8 V)
(for I/O buffer)
FN
Function Control
VSSQ
Power
(for I/O buffer)
PD
Power Down Control
VREF
Reference Voltage
CLK, CLK
Clock Input
NC
Not Conneted
4 bank operation can be performed using BA2 as A14.
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
x 16
1
2
5
6
VSS
DQ15
DQ0
VDD
B
DQ14
VSSQ
VDDQ
DQ1
C
DQ13
VDDQ
VSSQ
DQ2
D
DQ12
DQ11
DQ4
DQ3
E
DQ10
VSSQ
VDDQ
DQ5
DQ9
VDDQ
VSSQ
DQ6
G
DQ8
VSSQ
VDDQ
DQ7
H
NC
UDQS
LDQS
NC
J
VREF
VSS
VDD
BA2
CLK
CLK
FN
A13
L
A12
PD
CS
NC
M
A11
A9
BA1
BA0
N
A8
A7
A0
A10
P
A5
A6
A2
A1
R
VSS
A4
A3
VDD
A
F
K
Index
NC
NC
3
4
NC
NC
: Depopulated ball
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TC59LM914/06AMG-37,-50
BLOCK DIAGRAM
CLK
CLK
PD
CS
FN
DLL
CLOCK
BUFFER
COMMAND
DECODER
To each block
BANK #7
BANK #6
BANK #5
BANK #4
BANK #3
CONTROL
SIGNAL
GENERATOR
BANK #2
DATA
CONTROL AND LATCH
CIRCUIT
BANK #1
A0~A13
ADDRESS
BUFFER
BA0~BA2
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
REFRESH
COUNTER
BURST
COUNTER
ROW DECODER
BANK #0
MODE
REGISTER
MEMORY
CELL ARRAY
COLUMN DECODER
READ
DATA
BUFFER
WRITE ADDRESS
LATCH/
ADDRESS
COMPARATOR
DQS
DQS
WRITE
DATA
BUFFER
DQ BUFFER
DQ0~DQn
Note: The TC59LM906AMG configuration is 8 Banks of 16384 × 512 × 8 of cell array with the DQ pins numbered DQ0~DQ7.
The TC59LM914AMG configuration is 8 Banks of 16384 × 256 × 16 of cell array with the DQ pins numbered DQ0~DQ15.
TC59LM906AMG has DQS, DQS pin for Differential Data Strobe.
TC59LM914AMG has UDQS and LDQS.
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TC59LM914/06AMG-37,-50
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
−0.3~ 3.3
V
VDD
Power Supply Voltage
VDDQ
Power Supply Voltage (for I/O buffer)
−0.3~VDD+ 0.3
V
VIN
Input Voltage
−0.3~VDD+ 0.3
V
VOUT
Output and I/O pin Voltage
−0.3~VDDQ + 0.3
V
VREF
Input Reference Voltage
−0.3~VDD+ 0.3
V
Topr
Operating Temperature (case)
0~85
°C
Tstg
Storage Temperature
−55~150
°C
Tsolder
Soldering Temperature (10 s)
260
°C
PD
Power Dissipation
2
W
IOUT
Short Circuit Output Current
±50
mA
NOTES
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(TCASE = 0~85°C)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
2.375
2.5
2.625
V
1.4
⎯
1.9
V
NOTES
VDD
Power Supply Voltage
VDDQ
Power Supply Voltage (for I/O buffer)
VREF
Input Reference Voltage
VDDQ/2 × 95%
VDDQ/2
VDDQ/2 × 105%
V
2
VIH (DC)
Input DC High Voltage
VREF + 0.125
⎯
VDDQ + 0.2
V
5
VIL (DC)
Input DC Low Voltage
−0.1
⎯
VREF − 0.125
V
5
VICK (DC)
Differential DC Input Voltage
−0.1
⎯
VDDQ + 0.1
V
10
VID (DC)
Input DC Differential Voltage.
0.4
⎯
VDDQ + 0.2
V
7, 10
VIH (AC)
Input AC High Voltage
VREF + 0.2
⎯
VDDQ + 0.2
V
3, 6
VIL (AC)
Input AC Low Voltage
−0.1
⎯
VREF − 0.2
V
4, 6
VID (AC)
Input AC Differential Voltage
0.5
⎯
VDDQ + 0.2
V
7, 10
VX (AC)
Differential AC Input Cross Point Voltage
VDDQ/2 − 0.125
⎯
VDDQ/2 + 0.125
V
8, 10
VISO (AC)
Differential AC Middle Level
VDDQ/2 − 0.125
⎯
VDDQ/2 + 0.125
V
9, 10
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TC59LM914/06AMG-37,-50
Note:
(1) All voltages referenced to VSS, VSSQ.
(2) VREF is expected to track variations in VDDQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
(3) Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns.
(4) Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns.
(5) VIH (DC) and VIL (DC) are levels to maintain the current logic state.
(6) VIH (AC) and VIL (AC) are levels to change to the new logic state.
(7) VID is magnitude of the difference between VTR input level and VCP input level.
(8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.
(9) VISO means {VICK (VTR) + VICK (VCP)} /2.
(10) Refer to the figure below. VTR is the true input (such as CLK, DQS) level and VCP is the complementary
input (such as CLK , DQS ) level.
CLK
Vx
Vx
Vx
Vx
Vx
VID (AC)
CLK
VICK
VICK
VICK
VISO (min)
VISO (max)
VICK
VSS
|VID (AC)|
0 V Differential
VISO
VSS
(11) In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC) ±
0.04 V.
CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C)
SYMBOL
PARAMETER
MIN
MAX
Delta
UNIT
CIN
Input pin Capacitance
1.5
2.5
0.25
pF
CINC
Clock pin (CLK, CLK ) Capacitance
1.5
2.5
0.25
pF
CI/O
DQ, DQS, UDQS, LDQS, DQS Capacitance
2.5
4
0.5
pF
CNC
NC pin Capacitance
⎯
4
⎯
pF
Note: These parameters are periodically sampled and not 100% tested.
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2004-08-20
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TC59LM914/06AMG-37,-50
RECOMMENDED DC OPERATING CONDITIONS
(VDD=2.5V ± 0.125V, VDDQ=1.4V ~ 1.9V, TCASE = 0~85°C)
MAX
SYMBOL
PARAMETER
UNIT
NOTES
-37
-50
280
240
1, 2
120
100
1, 2
90
80
1, 2
450
350
Operating Current
IDD1S
tCK = min, IRC = min ;
Read/Write command cycling ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
1 bank operation, Burst length = 4 ;
Address change up to 2 times during minimum IRC.
Standby Current
IDD2N
tCK = min, CS = VIH, PD = VIH ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
All banks: inactive state ;
Other input signals are changed one time during 4 × tCK.
Standby (Power Down) Current
IDD2P
tCK = min, CS = VIH, PD = VIL (Power Down) ;
0 V ≤ VIN ≤ VDDQ ;
All banks: inactive state
Write Operating Current (4 Banks)
IDD4W
8 Bank Interleaved continuos burst wirte operation ;
tCK = min, IRC = min
Burst Length = 4, CAS Latency = 5
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Address inputs change once per clock cycle ;
DQ and DQS inputs change twice per clock cycle.
1, 2
mA
Read Operating Current (4 Banks)
IDD4R
8 Bank Interleaved continuos burst wirte operation ;
tCK = min, IRC = min, IOUT = 0mA ;
Burst Length = 4, CAS Latency = 5 ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Address inputs change once per clock cycle ;
Read data change twice per clock cycle.
450
350
1, 2
280
250
1, 2, 3
20
20
2
Burst Auto Refresh Current
IDD5B
Refresh command at every IREFC at interval ;
tCK = min、IREFC = min
CAS Latency = 5
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Address inputs change up to 2 times during minimum IREFC.
DQ and DQS inputs change twice per clock cycle.
Self-Refresh Current
IDD6
Self-Refresh mode
PD = 0.2 V, 0 V ≤ VIN ≤ VDDQ
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
tCK, tRC and IRC.
2. These parameters define the current between VDD and VSS.
3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet tREFI
specification.
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2004-08-20
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TC59LM914/06AMG-37,-50
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD=2.5V ± 0.125V, VDDQ=1.4V ~ 1.9V, TCASE = 0~85°C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
ILI
Input Leakage Current
( 0 V ≤ VIN ≤ VDDQ, all other pins not under test = 0 V)
−5
5
µA
ILO
Output Leakage Current
(Output disabled, 0 V ≤ VOUT ≤ VDDQ)
−5
5
µA
IREF
VREF Current
−5
5
µA
VOH = 1.420V
−5.6
⎯
VOL = 0.280V
5.6
⎯
VOH = 1.420V
−9.8
⎯
IOH (DC)
Normal Output Driver
IOL (DC)
IOH (DC)
Strong Output Driver
IOL (DC)
Output Source DC Current
VOL = 0.280V
9.8
⎯
IOH (DC)
(VDDQ = 1.7V ~ 1.9V)
VOH = 1.420V
−2.8
⎯
VOL = 0.280V
2.8
⎯
VOH = 1.420V
−13.4
⎯
VOL = 0.280V
13.4
⎯
VOH = VDDQ−0.4V
−4
⎯
VOL = 0.4V
4
⎯
VOH = VDDQ−0.4V
−8
⎯
Weak Output Driver
IOL (DC)
IOH (DC)
IOL (DC)
IOH (DC)
Full Strength Output
Driver
Normal Output Driver
IOL (DC)
IOH (DC)
Strong Output Driver
IOL (DC)
Output Source DC Current
VOL = 0.4V
8
⎯
IOH (DC)
(VDDQ = 1.4V ~ 1.6V)
Not defined
⎯
⎯
Not defined
⎯
⎯
VOH = VDDQ−0.4V
−10
⎯
VOL = 0.4V
10
⎯
Weak Output Driver
IOL (DC)
IOH (DC)
IOL (DC)
Full Strength Output
Driver
NOTES
1
mA
1, 2
1
mA
1, 2
Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
2. In case of Full Strength Output Driver, OCD calibration (Off chip Driver impedance adjustment) can be used. The
specification of Full Strength Output Driver defines the default value after power-up.
Rev 1.0
2004-08-20
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TC59LM914/06AMG-37,-50
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
-37
SYMBOL
tRC
tCK
-50
PARAMETER
UNIT
MAX
MIN
MAX
22.5
⎯
27.5
⎯
3
CL = 3
5.5
8.5
6.0
8.5
3
CL = 4
4.5
8.5
5.5
8.5
3
CL = 5
3.75
8.5
5.0
8.5
3
Random Cycle Time
Clock Cycle Time
NOTES
MIN
tRAC
Random Access Time
⎯
22.0
⎯
24
3
tCH
Clock High Time
0.45 × tCK
⎯
0.45 × tCK
⎯
3
tCL
Clock Low Time
0.45 × tCK
⎯
0.45 × tCK
⎯
3
tCKQS
DQS Access Time from CLK
−0.45
0.45
−0.6
0.6
3,8,10
tQSQ
Data Output Skew from DQS
⎯
0.25
⎯
0.35
4
tAC
Data Access Time from CLK
−0.5
0.5
−0.65
0.65
3,8,10
tOH
Data Output Hold Time from CLK
−0.5
0.5
−0.65
0.65
3, 8
tQSPRE
DQS (read) Preamble Pulse Width
0.9 × tCK
1.1 × tCK
0.9 × tCK
1.1 × tCK
3, 8
tHP
CLK half period (minimum of Actual tCH,
tCL)
min(tCH, tCL)
⎯
min(tCH, tCL)
⎯
3
tQSP
DQS (read) Pulse Width
tHP−tQHS
⎯
tHP−tQHS
⎯
4, 8
tQSQV
Data Output Valid Time from DQS
tHP−tQHS
⎯
tHP−tQHS
⎯
4, 8
tQHS
DQ, DQS Hold Skew factor
⎯
0.055 × tCK
+0.17
⎯
0.055 × tCK
+0.17
tDQSS
DQS (write) Low to High Setup Time
0.75 × tCK
1.25 × tCK
0.75 × tCK
1.25 × tCK
tDSPRE
DQS (write) Preamble Pulse Width
0.25 × tCK
⎯
0.25 × tCK
⎯
4
tDSPRES
DQS First Input Setup Time
0
⎯
0
⎯
3
tDSPREH
DQS First Low Input Hold Time
0.25 × tCK
⎯
0.25 × tCK
⎯
3
tDSP
DQS High or Low Input Pulse Width
0.35 × tCK
0.65 × tCK
0.35 × tCK
0.65 × tCK
4
CL = 3
0.75
⎯
1.0
⎯
3, 4
tDSS
DQS Input Falling Edge to
Clock Setup Time
CL = 4
0.75
⎯
1.0
⎯
3, 4
CL = 5
0.75
⎯
1.0
⎯
3, 4
0.55
⎯
0.75
⎯
3, 4
0.4 × tCK
⎯
0.4 × tCK
⎯
4
CL = 3
0.75
⎯
1.0
⎯
3, 4
CL = 4
0.75
⎯
1.0
⎯
3, 4
CL = 5
0.75
⎯
1.0
⎯
3, 4
tDSH
DQS Input Falling Edge Hold Time from
CLK
tDSPST
DQS (write) Postamble Pulse Width
tDSPSTH
DQS (write) Postamble Hold
Time
ns
3
tDSSK
UDQS – LDQS Skew (×16)
−0.5× tCK
0.5× tCK
−0.5× tCK
0.5× tCK
tDS
Data Input Setup Time from DQS
0.35
⎯
0.45
⎯
4
tDH
Data Input Hold Time from DQS
0.35
⎯
0.45
⎯
4
tIS
Command/Address Input Setup Time
0.5
⎯
0.7
⎯
3
tIH
Command/Address Input Hold Time
0.5
⎯
0.7
⎯
3
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2004-08-20
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TC59LM914/06AMG-37,-50
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-37
SYMBOL
-50
PARAMETER
UNIT
MIN
MAX
MIN
MAX
NOTES
tLZ
Data-out Low Impedance Time from CLK
−0.5
⎯
−0.65
⎯
3,6,8
tHZ
Data-out High Impedance Time from CLK
⎯
0.5
⎯
0.65
3,7,8
tQSLZ
DQS-out Low Impedance Time from CLK
−0.5
⎯
−0.65
⎯
3,6,8
tQSHZ
DQS-out High Impedance Time from CLK
−0.5
0.5
−0.65
0.65
3,7,8
tQPDH
Last output to PD High Hold Time
0
⎯
0
⎯
tPDEX
Power Down Exit Time
0.6
⎯
0.8
⎯
tT
Input Transition Time
0.1
1
0.1
1
tFPDL
PD Low Input Window for Self-Refresh
Entry
−0.5 × tCK
5
−0.5 × tCK
5
tOIT
OCD drive mode output delay time
0
12
0
12
tREFI
Auto-Refresh Average Interval
0.4
3.9
0.4
3.9
tPAUSE
Pause Time after Power-up
200
⎯
200
⎯
Random Read/Write Cycle
Time
(applicable to same bank)
CL = 3
5
⎯
5
⎯
IRC
CL = 4
5
⎯
5
⎯
CL = 5
6
⎯
6
⎯
1
1
1
1
CL = 3
4
⎯
4
⎯
CL = 4
4
⎯
4
⎯
CL = 5
5
⎯
5
⎯
2
⎯
2
⎯
BL = 2
2
⎯
2
⎯
BL = 4
3
⎯
3
⎯
1
⎯
1
⎯
CL = 3
5
⎯
5
⎯
CL = 4
5
⎯
5
⎯
CL = 5
6
⎯
6
⎯
IRCD
RDA/WRA to LAL Command Input Delay
(applicable to same bank)
IRAS
LAL to RDA/WRA Command
Input Delay
(applicable to same bank)
IRBD
Random Bank Access Delay
(applicable to other bank)
IRWD
LAL following RDA to WRA
Delay
(applicable to other bank)
IWRD
LAL following WRA to RDA Delay
(applicable to other bank)
IRSC
Mode Register Set Cycle
Time
IPD
PD Low to Inactive State of Input Buffer
⎯
1
⎯
1
IPDA
PD High to Active State of Input Buffer
⎯
1
⎯
1
CL = 3
15
⎯
15
⎯
IPDV
Power down mode valid from
REF command
IREFC
Auto-Refresh Cycle Time
CL = 4
18
⎯
18
⎯
CL = 5
22
⎯
22
⎯
CL = 3
15
⎯
15
⎯
CL = 4
18
⎯
18
⎯
CL = 5
22
⎯
22
⎯
IREFC
⎯
IREFC
⎯
200
⎯
200
⎯
ICKD
REF Command to Clock Input Disable at
Self-Refresh Entry
ILOCK
DLL Lock-on Time (applicable to RDA
command)
ns
3
3
µs
5
cycle
Rev 1.0
2004-08-20
10/59
TC59LM914/06AMG-37,-50
AC TEST CONDITIONS
SYMBOL
PARAMETER
VALUE
UNIT
VIH (min)
Input High Voltage (minimum)
VREF + 0.2
V
VIL (max)
Input Low Voltage (maximum)
VREF − 0.2
V
VREF
Input Reference Voltage
VDDQ/2
V
VTT
Termination Voltage
VREF
V
VSWING
Input Signal Peak to Peak Swing
0.7
V
Vr
Differential Clock Input Reference Level
VX (AC)
V
VID (AC)
Input Differential Voltage
1.0
V
SLEW
Input Signal Minimum Slew Rate
2.5
V/ns
VOTR
Output Timing Measurement Reference Voltage
VDDQ/2
V
NOTES
9
VDDQ
VIH min (AC)
VREF
VSWING
VTT
25 Ω
VIL max (AC)
VSS
∆T
∆T
Output
Measurement point
SLEW = (VIH min (AC) − VIL max (AC))/∆T
AC Test Load
Note:
(1)
Transition times are measured between VIH min (DC) and VIL max (DC).
Transition (rise and fall) of input signals have a fixed slope.
(2)
If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is
rounded up to the nearest decimal place.
(i.e., tDQSS = 0.75 × tCK, tCK = 5 ns, 0.75 × 5 ns = 3.75 ns is rounded up to 3.8 ns.)
(3)
These parameters are measured from the differential clock (CLK and CLK ) AC cross point.
(4)
These parameters are measured from signal transition point of DQS crossing VREF level.
In case of DQS enable mode, these parameters are measured from the crossing point of DQS and DQS .
(5)
The tREFI (max) applies to equally distributed refresh method.
The tREFI (min) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)
is to 8 times in the maximum.
(6)
Low Impedance State is specified at VDDQ/2 ± 0.2 V from steady state.
(7)
High Impedance State is specified where output buffer is no longer driven.
(8)
These parameters depend on the clock jitter. These parameters are measured at stable clock.
(9)
Output timing is measured by using Normal driver strength at VDDQ = 1.7V∼1.9V.
Output timing is measured by using Strong driver strength at VDDQ = 1.4V∼1.6V.
(10)
These parameters are measured at tCK = minimum∼6.0ns. When tCK is longer than 6.0ns, these parameters
are specified as below for all Speed version
tCKQS (MIN/MAX) = −0.6ns / 0.6ns, tAC (MIN/MAX) = −0.65ns / 0.65ns
Rev 1.0
2004-08-20
11/59
TC59LM914/06AMG-37,-50
POWER UP SEQUENCE
(1)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
(2)
Apply VDD before or at the same time as VDDQ.
(3)
Apply VDDQ before or at the same time as VREF.
(4)
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
(5)
After stable power and clock, apply DESL and take PD =H.
(6)
Issue EMRS to enable DLL and to define driver strength with OCD calibration mode exit command
(A7∼A9=0). (Note: 1, 2)
(7)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
(8)
Issue two or more Auto-Refresh commands (Note: 1).
(9)
Ready for normal operation after 200 clocks from Extended Mode Register programming.
(10)
If OCD calibration (Off Chip Driver impedance adjustment) is used, execute OCD calibration sequence.
Notes:
(1)
Sequence 6, 7 and 8 can be issued in random order.
(2)
Set DQS mode for TC59LM906AMG.
(3)
L = Logic Low, H = Logic High
(4)
All DQs output level are high impedance state during power up sequence.
2.5V(TYP)
VDD
1.5V or 1.8V(TYP)
VDDQ
1/2 VDDQ(TYP)
VREF
CLK
CLK
tPDEX
lPDA
200us(min)
lRSC
lRSC
lREFC
lREFC
PD
200clock cycle(min)
Command
DESL
RDA MRS DESL
op-code
RDA MRS
DESL WRA REF
DESL
WRA REF
DESL
op-code
Address
EMRS
MRS
DQ
Hi-Z
DQS
Hi-Z
DQS
EMRS
MRS
Auto Refresh cycle
Normal Operation
Rev 1.0
2004-08-20
12/59
TC59LM914/06AMG-37,-50
TIMING DIAGRAMS
Input Timing
Command and Address
tCK
tCK
tCH
tCL
CLK
CLK
tIS
CS
tIH
tIS
1st
tIS
FN
2nd
tIS
tIH
1st
tIS
A0~A13
BA0∼BA2
tIH
tIH
2nd
tIH
tIH
tIS
UA, BA
LA
Data
• TC59LM906AMG
DQS enable mode
DQS
DQS
tDS tDH
tDS tDH
DQ (input)
Data
• TC59LM906AMG
• TC59LM914AMG
DQS disable mode
DQS
tDS tDH
tDS tDH
DQ (input)
Refer to the Command Truth Table.
Timing of the CLK, CLK
tCH
tCL
VIH
VIH (AC)
VIL (AC)
VIL
CLK
CLK
tT
tT
tCK
CLK
VIH
CLK
VIL
VID (AC)
VX
VX
VX
Rev 1.0
2004-08-20
13/59
TC59LM914/06AMG-37,-50
Read Timing (Burst Length = 4)
tCH
tCL
tCK
CLK
CLK
tIS tIH
LAL (after RDA)
Input
(control &
addresses)
DESL
tCKQS
tQSLZ
tCKQS
CAS latency = 3
DQS/ DQS
(output)
tQSP tQSP
tQSHZ
tQSPRE
Hi-Z
Preamble
Postamble
tQSQV
tLZ
tQSQ
DQ
(output)
tCKQS
tQSQ
Hi-Z
Q0
tAC
tQSQ
tHZ
tQSQV
Q1
Q2
tAC
Q3
tAC
tOH
tCKQS
tQSLZ
CAS latency = 4
DQS/ DQS
(output)
tCKQS
tQSHZ
tQSP tQSP
tQSPRE
Hi-Z
Preamble
Postamble
tLZ
tQSQV
tQSQ
DQ
(output)
tCKQS
Hi-Z
tQSQ
Q0
tAC
tQSQ
tQSQV
Q1
tAC
Q2
tHZ
Q3
tAC
tOH
tCKQS
tQSLZ
CAS latency = 5
DQS/ DQS
(output)
tCKQS
tQSPRE
tQSHZ
Hi-Z
Preamble
Postamble
tLZ
tQSQ
DQ
(output)
tCKQS
tQSP tQSP
Hi-Z
tQSQ
Q0
tAC
Note:
tQSQ
tQSQV
tQSQV
Q1
tAC
Q2
tAC
tHZ
Q3
tOH
TC59LM914AMG doesn’t have DQS .
The correspondence of LDQS, UDQS to DQ. (TC59LM914AMG)
LDQS
UDQS
DQ0∼DQ7
DQ8∼DQ15
DQS is Hi-Z in DQS disable mode.
DQS mode is chosen by EMRS. (TC59LM906AMG)
When DQS is enable, the condition of DQS is changed from Hi-Z to “High at Preamble and the
condition of DQS is changed from “High” to Hi-Z at Postamble.
Rev 1.0
2004-08-20
14/59
TC59LM914/06AMG-37,-50
Write Timing (Burst Length = 4)
tCH
tCL
tCK
CLK
CLK
tIS tIH
LAL (after WRA)
Input
(control &
addresses)
DESL
tDQSS
tDSPRES
tDSPSTH
tDSS
tDSPREH tDSP tDSP tDSP tDSPST
CAS latency = 3
DQS/ DQS
(input)
tDSS
Preamble
tDSPRE
tDS
tDS
tDS
tDH
tDH
DQ
(input)
Postamble
D0
D1
tDH
D2
D3
tDQSS
tDSS
tDSPRES
CAS latency = 4
tDSPSTH
tDSS
tDSPREH tDSP
tDSP tDSP tDSPST
DQS/ DQS
(input)
Preamble
tDSPRE
Postamble
tDS
tDS
tDH
DQ
(input)
D0
tDQS
tDS
tDH
D1
tDH
D3
D2
tDQS
tDSS
tDSPRES
tDSS
tDSPSTH
tDSPREH tDSP tDSP tDSP tDSPST
CAS latency = 5
DQS/ DQS
(input)
Preamble
tDSPRE
Postamble
tDS
tDS
tDH
DQ
(input)
D0
tDQSS
Note:
tDS
tDH
D1
D2
tDH
D3
tDQSS
TC59LM914AMG doesn’t have DQS .
The correspondence of LDQS, UDQS to DQ. (TC59LM914AMG)
LDQS
DQ0∼DQ7
UDQS
DQ8∼DQ15
DQS is ignored in DQS disable mode.
DQS mode is chosen by EMRS. (TC59LM906AMG)
Rev 1.0
2004-08-20
15/59
TC59LM914/06AMG-37,-50
tREFI, tPAUSE, Ixxxx Timing
CLK
CLK
tREFI, tPAUSE, IXXXX
tIS tIH
tIS tIH
Input
(control &
addresses)
Command
Command
Note: “IXXXX” means “IRC”, “IRCD”, “IRAS”, etc.
Rev 1.0
2004-08-20
16/59
TC59LM914/06AMG-37,-50
Write Timing (x16 device) (Burst Length =4)
CLK
CLK
Input
(control &
addresses)
WRA
LAL
DESL
tDSSK tDSSK tDSSK tDSSK
CAS latency = 3
LDQS
Preamble
tDS
tDS
D0
DQ0~DQ7
tDH
tDH
tDH
Postamble
tDS
tDS
D1
D2
tDH
D3
UDQS
Preamble
Postamble
tDS
tDS
tDH
DQ8~DQ15
tDS
tDH
tDH
D0
tDS
D1
tDH
D2
D3
tDSSK tDSSK tDSSK tDSSK
CAS latency = 4
LDQS
Preamble
tDS
tDH
Postamble
tDS
tDH
D0
DQ0~DQ7
tDS
tDS
tDH
tDH
D1
D2
D3
UDQS
Preamble
tDS
tDS
tDH
DQ8~DQ15
tDS
tDH
D0
D1
Postamble
tDS
tDH
D2
tDH
D3
tDSSK tDSSK tDSSK tDSSK
CAS latency = 5
LDQS
Preamble
tDS
tDH
tDH
DQ0~DQ7
tDS
tDS
D0
Postamble
tDS
tDH
tDH
D1
D2
D3
UDQS
Preamble
tDS
tDS
tDH
tDH
DQ8~DQ15
tDS
D0
D1
tDS
tDH
D2
Postamble
tDH
D3
Rev 1.0
2004-08-20
17/59
TC59LM914/06AMG-37,-50
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL
FUNCTION
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
DESL
Device Deselect
H
×
×
×
×
×
×
RDA
Read with Auto-close
L
H
BA
UA
UA
UA
UA
WRA
Write with Auto-close
L
L
BA
UA
UA
UA
UA
• The Second Command (The next clock of RDA or WRA command)
SYMBOL
FUNCTION
CS
FN
BA1~
BA0
BA2
A13
A12~
A11
A10~A
9
A8
A7
A6~A0
LAL
Lower Address Latch (x16)
H
×
×
V
V
V
×
×
LA
LA
LAL
Lower Address Latch (x8)
H
×
×
V
V
×
×
LA
LA
LA
REF
Auto-Refresh
L
×
×
×
×
×
×
×
×
×
MRS
Mode Register Set
L
×
V
L
L
L
L
L
V
V
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL)
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
RDA (1st)
L
H
BA
UA
UA
UA
UA
LAL (2nd)
H
×
×
×
LA
LA
LA
NOTES
5
Note 5 : For x16 device, A8 is “X” (either L or H).
Write Command Table
• TC59LM914AMG
COMMAND(SYMBOL)
CS
FN
BA1~
BA0
BA2
A13
A12
A11
A10~
A9
A8
A7
A6~A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
×
×
LVW0
LVW1
UVW0
UVW1
×
×
LA
LA
COMMAND(SYMBOL)
CS
FN
BA1~
BA0
BA2
A13
A12
A11
A10~
A9
A8
A7
A6~A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
×
×
VW0
VW1
×
×
×
LA
LA
LA
• TC59LM906AMG
Notes: 6. BA2, A13 ∼ A11 are used for Variable Write Length (VW) control at Write Operation.
Rev 1.0
2004-08-20
18/59
TC59LM914/06AMG-37,-50
FUNCTION TRUTH TABLE (continued)
VW Truth Table
Burst Length
Function
VW0
VW1
Write All Words
L
×
Write First One Word
H
×
Reserved
L
L
Write All Words
H
L
Write First Two Words
L
H
Write First One Word
H
H
BL=2
BL=4
Note 7 : For x16 device, LVW0 and LVW1 control DQ0~DQ7.
UVW0 and UVW1 control DQ8~DQ15.
Mode Register Set Command Table
COMMAND (SYMBOL)
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
NOTES
RDA (1st)
L
H
×
×
×
×
×
MRS (2nd)
L
×
V
V
V
V
V
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
8
Notes: 8. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
COMMAND
(SYMBOL)
CURRENT
STATE
Active
WRA (1st)
Auto-Refresh
REF (2nd)
FUNCTION
PD
n−1
n
Standby
H
H
L
L
×
×
×
×
×
Active
H
H
L
×
×
×
×
×
×
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
NOTES
Self-Refresh Command Table
COMMAND
(SYMBOL)
CURRENT
STATE
Active
WRA (1st)
Self-Refresh Entry
FUNCTION
PD
NOTES
n−1
n
Standby
H
H
L
L
×
×
×
×
×
REF (2nd)
Active
H
L
L
×
×
×
×
×
×
⎯
Self-Refresh
L
L
×
×
×
×
×
×
×
SELFX
Self-Refresh
L
H
H
×
×
×
×
×
×
11
COMMAND
(SYMBOL)
CURRENT
STATE
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
NOTES
PDEN
10
Self-Refresh Continue
Self-Refresh Exit
9, 10
Power Down Table
FUNCTION
Power Down Entry
Power Down Continue
Power Down Exit
Notes: 9.
10.
PD
n−1
n
Standby
H
L
H
×
×
×
×
×
×
⎯
Power Down
L
L
×
×
×
×
×
×
×
PDEX
Power Down
L
H
H
×
×
×
×
×
×
11
PD has to be brought to Low within tFPDL from REF command.
PD should be brought to Low after DQ’s state turned high impedance.
11. When PD is brought to High from Low, this function is executed asynchronously.
Rev 1.0
2004-08-20
19/59
TC59LM914/06AMG-37,-50
FUNCTION TRUTH TABLE (continued)
CURRENT STATE
PD
n−1 n
CS
FN
ADDRESS
COMMAND
ACTION
NOTES
Idle
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
⎯
⎯
Row Active for Read
H
H
H
H
L
H
H
L
L
×
H
L
H
L
×
×
×
×
×
×
LA
Op-code
×
×
×
LAL
MRS/EMRS
PDEN
MRS/EMRS
⎯
Row Active for Write
H
H
H
H
L
H
H
L
L
×
H
L
H
L
×
×
×
×
×
×
LA
×
×
×
×
LAL
REF
PDEN
REF (self)
⎯
Read
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
⎯
⎯
H
H
H
×
×
DESL
H
H
H
H
L
H
H
L
L
×
L
L
H
L
×
H
L
×
×
×
BA, UA
BA, UA
×
×
×
RDA
WRA
PDEN
⎯
⎯
Data Write & Continue Burst Write to
End
Illegal
Illegal
Illegal
Illegal
Invalid
Auto-Refreshing
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
⎯
⎯
NOP → Idle after IREFC
Illegal
Illegal
Self-Refresh Entry
Illegal
Refer to Self-Refreshing State
Mode Register
Accessing
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
⎯
⎯
NOP → Idle after IRSC
Illegal
Illegal
Illegal
Illegal
Invalid
H
L
×
L
×
×
×
×
×
×
⎯
⎯
L
H
H
×
×
PDEX
L
H
L
×
×
⎯
Invalid
Maintain Power Down Mode
Exit Power Down Mode → Idle after
tPDEX
Illegal
H
L
L
L
×
L
H
H
×
×
H
L
×
×
×
×
×
×
×
×
⎯
⎯
SELFX
⎯
Invalid
Maintain Self-Refresh
Exit Self-Refresh → Idle after IREFC
Illegal
Write
Power Down
Self-Refreshing
NOP
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
Refer to Power Down State
12
Begin Read
Access to Mode Register
Illegal
Illegal
Invalid
Begin Write
Auto-Refresh
Illegal
Self-Refresh Entry
Invalid
Continue Burst Read to End
Illegal
Illegal
Illegal
Illegal
Invalid
13
13
13
13
14
Notes: 12. Illegal if any bank is not idle.
13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
14. Illegal if tFPDL is not satisfied.
Rev 1.0
2004-08-20
20/59
TC59LM914/06AMG-37,-50
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
*1
ADDRESS
*1
BA1
BA0
0
0
Register
*3
BA2, A13~A8
A7
0
A6~A4
A3
A2~A0
CL
BT
BL
TE
A7
TEST MODE (TE)
A3
BURST TYPE (BT)
0
Regular (default)
0
Sequential
1
Test Mode Entry
1
Interleave
A6
A5
A4
0
0
×
Reserved
0
1
0
Reserved
0
1
1
1
0
0
1
0
CAS LATENCY (CL)
1
A2
A1
A0
0
0
0
0
0
1
2
3
0
1
0
4
4
0
1
1
*2
*2
5
1
1
1
0
Reserved
1
1
1
Reserved
×
BURST LENGTH (BL)
Reserved
Reserved
×
*2
*2
*2
*2
Extended Mode Register (Notes: 4)
*4
ADDRESS
*4
BA1
BA0
0
1
Register
BA2,
A13~A12
*6
A11
0
0
*7
A10
DQS
A9~A7
A6
A5~A2
A1
OCD
DIC
0
DIC
A0
*5
DS
A6
A1
OUTPUT DRIVE IMPEDANCE CONTROL
(DIC)
OCD Calibration mode exit
0
0
Normal Output Driver
1
Drive (1)
0
1
Strong Output Driver
1
0
Drive (0)
1
0
Weak Output Driver
1
0
0
Adjust mode
1
1
Full strength Output Driver
1
1
1
OCD Calibration default
A9
A8
A7
0
0
0
0
0
0
Driver Impedance Adjustment
A10
DQS Enable
A0
DLL SWITCH (DS)
0
Disable
0
DLL Enable
1
Enable
1
DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
6. A11 in Extended Mode Register must be set to “0”.
7. TC59LM914AMG, A10 in Extended Mode Register is ignored. DQS is available only TC59LM906AMG.
Rev 1.0
2004-08-20
21/59
TC59LM914/06AMG-37,-50
STATE DIAGRAM
SELFREFRESH
POWER
DOWN
SELFX
( PD = H)
PDEX
( PD = H)
PD = L
PDEN
( PD = L)
STANDBY
(IDLE)
PD = H
AUTOREFRESH
MODE
REGISTER
WRA
RDA
REF
MRS
ACTIVE
(RESTORE)
ACTIVE
LAL
LAL
WRITE
(BUFFER)
READ
Command input
Automatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
Rev 1.0
2004-08-20
22/59
TC59LM914/06AMG-37,-50
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
Command
RDA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
IRAS = 4 cycles
LA
RDA
LAL
IRCD=1 cycle
UA
IRC = 5 cycles
DESL
RDA
IRAS = 4 cycles
LA
IRCD=1 cycle
UA
#0
LAL
DESL
RDA
IRAS = 4 cycles
LA
UA
#0
#0
BL = 2
DQS/ DQS
(output)
Hi-Z
DQ
(output)
Hi-Z
CL = 3
CL = 3
Q0 Q1
CL = 3
Q0 Q1
Q0 Q1
BL = 4
DQS/ DQS
(output)
Hi-Z
CL = 3
DQ
(output)
Hi-Z
CL = 3
Q0 Q1 Q2 Q3
CL = 3
Q0 Q1 Q2 Q3
Q0 Q1 Q2
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
23/59
TC59LM914/06AMG-37,-50
SINGLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
Command
RDA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
IRAS = 4 cycles
LA
RDA
LAL
IRCD=1 cycle
UA
DESL
IRAS = 4 cycles
LA
IRC = 5 cycles
RDA
DESL
IRCD=1 cycle
UA
#0
LAL
RDA
IRAS = 4 cycles
LA
UA
#0
#0
BL = 2
DQS/ DQS
(output)
Hi-Z
DQ
(output)
Hi-Z
CL = 4
CL = 4
Q0 Q1
CL = 4
Q0 Q1
Q0
BL = 4
DQS/ DQS
(output)
Hi-Z
CL = 4
DQ
(output)
Hi-Z
CL = 4
Q0 Q1 Q2 Q3
CL = 4
Q0 Q1 Q2 Q3
Q0
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
24/59
TC59LM914/06AMG-37,-50
SINGLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RDA
LAL
14
15
CLK
CLK
IRC = 6 cycles
IRC = 6 cycles
Command
RDA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
IRAS = 5 cycles
LA
RDA
LAL
IRCD=1 cycle
UA
DESL
IRAS = 5 cycles
LA
IRCD=1 cycle
UA
#0
DESL
LA
#0
BL = 2
DQS/ DQS
(output)
Hi-Z
CL = 5
DQ
(output)
Hi-Z
CL = 5
Q0 Q1
Q0 Q1
BL = 4
DQS/ DQS
(output)
Hi-Z
CL = 5
DQ
(output)
Hi-Z
CL = 5
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
25/59
TC59LM914/06AMG-37,-50
SINGLE BANK WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
Command
WRA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
WRA
IRAS = 4 cycles
LA
LAL
IRCD=1 cycle
UA
DESL
IRC = 5 cycles
WRA
IRAS = 4 cycles
LA
IRCD=1 cycle
UA
#0
LAL
DESL
WRA
IRAS = 4 cycles
LA
UA
#0
#0
BL = 2
DQS/ DQS
(input)
WL = 2
DQ
(input)
WL = 2
D0 D1
WL = 2
D0 D1
D0 D1
BL = 4
DQS/ DQS
(input)
WL = 2
DQ
(input)
WL = 2
D0 D1 D2 D3
WL = 2
D0 D1 D2 D3
D0 D1 D2 D3
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
26/59
TC59LM914/06AMG-37,-50
SINGLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
Command
WRA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
WRA
IRAS = 4 cycles
LAL
IRCD=1 cycle
LA
UA
IRC = 5 cycles
DESL
WRA
IRAS = 4 cycles
LAL
IRCD=1 cycle
LA
UA
#0
DESL
WRA
IRAS = 4 cycles
LA
UA
#0
#0
BL = 2
DQS/ DQS
(input)
WL = 3
DQ
(input)
WL = 3
D0 D1
WL = 3
D0 D1
D0 D1
BL = 4
DQS/ DQS
(input)
WL = 3
DQ
(input)
WL = 3
D0 D1 D2 D3
WL = 3
D0 D1 D2 D3
D0 D1 D2 D3
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
27/59
TC59LM914/06AMG-37,-50
SINGLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
6
5
7
8
9
10
11
12
13
WRA
LAL
14
15
CLK
CLK
IRC = 6 cycles
IRC = 6 cycles
Command
WRA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
WRA
IRAS = 5 cycles
LAL
IRCD=1 cycle
LA
UA
DESL
IRAS = 5 cycles
DESL
IRCD=1 cycle
LA
UA
#0
LA
#0
BL = 2
DQS/ DQS
(input)
WL = 4
DQ
(input)
WL = 4
D0 D1
D0 D1
BL = 4
DQS/ DQS
(input)
WL = 4
DQ
(input)
WL = 4
D0 D1 D2 D3
D0 D1 D2 D3
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
28/59
TC59LM914/06AMG-37,-50
SINGLE BANK READ-WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
RDA
LAL
Address
UA
LA
Bank Add.
#0
Command
DESL
WRA
LAL
UA
LA
DESL
IRC = 5 cycles
RDA
LAL
UA
LA
#0
DESL
WRA
UA
#0
#0
BL = 2
DQS
DQS
Hi-Z
Hi-Z
CL = 3
DQ
Hi-Z
WL = 2
Q0 Q1
CL = 3
D0 D1
Q0 Q1
BL = 4
Hi-Z
DQS
DQS
Hi-Z
CL = 3
DQ
Hi-Z
WL = 2
Q0 Q1 Q2 Q3
CL = 3
D0 D1 D2 D3
Q0 Q1 Q2
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
29/59
TC59LM914/06AMG-37,-50
SINGLE BANK READ-WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
Command
RDA
LAL
Address
UA
LA
Bank Add.
#0
DESL
WRA
LAL
UA
LA
DESL
IRC = 5 cycles
RDA
LAL
UA
LA
#0
DESL
WRA
UA
#0
#0
BL = 2
DQS
Hi-Z
Hi-Z
DQS
CL = 4
DQ
Hi-Z
WL = 3
Q0 Q1
CL = 4
D0 D1
Q0
BL = 4
DQS
Hi-Z
Hi-Z
DQS
CL = 4
DQ
Hi-Z
WL = 3
Q0 Q1 Q2 Q3
CL = 4
D0 D1 D2 D3
Q0
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
30/59
TC59LM914/06AMG-37,-50
SINGLE BANK READ-WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RDA
LAL
UA
LA
14
15
CLK
CLK
IRC = 6 cycles
IRC = 6 cycles
Command
RDA
LAL
Address
UA
LA
Bank Add.
#0
DESL
WRA
LAL
UA
LA
DESL
#0
DESL
#0
BL = 2
DQS
DQS
Hi-Z
Hi-Z
CL = 5
DQ
Hi-Z
WL = 4
Q0 Q1
D0 D1
BL = 4
DQS
DQS
Hi-Z
Hi-Z
WL = 4
CL = 5
DQ
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
31/59
TC59LM914/06AMG-37,-50
MULTIPLE BANK READ TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRBD = 2 cycles
Command
Address
Bank Add.
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
RDA
LAL
RDA
LAL
UA
LA
UA
LA
Bank
"a"
DESL RDA
UA
Bank
"b"
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"b"
Bank
"a"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
BL = 2
DQS/ DQS
(output)
Hi-Z
CL = 3
CL = 3
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
Qd0Qd1
BL = 4
DQS/ DQS
(output)
Hi-Z
CL = 3
CL = 3
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2 Qc3Qd0Qd1
Note: lRC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
32/59
TC59LM914/06AMG-37,-50
MULTIPLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRBD = 2 cycles
Command
Address
Bank Add.
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
RDA
LAL
RDA
LAL
UA
LA
UA
LA
Bank
"a"
DESL RDA
Bank
"b"
UA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"b"
Bank
"a"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
BL = 2
DQS/ DQS
(output)
Hi-Z
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
BL = 4
DQS/ DQS
(output)
Hi-Z
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
Note: lRC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
33/59
TC59LM914/06AMG-37,-50
MULTIPLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
RDA
LAL
RDA
LAL
UA
LA
UA
LA
Bank
"a"
DESL
Bank
"b"
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 6 cycles
IRC (Bank"b") = 6 cycles
BL = 2
DQS/ DQS
(output)
Hi-Z
CL = 5
CL = 5
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
BL = 4
DQS/ DQS
(output)
Hi-Z
CL = 5
CL = 5
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
Note: lRC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
34/59
TC59LM914/06AMG-37,-50
MULTIPLE BANK WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
WRA
LAL
WRA
LAL
UA
LA
UA
LA
Bank
"a"
DESL WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
UA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
BL = 2
DQS/ DQS
(input)
WL = 2
WL = 2
DQ
(input)
Da0 Da1
Db0Db1
Da0Da1
Db0Db1
Dc0 Dc1
Dd0Dd1
BL = 4
DQS/ DQS
(input)
WL = 2
WL = 2
DQ
(input)
Da0 Da1Da2 Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0Dd1Dd2Dd3
Note: lRC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
35/59
TC59LM914/06AMG-37,-50
MULTIPLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
WRA
LAL
WRA
LAL
UA
LA
UA
LA
Bank
"a"
DESL WRA
UA
Bank
"b"
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
BL = 2
DQS/ DQS
(input)
WL = 3
WL = 3
DQ
(input)
Da0 Da1
Db0Db1
Da0Da1
Db0 Db1
Dc0 Dc1
Dd0Dd1
BL = 4
DQS/ DQS
(input)
WL = 3
WL = 3
DQ
(input)
Da0 Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0 Db1Db2 Db3 Dc0 Dc1 Dc2Dc3 Dd0Dd1
Note: lRC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
36/59
TC59LM914/06AMG-37,-50
MULTIPLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
WRA
LAL
WRA
LAL
UA
LA
UA
LA
Bank
"a"
DESL
Bank
"b"
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 6 cycles
IRC (Bank"b") = 6 cycles
BL = 2
DQS/ DQS
(input)
WL = 4
WL = 4
DQ
(input)
Da0Da1
Db0Db1
Da0 Da1
Db0 Db1
Dc0Dc1
BL = 4
DQS DQS
(input)
WL = 4
WL = 4
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0 Da1 Da2 Da3 Db0 Db1Db2Db3Dc0Dc1
Note: lRC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
37/59
TC59LM914/06AMG-37,-50
MULTIPLE BANK READ-WRITE TIMING (BL = 2)
0
1
2
3
4
5
6
7
LAL
RDA
8
9
10
11
12
13
LAL
RDA
LAL
LA
UA
LA
14
15
CLK
CLK
Command
IRBD = 2 cycles
cycle
WRA IWRD
LAL= 1 RDA
IWRD = 1 cycle
Address
Bank Add.
UA
Bank
"a"
LA
UA
LAL
DESL WRA
IRWD = 2 cycles IWRD = 1 cycle
LA
Bank
"b"
UA
LA
Bank
"a"
UA
IRWDDESL
= 2 cycles
LAL
WRA
DESL WRA
IRWD = 2 cycles
LA
UA
Bank
"d"
Bank
"a"
UA
Bank
"b"
Bank
"c"
IRC (Bank"a")
IRC (Bank"b")
CL = 3
DQS
DQS
Hi-Z
Hi-Z
CL = 3
WL = 2
DQ
CL = 4
DQS
DQS
Hi-Z
Da0 Da1
Qb0Qb1
Dc0Dc1
Qd0Qd1
Da0 Da1
Hi-Z
Hi-Z
CL = 4
WL = 3
DQ
CL = 5
DQS
DQS
Hi-Z
Da0 Da1
Qb0Qb1
Dc0 Dc1
Qd0Qd1
Da0Da1
Hi-Z
Hi-Z
CL = 5
WL = 4
DQ
Hi-Z
Da0Da1
Qb0Qb1
Dc0Dc1
Qd0Qd1
Da0Da1
Note: lRC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20
38/59
TC59LM914/06AMG-37,-50
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
0
1
2
3
4
5
6
7
WRA
LAL
8
9
10
11
12
13
14
15
WRA
LAL
RDA
LAL
CLK
CLK
Command
IRBD = 2 cycles
cycle
WRA IWRD
LAL= 1 RDA
LAL
IWRD = 1 cycle
Address
Bank Add.
UA
Bank
"a"
LA
DESL
IRWD = 3 cycles
UA
IWRD = 1 cycle
LA
UA
Bank
"b"
IRWD LAL
= 2 cyclesDESL
RDA
LA
Bank
"c"
UA
IRWD = 3 cycles
IWRD = 1 cycle
LA
UA
Bank
"d"
Bank
"a"
LA
UA
LA
Bank
"b"
IRC (Bank"a")
IRC (Bank"b")
CL = 3
DQS
Hi-Z
DQS
Hi-Z
CL = 3
WL = 2
DQ
CL = 4
DQS
DQS
Hi-Z
Da0 Da1 Da2 Da3
Qb0Qb1Qb2Qb3
Dc0Dc1 Dc2Dc3
Qd0Qd1Qd2Qd3
Hi-Z
Hi-Z
CL = 4
WL = 3
DQ
CL = 5
DQS
DQS
Hi-Z
Da0 Da1Da2Da3
Qb0Qb1Qb2Qb3
Dc0 Dc1 Dc2 Dc3
Qd0Qd1Qd2Qd3
Hi-Z
Hi-Z
CL = 5
WL = 4
DQ
Hi-Z
Da0Da1Da2Da3
Qb0Qb1Qb2Qb3
Dc0 Dc1 Dc2 Dc3
Qd0Qd1Qd2Qd3
Note: lRC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
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TC59LM914/06AMG-37,-50
WRITE with VARIAVLE WRITE LENGTH (VW) CONTROL (CL = 4)
0
1
2
3
4
5
6
WRA
LAL
UA
LA=#1
VW=1
7
8
9
10
11
12
13
14
15
CLK
CLK
BL = 2, SEQUENTIAL MODE
Command
Address
WRA
LAL
UA
LA=#3
VW=All
DESL
VW0 = Low
VW1 = don't care
Bank Add.
Bank
"a"
DESL
VW0 = High
VW1 = don't care
Bank
"a"
DQS/ DQS
(input)
DQ
(input)
Lower Address
D0 D1
D0
#3 #2
#1 (#0)
Last one data is masked.
BL = 4, SEQUENTIAL MODE
Command
Address
WRA
LAL
UA
LA=#3
VW=All
DESL
WRA
LAL
UA
LA=#1
VW=1
VW0 = High
VW1 = Low
Bank Add.
Bank
"a"
DESL
WRA
LAL
UA
LA=#2
VW=2
VW0 = High
VW1 = High
DESL
VW0 = Low
VW1 = High
Bank
"a"
Bank
"a"
DQS/ DQS
(input)
DQ
(input)
Lower Address
D0 D1 D2 D3
D0
D0 D1
#3 #0 #1 #2
#1(#2)(#3)(#0)
#2 #3 (#0)(#1)
Last three data are masked.
Last two data are masked.
Note: DQS ( DQS ) input must be continued till end of burst count even if some of laster data is masked.
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TC59LM914/06AMG-37,-50
POWER DOWN TIMING (CL = 4, BL = 4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
IPDA
Command
Address
RDA
LAL
UA
LA
DESL
RDA
or
WRA
DESL
UA
tIS
IPD = 1 cycle
tIH
PD
tQPDH
tPDEX
lRC(min) , tREFI(max)
DQS
(output)
Hi-Z
DQS
(output)
Hi-Z
Hi-Z
CL = 4
DQ
(output)
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Power Down Entry
Power Down Exit
Note: PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
TC59LM914AMG doesn’t have DQS .
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TC59LM914/06AMG-37,-50
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
IPDA
Command
Address
WRA
LAL
UA
LA
DESL
RDA
or
WRA
DESL
UA
tIS
IPD = 1 cycle
tIH
PD
WL = 3
2 clock cycles
tPDEX
lRC(min) , tREFI(max)
DQS
(input)
DQS
(input)
WL = 3
DQ
(input)
D0 D1 D2 D3
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
TC59LM914AMG doesn’t have DQS .
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MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="0"
BA1="0"
BA2="0"
BA
CLK
CLK
IRSC
RDA
LAL
A13~A0
UA
LA
BA0~BA2
BA
Command
DESL
RDA
MRS
DESL
CL + BL/2
DQS
(output)
Hi-Z
Hi-Z
DQS
DQ
(output)
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
TC59LM914AMG doesn’t have DQS .
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MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="0"
BA1="0"
BA2="0"
BA
CLK
CLK
IRSC
WRA
LAL
A13~A0
UA
LA
BA0~BA2
BA
Command
DESL
RDA
MRS
DESL
WL+BL/2
DQS
(input)
DQS
(input)
DQ
(input)
D0 D1 D2 D3
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
TC59LM914AMG doesn’t have DQS .
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EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="1"
BA1="0"
BA2="0"
BA
CLK
CLK
IRSC
Command
RDA
LAL
A13~A0
UA
LA
BA0~BA2
BA
DESL
RDA
MRS
DESL
CL + BL/2
DQS
(output)
Hi-Z
DQS
(output)
Hi-Z
DQ
(output)
Q0 Q1
Note:
Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
TC59LM914AMG doesn’t have DQS .
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TC59LM914/06AMG-37,-50
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="1"
BA1="0"
BA2="0"
BA
CLK
CLK
IRSC
Command
WRA
LAL
A13~A0
UA
LA
BA0~BA2
BA
DESL
RDA
MRS
DESL
WL+BL/2
DQS
(input)
DQS
(input)
DQ
(input)
D0 D1 D2 D3
Note:
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
TC59LM914AMG doesn’t have DQS .
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TC59LM914/06AMG-37,-50
AUTO-REFRESH TIMING (CL = 4, BL = 4)
0
1
2
3
4
5
6
7
n−1
n
n+1
n+2
RDA
or
WRA
LAL or
MRS or
REF
CLK
CLK
IRC = 5 cycles
Command
RDA
LAL
Bank, Address
Bank,
UA
LA
IRCD = 1 cycle
DQS/ DQS
(output)
Hi-Z
DQ
(output)
Hi-Z
IREFC = 18 cycles
DESL
WRA
IRAS = 4 cycles
REF
DESL
IRCD = 1 cycle
Hi-Z
CL = 4
Hi-Z
Q0 Q1 Q2 Q3
Note: In case of CL = 4, IREFC must be meet 18 clock cycles.
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh
command specified by tREFI must be satisfied.
tREFI is average interval time in 8 Refresh cycles that is sampled randomly.
TC59LM914AMG doesn’t have DQS .
t1
t2
t3
t7
t8
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
tREFI =
Total time of 8 Refresh cycle
8
=
t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8
8
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area
than Read / Write operation.
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TC59LM914/06AMG-37,-50
SELF-REFRESH ENTRY TIMING
0
1
2
3
4
m−1
5
m
m+1
CLK
CLK
Command
IRCD = 1 cycle
WRA
IREFC
REF
DESL
tFPDL (min) tFPDL (max)
Auto Refresh
PD
Self Refresh Entry
IPDV
tQPDH
ICKD
Hi-Z
DQS/ DQS
(output)
DQ
(output)
*2
Hi-Z
Qx
Notes: 1.
is don’t care.
2. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh
mode. When PD is brought to "Low" after lPDV, FCRAM perform Auto Refresh and enter Power
down mode. In case of PD fall between tFPDL(max) and lPDV, FCRAM will either entry
Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be specified which
mode FCRAM operates.
3. It is desirable that clock input is continued at least lCKD from REF command even though PD is
brought to “Low” for Self-Refresh Entry.
4. TC59LM914AMG doesn’t have DQS .
5. In the case of Self-Refresh entry after Write Operation, the delay time from the LAL command
following WRA to the REF command is Write Latency (WL) +3 clock cycles minimum.
SELF-REFRESH EXIT TIMING
0
1
m−1
2
m+1
m
m+2
n−1
n
n+1
p−1
p
CLK
CLK
*6
*2
IREFC
IREFC
*3
DESL
Command
IPDA = 1 cycles
WRA
*4
*5
*5
REF
Command (1st)
*6
Command (2nd)
DESL
IRCD = 1 cycle
RDA
*7
*7
LAL
IRCD = 1 cycle
PD
tPDEX
ILOCK
DQS/ DQS
(output)
Hi-Z
DQ
(output)
Hi-Z
Self-Refresh Exit
Notes: 1.
2.
3.
4.
5.
is don’t care.
Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
DESL command must be asserted during IREFC after PD is brought to “High”.
IPDA is defined from the first clock rising edge after PD is brought to “High”.
It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
6. Any command (except Read command) can be issued after IREFC.
7. Read command (RDA + LAL) can be issued after ILOCK.
8. TC59LM914AMG doesn’t have DQS .
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TC59LM914/06AMG-37,-50
FUNCTIONAL DESCRIPTION
Network FCRAM
TM
FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAMTM is competent to
perform fast random core access, low latency and high-speed data transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The
CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative
edge of CLK . The DQS and DQ output are aligned to the crossing point of CLK and CLK . The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock
Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if
any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL: CS & FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each operation
mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs.
BANK ADDRESSES: BA0~BA2
The BA0 to BA2 inputs are latched at the time of assertion of the RDA or WRA command and are selected the
bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register
Set command (MRS or EMRS).
Bank #0
Bank #1
Bank #2
Bank #3
Bank #4
Bank #5
Bank #6
Bank #7
BA0
BA1
BA2
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
Also, when BA2 input assign to A14 input, TC59LM914/06AMG can function as 4 bank devices and can keep
backward compatibility to 256Mb (4bank) Network FCRAM.
ADDRESS INPUTS: A0~A13
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The
Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are
latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or
Extended Mode Register set cycle.
8 bank operation
4 bank operation
I/O organization
UPPER ADDRESS
LOWER ADDRESS
8 bits
A0~A13
A0~A8
16 bits
A0~A13
A0~A7
8 bits
A0~A13, BA2(A14)
A0~A8
16 bits
A0~A13, BA2(A14)
A0~A7
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TC59LM914/06AMG-37,-50
DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The output
data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
DATA STROBE: DQS, DQS
The DQS is bi-directional signal. Both edge of DQS are used as the reference of data input or output. In write
operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS is an
output signal provides the read data strobe.
TC59LM906AMG has differential data strobe pin ( DQS ). When DQS is enable mode, DQS is differential
output signal for DQS in read operation, data input are latched at the crossing point of DQS and DQS in Write
operation. When DQS is disable mode, DQS is always Hi-Z, and data input are latched at the crossing point of
DQS and VREF level. DQS mode is set at Extended Mode Register Set Cycle.
TC59LM914AMG doesn’t have DQS pin. Data input are latched at the crossing point of L/UDQS and VREF
level in Write operation. LDQS is strobe signal for DQ0-DQ7. UDQS is strobe signal for DQ8-DQ15.
POWER SUPPLY: VDD, VDDQ, VSS, VSSQ
VDD and VSS are power supply pins for memory core and peripheral circuits.
VDDQ and VSSQ are power supply pins for the output buffer.
REFERENCE VOLTAGE: VREF
VREF is reference voltage for all input signals.
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TC59LM914/06AMG-37,-50
COMMAND FUNCTIONS and OPERATIONS
TC59LM914/06AMG are introduced the two consecutive command input method. Therefore, except for Power
Down mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next
clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS/ DQS
output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing of
the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after lRC. DQS is differential data strobe signal supported TC59LM906AMG.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of
DQS/ DQS input signal (Burst Write Operation). The data and DQS/ DQS inputs have to be asserted in keeping
with clock input after CAS latency-1 from the issuing of the LAL command. The DQS/ DQS has to be provided
for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write
operated bank goes back automatically to the idle state after lRC. Write Burst Length is controlled by VW0 and
VW1 inputs with LAL command. See VW truth table. DQS is differential data strobe signal supported
TC59LM906AMG.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM914/06AMG are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with
the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks
are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by the REF
command having gone into the next clock of the WRA command instead of the LAL command. The minimum
period between the Auto-Refresh command and the next command is specified by lREFC. However, about a
synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh,
Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum. In case of burst refresh or
random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than
400 ns always. In other words, the number of Auto-Refresh cycles that be performed within 3.2 µs (8 × 400 ns) is
to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD= “L”)
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM914/06AMG become
Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within tFPDL from the
REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh
period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command.
Once the device enters Self-Refresh mode, the DESL command must be continued for lREFC period. In addition, it
is desirable that clock input is kept in lCKD period. The device is in Self-Refresh mode as long as PD held “Low”.
During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power
dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along
with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified
by lREFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh
command is issued to avoid the violation of the refresh period just after lREFC from Self-Refresh exit.
Power Down Mode ( PD= “L”)
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM914/06AMG become Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers are disabled after specified time except for PD . Therefore, the power dissipation lowers. To exit the
Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for two clock cycle
after PD goes high. The Power Down exit function is asynchronous operation.
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Mode Register Set (MRS) and Extended Mode Register Set (EMRS)
(1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program
the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set
in the Mode Register is transferred using A0 to A13, BA0 to BA2 address inputs. The TC59LM914/06AMG have
two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is
chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a
read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has four function fields.
The five fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable.
(E-2) Output Driver Impedance Control field.
(E-3) Off-Chip Driver (OCD) Impedance Adjustment for full strength output driver.
(E-4) DQS enable field.
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register
is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended
Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before
proper operation.
•
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
Mode Register Set
0
0
Regular MRS
0
1
Extended MRS
1
×
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0), (BL)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length
to be 2 or 4 words.
A2
A1
A0
BURST LENGTH
0
0
0
Reserved
0
0
1
2 words
0
1
0
4 words
0
1
1
Reserved
1
×
×
Reserved
(R-2) Burst Type field (A3), (BT)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential
mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst
length of 2 and 4 words.
A3
BURST TYPE
0
Sequential
1
Interleave
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•
Addressing sequence of Sequential mode
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device.
CAS Latency = 4
CLK
CLK
Command
RDA
LAL
DQS/ DQS
Data Data Data Data
0
1
2
3
DQ
Addressing sequence for Sequential mode
•
DATA
ACCESS ADDRESS
Data 0
n
Data 1
n+1
Data 2
n+2
Data 3
n+3
BURST LENGTH
2 words (address bits is LA0)
not carried from LA0~LA1
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits
in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA
(R-3)
ACCESS ADDRESS
BURST LENGTH
Data 0
ּּּA8
A7
A6
A5
A4
A3
A2
A1
A0
Data 1
ּּּA8
A7
A6
A5
A4
A3
A2
A1
A0
Data 2
ּּּA8
A7
A6 A5
A4
A3 A2
A1
A0
Data 3
ּּּA8
A7
A6 A5
A4
A3 A2
A1
A0
2 words
4 words
CAS Latency field (A6 to A4), (CL)
This field specifies the number of clock cycles from the assertion of the LAL command following the
RDA command to the first data read. The minimum values of CAS Latency depends on the frequency
of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
A6
A5
A4
CAS LATENCY
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
Reserved
1
1
1
Reserved
(R-4) Test Mode field (A7), (TE)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A13, BA2)
These bits are reserved for future operations. They must be set to “0” for normal operation.
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TC59LM914/06AMG-37,-50
Extended Mode Register fields
(E-1) DLL Switch field (A0), (DS)
This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must set to “0” for
normal operation.
(E-2) Output Driver Impedance Control field (A1, A6) (DIC)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported.
Output Driver Strength can be set by field in EMRS with OCD calibration default (A7~A9=1 at EMRS).
A6
A1
OUTPUT DRIVER IMPEDANCE CONTROL
0
0
Normal Output Driver
0
1
Strong Output Driver
1
0
Weak Output Driver
1
1
Full Strength Output Driver
(E-3) Off-Chip Driver (OCD) Impedance Adjustment for full strength output driver (A7 to A9) (OCD)
Output Driver Strength can be set by DIC field (E-2). In case of choosing Full strength Output Driver,
OCD calibration is available. The driver strength set by DIC field is the initial driver level at OCD
Impedance Adjustment. When OCD calibration is performed, A1 and A6 inputs at EMRS must be “1” for
Full Strength Output Driver.
The Network FCRAMTM supports driver calibration feature and the flow chart below is an example of
sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before
any other command being issued. MRS should be set before entering OCD impedance adjustment.
MRS should be set before entering OCD impedance adjustment.
Start
EMRS: OCD calibration mode exit
EMRS: Drive(1)
DQ &DQS High; DQS Low
Test
EMRS: Drive(0)
DQ &DQS Low; DQS High
ALL OK
ALL OK
Need Calibration
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
EMRS:
Enter Adjust Mode
BL=4 code Input to all DQs
Inc, Dec, or NOP
BL=4 code Input to all DQs
Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
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Extended Mode Register Set for OCD Impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are
driven out by Network FCRAM. In drive (1) mode, all DQ, DQS signals are driven high and DQS signals are
driven low. In drive (0) mode, all DQ, DQS signals are driven low and DQS signals are driven high. In adjust
mode, BL=4 of operation code data must be used
A9
A8
A7
Operation
0
0
0
OCD calibration mode exit
0
0
1
Drive (1) DQ, DQS high and DQS low
0
1
0
Drive (0) DQ, DQS low and DQS high
1
0
0
Adjust mode
1
1
1
OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit
burst code to Network FCRAM. For this operation, Burst Length has to be set to BL=4 via MRS command
before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 means all
DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DQs
simultaneously and after OCD calibration, all DQs of a given Network FCRAM will be adjusted to the same
driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further
increment or decrement code has no effect.
Off-Chip Driver Program
4bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
0
0
0
NOP (No operation)
NOP (No operation)
0
0
0
1
Increase by 1 step
NOP
0
0
1
0
Decrease by 1 step
NOP
0
1
0
0
NOP
Increase by 1 step
1
0
0
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
Increase by 1 step
0
1
1
0
Decrease by 1 step
Increase by 1 step
1
0
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Decrease by 1 step
Other Combinations
Reserved
For proper operation of adjust mode, WL=CL-1 clocks and tDS / tDH should be met as the following timing
diagram. For input data pattern for adjustment, DT0~DT3 is a fixed order and “not affected by MRS addressing
mode (i.e. Sequential or interleave).
Driver strength is controlled within the following range by OCD impedance adjustment.
SYMBOL
IOH (DC)
IOL (DC)
PARAMETER
Output Source DC Current for VDDQ = 1.7V~1.9V
Full Strength VDDQ = 1.7V VOH = 1.420V
Output Driver Output Sink DC Current for V Q = 1.7V~1.9V
DD
VDDQ = 1.7V VOL = 0.280V
MIN
MAX
−14.0
−18.7
14.0
18.7
UNIT
NOTES
mA
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TC59LM914/06AMG-37,-50
OCD adjust mode
Command
RDA
OCD calibration mode exit
EMRS
NOP
NOP
NOP
NOP
RDA
EMRS
NOP
CLK
CLK
WL
1clock
DQS
DQS_in
tDS tDH
DT0
DQ_in
DT1
DT2
DT3
Drive mode
Drive mode, both Drive (1) and Drive (0), is used for controllers to measure Network FCRAM Driver
impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output
drivers are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
OCD calibration mode exit
Enter Drive mode
Command
RDA
EMRS
NOP
NOP
RDA
EMRS
NOP
CLK
CLK
DQS,
DQS
DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0)
DQs high for Drive (1), DQs low for Drive (0)
DQ
tOIT
tOIT
0∼12ns
0∼12ns
(E-4) DQS enable field (A10), ( DQS )
This bit is used to enable Differential Data strobe.
DQS is available on TC59LM906AMG. This field of TC59LM914AMG is ignored.
A10
DQS Enable
0
Disable
1
Enable
(E-5) Interface mode select (A11)
This bit must be always set “0”.
(E-6) Reserved field (A2 to A5, A12 to A13, BA2)
These bits are reserved for future operations and must be set to “0” for normal operation.
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PACKAGE DIMENSIONS
P-BGA64-1317-1.00AZ
0.2 S B
0.2 S A
16.5
0
13.086 -0.15
12.7
0
10.975 -0.15
0.15
1.20MAX
0.2 S
S
0.4 0.05
0.15MIN
0.1 S
0.5 0.05
0.08
S AB
1.25
B
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
3.85
INDEX
A
1.0
4 5 6
1.5 1.5
1 2 3
3.85
1.85
1.0
2.0
Note: In order to support a package, four outer balls located on F and K row are required to assembly to board.
These four ball is not connected to any electrical level.
Weight: 0.23g (typ.)
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REVISION HISTORY
− Rev.0.9 (Feb. 27 ’2004)
− Rev0.91 (Mar. 16 ‘2004)
• Corrected TYPO (page57). Pin name is changed from “Q” to “R”.
− Rev0.92 (Apr. 21 ‘2004)
• Parameter definition in Recommended DC, AC Operating Conditions Table are changed (page 5).
− VICK(DC): Differential Clock DC Input Voltage
− VID(DC): Input DC Differential Voltage. CLK and /CLK inputs (DC)
− VID(AC): Input AC Differential Voltage. CLK and /CLK inputs (AC)
− VID(AC),min is changed from 0.55V to 0.5V.
− VISO(AC): Differential Clock AC Middle Level.
• CLK is changed to VTR and CLK is changed to VCP (page 6).
• Below comment is added in Note(10) (page 6).
VTR is the true input (such as CLK, DQS) level and VCP is the complementary input (such as CLK , DQS )
level.
− Rev0.93 (Jun. 9 ‘2004)
• Package name (P−BGA64−1317−1.00AZ) added (page 1).
• tREFI (Auto-Refresh Average Interval) spec changed from 7.8µs to 3.9µs (page 1, 10, 51).
• VDD range changed from 2.5V ± 0.15V to 2.5V ± 0.125V.
• Corrected TYPO (page 9, 10, 14, 15, 17)
• tDSP spec changed for all speed bin as below (page 9)
tDSP(min) = 0.4 × tCK → 0.35 × tCK
tDSP(max) = 0.6 × tCK → 0.65 × tCK
• tIS and tIH spec changed for all speed bin as below (page 9)
“−37”: tIS = 0.6ns → 0.5ns , tIH = 0.6ns → 0.5ns
“−45”: tIS = 0.7ns → 0.6ns , tIH = 0.7ns → 0.6ns
“−50”: tIS = 0.8ns → 0.7ns , tIH = 0.8ns → 0.7ns
• tDSH (DQS Input Falling Edge Hold Time from CLK) added (page 9).
• tOIT (OCD drive mode output delay time) added (page 10, 56).
• OCD definition at power up sequence added (page 12).
• Note (4) added at power up sequence (page 12).
• OCD setting on Extended Mode Register table changed as below (page 21, 54, 55)
(A9, A8, A7) = (0, 0, 0): OCD Calibration default → OCD Calibration mode exit.
(A9, A8, A7) = (1, 1, 1): OCD Calibration mode exit → OCD Calibration mode default.
• Full strength Output Driver added on DIC (page 21, 54).
(A6, A1) = (1, 1): Reserved → Full Strength Output Driver.
• Note (5) added on Self-Refresh Entry Timing (page 48).
• Explanation for OCD Impedance Adjustment modified (page 54).
• IOH / IOL table added (page 55).
− Rev1.0 (Aug. 20 ‘2004)
• “-45” version dropped.
• Some notes in the page 8 moved to page 7 (page 7, 8).
• Note 2 changed as below (page 7).
Before: These parameters depend on the output loading. The specified values are obtained with the
output open
After: These parameters define the current between VDD and VSS.
• Corrected TYPO (page 2, 3, 14, 15, 17).
• Package weight (0.23g) added (page 57).
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TC59LM914/06AMG-37,-50
RESTRICTIONS ON PRODUCT USE
•
030619EBA
The information contained herein is subject to change without notice.
•
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
•
•
The products described in this document are subject to the foreign exchange and foreign trade laws.
TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
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