Revised February 2005
74ABT125
Quad Buffer with 3-STATE Outputs
General Description
Features
The ABT125 contains four independent non-inverting buffers with 3-STATE outputs.
■ Non-inverting buffers
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
■ Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number
Package
Package Description
Number
74ABT125CSC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ABT125CSJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT125CMTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT125CMTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
Descriptions
An , Bn
Inputs
On
Outputs
Function Table
Inputs
Output
An
Bn
L
L
On
L
L
H
H
H
X
Z
H HIGH Voltage Level
L LOW Voltage Level
Z HIGH Impedance
X Immaterial
© 2005 Fairchild Semiconductor Corporation
DS011667
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74ABT125 Quad Buffer with 3-STATE Outputs
March 1994
74ABT125
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
65qC to 150qC
55qC to 125qC
55qC to 150qC
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Supply Voltage
Minimum Input Edge Rate ('V/'t)
VCC Pin Potential to
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
40qC to 85qC
4.5V to 5.5V
Free Air Ambient Temperature
Data Input
50 mV/ns
Enable Input
20 mV/ns
Voltage Applied to Any Output
in the Disabled or
0.5V to 5.5V
0.5V to VCC
Power-Off State
in the HIGH State
Current Applied to Output
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
twice the rated IOL (mA)
in LOW State (Max)
DC Latchup Source Current
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
300 mA
(Across Comm Operating Range)
Over Voltage Latchup (I/O)
10V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
1.2
V
Min
IIN
18 mA
VOH
Output HIGH Voltage
2.5
V
Min
IOH
3 mA
2.0
V
Min
IOH
32 mA
V
Min
IOL
64 mA
PA
Max
PA
Max
VOL
Output LOW Voltage
IIH
Input HIGH Current
V
Conditions
VIH
0.55
1
1
IBVI
Input HIGH Current Breakdown Test
7
IIL
Input LOW Current
1
1
Recognized HIGH Signal
Recognized LOW Signal
PA
Max
V
0.0
VIN
2.7V (Note 4)
VIN
VCC
VIN
7.0V
VIN
0.5V (Note 4)
VIN
0.0V
1.9 PA, All Other Pin Grounded
VID
Input Leakage Test
IOZH
Output Leakage Current
10
PA
05.5V
VOUT
2.7V; OEn
2.0V
IOZL
Output Leakage Current
10
PA
05.5V
VOUT
0.5V; OEn
2.0V
IOS
Output Short-Circuit Current
275
mA
Max
VOUT
0.0V
IID
ICEX
Output HIGH Leakage Current
50
PA
Max
VOUT
VCC
IZZ
Bus Drainage Test
100
PA
0.0
VOUT
5.5V; All Others GND
ICCH
Power Supply Current
50
PA
Max
All Outputs HIGH
ICCL
Power Supply Current
15
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
50
PA
Max
OE n
VCC;
All Others at V CC or Ground
ICCT
Additional ICC /Input
Max
VI
V CC 2.1V
Outputs Enabled
1.5
mA
Outputs 3-STATE
1.5
mA
Enable Input VI
Outputs 3-STATE
50
PA
Data Input V I
VCC 2.1V
VCC 2.1V
All Others at V CC or Ground
ICCD
Dynamic ICC
No Load
mA/
(Note 4)
0.1
MHz
Max
Outputs Open
OE n
GND, (Note 5)
One Bit Toggling, 50% Duty Cycle
Note 4: Guaranteed, but not tested.
Note 5: For 8 bits toggling, ICCD 0.8 mA/MHz.
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2
25qC
TA
Symbol
VCC
Parameter
CL
Min
40qC to 85qC
TA
5V
VCC
50 pF
Typ
CL
4.5V–5.5V
Units
50 pF
Max
Min
tPLH
Propagation Delay
1.0
4.6
1.0
Max
4.6
tPHL
Data to Outputs
1.0
4.9
1.0
4.9
tPZH
Output Enable
1.0
5.1
1.0
5.1
tPZL
Time
1.0
6.8
1.0
6.8
tPHZ
Output Disable
1.0
6.2
1.0
6.2
tPLZ
Time
1.0
5.5
1.0
5.5
ns
ns
ns
Capacitance
Symbol
Parameter
CIN
Input Capacitance
COUT (Note 6)
Output Capacitance
Note 6: COUT is measured at frequency f
Conditions
Typ
Units
5.0
pF
V CC
0V
9.0
pF
V CC
5.0V
TA
25qC
1 MHz, per MIL-STD-883, Method 3012.
3
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74ABT125
AC Electrical Characteristics
74ABT125
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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4
74ABT125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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74ABT125 Quad Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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