NSC CLC007 Serial digital cable driver with dual complementary Datasheet

CLC007
Serial Digital Cable Driver with Dual Complementary
Outputs
General Description
Applications
National’s Comlinear CLC007 is a monolithic, high-speed cable driver designed for the SMPTE 259M serial digital video
data transmission standard. The CLC007 drives 75Ω transmission lines (Belden 8281 or equivalent) at data rates up to
400 Mbps. Controlled output rise and fall times (750 ps typical) minimize transition-induced jitter. The output voltage
swing, typically 1.65V, set by an accurate, low-drift internal
bandgap reference, delivers an 800 mV swing to backmatched and terminated 75Ω cable.
The CLC007’s class AB output stage consumes less power
than other designs, 195 mW with all outputs terminated, and
requires no external bias resistors. The differential inputs accept a wide range of digital signals from 200 mVP-P to ECL
levels within the specified common-mode limits. All this make
the CLC007 an excellent general purpose high speed driver
for digital applications.
The CLC007 is powered from a single +5V or −5.2V supply
and comes in an 8-pin SOIC package.
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Digital routers and distribution amplifiers
Coaxial cable driver for digital transmission line
Twisted pair driver
Digital distribution amplifiers
SMPTE, Sonet/SDH, and ATM compatible driver
Buffer applications
270 Mbps Eye Pattern
Key Specifications
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■
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650 ps rise and fall times
Data rates to 400 Mbps
2 sets of complimentary outputs
200 mV differential input
Low residual jitter (25 pspp)
10008501
Connection Diagram (8-Pin SOIC)
Features
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No external pull-down resistors
Differential input and output
Low power dissipation
Single +5V or −5.2V supply
Replaces GS9007 in most applications
10008503
Order Number CLC007BM
See NS Package Number M08A
© 2007 National Semiconductor Corporation
100085
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CLC007 Serial Digital Cable Driver with Dual Complementary Outputs
October 2007
CLC007
Typical Application
10008502
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If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Output Current
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering 10 Second)
ESD Rating (Human body Model)
6V
30 mA
+125°C
−65°C to +150°C
+160°C
+105°C/W
254 Mhr
Recommended Operating
Conditions
Supply Voltage (VCC – VEE)
+300°C
1000V
+4.5V to +5.5V
Electrical Characteristics
(VCC = 0V, VEE = −5V; unless otherwise specified).
Parameter
Conditions
Typ +25°C
Min/Max
+25°C
Min/Max
0°C to
+70°C
Min/Max
−40°C to
+85°C
Units
STATIC PERFORMANCE
Supply Current, Loaded
(Note 5)
39
—
—
—
mA
Supply Current, Unloaded
(Note 3)
34
28/45
26/47
26/47
mA
Output HIGH Voltage (VOH)
(Note 3)
−1.7
−2.0/1.4
−2.0/1.4
−2.0/1.4
V
Output Low Voltage (VOL)
(Note 3)
−3.3
−3.6/3.0
−3.6/3.0
−3.6/3.0
V
10
30
50
50
μA
Input Bias Current
Output Swing
1.65
1.55/1.75
1.53/1.77
1.51/1.79
V
Common Mode Input Range Upper Limit
(Note 3)
−0.7
−0.8
−0.8
−0.8
V
Common Mode Input Range Lower Limit
−2.6
−2.5
−2.5
−2.5
V
Minimum Differential Input Swing
200
200
200
200
mV
Power Supply Rejection Ratio (Note 3)
26
20
20
20
dB
650
425/955
400/1100
400/1100
ps
AC PERFORMANCE
Output Rise and Fall Time
(Notes 3, 4, 5)
Overshoot
5
%
Propagation Delay
1.0
ns
Duty Cycle Distortion
50
Residual Jitter
25
ps
—
—
—
pspp
MISCELLANEOUS PERFORMANCE
Input Capacitance
1.0
pF
Output Resistance
10
Output Inductance
6
Ω
nH
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: Spec is 100% tested at +25°C
Note 4: Measured between the 20% and 80% levels of the waveform.
Note 5: Measured with both outputs driving 150Ω, AC coupled at 270 Mbps.
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CLC007
Package Thermal Resistance
θJA 8–pin SOIC
θJC 8–pin SOIC
Reliability Information
MTTF
Absolute Maximum Ratings (Note 1)
CLC007
Figure 5 show how Thevenin-equivalent resistor networks are
used to provide input termination and biasing. The input D.C.
common-mode voltage range is 0.8V to 2.5V below the positive power supply (VCC). Input signals plus bias should be
kept within the specified common-mode range. For an
800 mVP-P input signal, typical input bias levels range from
1.2V to 2.1V below the positive supply.
Operation
INPUT INTERFACING
The CLC007 has high impedance, emitter-follower buffered,
differential inputs. Single-ended signals may also be input.
Transmission lines supplying input signals must be properly
terminated close to the CLC007. Either A.C. or D.C. coupling
as in Figure 2 or Figure 3 may be used. Figures 2, 4 and
Resistor to VCC (R1)
Resistor to VEE (R2)
ECL, 50Ω, 5V, VT=2V
Load Type
82.5Ω
124Ω
ECL, 50Ω, 5.2V, VT=2V
80.6Ω
133Ω
ECL, 75Ω, 5V, VT=2V
124Ω
187Ω
ECL, 75Ω, 5.2V, VT=2V
121Ω
196Ω
800 mVP-P, 50Ω, 5V, VT=1.6V
75.0Ω
154Ω
800 mVP-P, 75Ω, 5V, VT=1.6V
110Ω
232Ω
800 mVP-P, 2.2 KΩ, 5V, VT=1.6V
3240Ω
6810Ω
10008504
FIGURE 1. Input Stage
10008505
FIGURE 2. AC Coupled Input
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CLC007
10008506
FIGURE 3. DC Coupled Input
10008507
FIGURE 4. Single Ended 50Ω ECL Input
5
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CLC007
10008508
FIGURE 5. Differential 50Ω ECL Input
OUTPUT INTERFACING
The CLC007’s class AB output stage, Figure 6, requires no
standing current in the output transistors and therefore requires no biasing or pull-down resistors. Advantages of this
arrangement are lower power dissipation and fewer external
components. The output may be either D.C. or A.C. coupled
to the load. A bandgap voltage reference sets output voltage
levels which are compatible with F100K and 10K ECL when
correctly terminated. The outputs do not have the same output voltage temperature coefficient as 10K. Therefore, noise
margins will be reduced over the full temperature range when
driving 10K ECL. Noise margins will not be affected when interfacing to F100K since F100K is fully voltage and temperature compensated.
10008509
FIGURE 6. Output Stage
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CLC007
10008510
FIGURE 7. Differential Input DC Coupled Output
OUTPUT RISE AND FALL TIMES
Output load capacitance can significantly affect output rise
and fall times. The effect of load capacitance, stray or otherwise, may be reduced by placing the output back-match
resistor close to the output pin and by minimizing all interconnecting trace lengths. Figure 8 shows the effect on risetime
of parallel load capacitance across a 150Ω load.
10008511
FIGURE 8. Rise Time vs CL
PCB Layout Recommendations
Printed circuit board layout affects the performance of the
CLC007. The following guidelines will aid in achieving satisfactory device performance.
• Use a ground plane or power/ground plane sandwich
design for optimum performance.
• Bypass device power with a 0.01 µF monolithic ceramic
capacitor in parallel with a 6.8 µF tantalum electrolytic
capacitor located no more than 0.1” (2.5 mm) from the
device power pins.
• Provide short, symmetrical ground return paths for:
•
7
— inputs,
— supply bypass capacitors and
— the output load.
Provide short, grounded guard traces located
— under the centerline of the package,
— 0.1” (2.5 mm) from the package pins
— on both top and bottom of the board with connecting
vias.
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CLC007
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number CLC007BM
NS Package Number M08A
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CLC007
Notes
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CLC007 Serial Digital Cable Driver with Dual Complementary Outputs
Notes
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