TC94A48FG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC94A48FG Single-chip Audio Digital Signal Processor The TC94A48FG is a single-chip audio Digital Signal Processor, incorporating two channels AD converter and six channels DA converter. It can realize many applications, including sound field control, such as hall simulation, digital filters, such as equalizers, surround sound, base boost and more. Features P-LQFP64-1010-0.50E • Incorporates a 1-bit Σ-∆ AD converter (2 channels). • THD+N: -78 dB (typ.), S/N ratio: 92 dB (typ.) Incorporates a multi-bit Σ-∆ DA converter (6 channels). • THD+N: -88 dB (typ.), S/N ratio: 98 dB (typ.) Digital input/output ports • Four input ports (8 channels) Four output ports (8 channels) The DSP block specifications are as follows: • Data bus : 24 bits Multiplier/adder : 24 bits × 24 bits + 51 bits → 51 bits Accumulator : 51 bits (sign extension: 4 bits) Program ROM : 3072 words × 16 bits Program RAM : 1024 words × 16 bits XRAM : 4096 words × 24 bits YRAM : 1024 words × 24 bits CROM : 1024 words × 24 bits The microcontroller interface can be selected between serial mode and I2C bus mode. • Operating supply voltage: 3.3 V (some pins accept 5 V) • CMOS silicon structure supports high speed. • The package is a 64-pin LQFP (0.5-mm pitch) package. 1 Weight: 0.4 g (typ.) 2005-09-28 TC94A48FG Block Diagram PLLC /MIACK MILP /MIDIO /MICK /MICS GPI0 GPI1 MIMD Microcontroller interface Generalperpose port Timing ＰＬＬ GPO0 GPO1 MCKO BCKO XI XO LRCKO 11.2896MHz(256fs) LRCKI0 /RST BTMD SDO0 LRCKI1 BCKI0 ＳＩ SDI0 SDO1 ＳＯ (8ch) BCKI1 SDO2 (8ch) SDI1 SDO3 16bit Instruction DSP SDI2 SDI3 ＡＤＣ Ｌｃｈ VREF ADVR VREF (4fs rate ×2ch) DAO1 ΣΔ ＤＡＣ ２ｃｈ DAO2 ΣΔ ＤＡＣ ３ｃｈ DAO3 VREF (4fs rate ×6ch) (4fs rate ×2ch) ＡＤＣ Ｒｃｈ RIN ＤＡＣ １ｃｈ REG Buffer (64w ×21b) MUX ADVL (4fs rate ×6ch) ＭＡＦ(→4fs) LIN ΣΔ VRI ΣΔ ＤＡＣ ４ｃｈ DAO4 ΣΔ ＤＡＣ ５ｃｈ DAO5 ΣΔ ＤＡＣ ６ｃｈ DAO6 BCKO MCKO GPO1 GPO0 GND VDD GPI1 GPI0 /MICS /MICK /MIDIO /MIACK MILP GNDP PLLC VDDP Pin Layout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BTMD 49 32 LRCKO MIMD 50 31 SDO0 /RST 51 30 SDO1 VDD 52 29 SDO2 GND 53 28 SDO3 TEST1 54 27 BCKI0 TEST0 55 26 BCKI1 GNDL 56 25 LRCKI0 LIN 57 24 LRCKI1 ADVL 58 23 SDI0 VDDA 59 22 SDI1 ADVR 60 21 SDI2 RIN 61 20 SDI3 GNDR 62 19 GND GNDX 63 18 VDD XI 64 17 VDD6 XO VDD1 DAO1 GND12 DAO2 VDD23 DAO3 9 10 11 12 13 14 15 16 2 DAO6 8 GND56 7 DAO5 6 VDD45 5 DAO4 4 GND4 3 VRI 2 GND3 1 VDDX TC94A48FG 2005-09-28 TC94A48FG Pin Function Pin No. Symbol I/O 1 XO O Crystal oscillator connecting or clock output pin 2 VDDX － Power pin for oscillator circuit 3 VDD1 － Analog power pin for DAC1 4 DAO1 O DAC1 signal output pin 5 GND12 － Analog ground pin for DAC1/2 6 DAO2 O DAC2 signal output pin 7 VDD23 － Analog power pin for DAC2/3 8 DAO3 O DAC3 signal output pin 9 GND3 － Analog power pin for DAC3 10 VRI I 11 GND4 － Analog ground pin for DAC4 12 DAO4 O DAC4 signal output pin 13 VDD45 － Analog power pin for DAC4/5 14 DAO5 O DAC5 signal output pin 15 GND56 － Analog ground pin for DAC5/6 16 DAO6 O DAC6 signal output pin 17 VDD6 － Analog power pin for DAC6 18 VDD － Digital power pin 19 GND － Function Remarks Reference voltage pin for DAC Digital ground pin 20 SDI3 I Audio serial data input pin 3 It connects to GND or VDD pins when if it is unused this pin. 21 SDI2 I Audio serial data input pin 2 It connects to GND or VDD pins when if it is unused this pin. Schmitt input 5V tolerant 22 SDI1 I Audio serial data input pin 1 It connects to GND or VDD pins when if it is unused this pin. Schmitt input 5V tolerant 23 SDI0 I Audio serial data input pin 0 It connects to GND or VDD pins when if it is unused this pin. Schmitt input 5V tolerant 24 LRCKI1 I LR clock input pin 1 It connects to GND or VDD pins when if it is unused this pin. Schmitt input 5V tolerant 25 LRCKI0 I LR clock input pin 0 It connects to GND or VDD pins when if it is unused this pin. Schmitt input 5V tolerant 26 BCKI1 I Bit clock input pin 1 It connects to GND or VDD pins when if it is unused this pin. Schmitt input 5V tolerant 27 BCKI0 I Bit clock input pin 0 It connects to GND or VDD pins when if it is unused this pin. Schmitt input 5V tolerant 28 SDO3 O Audio serial data output pin 3 It leaves to open when if it is unused. Push-pull output 29 SDO2 O Audio serial data output pin 2 It leaves to open when if it is unused. Push-pull output 30 SDO1 O Audio serial data output pin 1 It leaves to open when if it is unused. Push-pull output 31 SDO0 O Audio serial data output pin 0 It leaves to open when if it is unused. Push-pull output 32 LRCKO O LR clock output pin It leaves to open when if it is unused. Push-pull output 33 BCKO O Bit clock output pin It leaves to open when if it is unused. Push-pull output 3 Schmitt input 5V tolerant 2005-09-28 TC94A48FG Pin No. Symbol I/O Function 34 MCKO O System clock output pin It leaves to open when if it is unused. Push-pull output 35 GPO1 O General-purpose output pin 1 It leaves to open when if it is unused. Open-drain output 5V tolerant 36 GPO0 O General-purpose output pin 0 It leaves to open when if it is unused. Open-drain output 5V tolerant 37 GND － Digital ground pin 38 VDD － Remarks Digital power pin 39 GPI1 I General-purpose input pin 1 It connects to GND or VDD pins when if it is unused this pin. 40 GPI0 I General-purpose input pin 0 It connects to GND or VDD pins when if it is unused this pin. Schmitt input 5V tolerant 41 /MICS I Microcontroller interface: Chip select signal input pin Schmitt input 5V tolerant 42 /MICK I 43 /MIDIO I/O Microcontroller interface: Data input/output pin Schmitt input / Open-drain output, 5V tolerant 44 /MIACK O Microcontroller interface: Acknowledge signal output pin Open-drain output 5V tolerant 45 MILP I Microcontroller interface: Latch pulse input pin Schmitt input 5V tolerant 46 GNDP － 47 PLLC I 48 VDDP － Microcontroller interface: Clock input pin Schmitt input 5V tolerant Schmitt input 5V tolerant Ground pin for PLL Charge pump for PLL Power pin for PLL 49 BTMD I Boot mode setting pin Schmitt input It is set to “L” when if software specification does not indicate 5V tolerant since there is deference by each program ROMs. 50 MIMD I Microcontroller interface: Mode select input pin Schmitt input 5V tolerant 51 /RST I Reset input pin Schmitt input 5V tolerant 52 VDD － 53 GND － Digital power pin Digital ground pin 54 TEST1 I Test setting pin 1 Usually it connects to GND pins. 55 TEST0 I Test setting pin 0 Usually it connects to GND pins. 56 GNDL － Ground pin for ADC-Lch 57 LIN I ADC-Lch signal input pin 58 AVDL I Reference voltage pin for ADC-Lch 59 VDDA － 60 ADVR I Schmitt input 5V intolerant Schmitt input 5V intolerant Analog power pin for ADC Reference voltage pin for ADC-Rch 61 RIN I ADC-Rch signal input pin 62 GNDR － Ground pin for ADC-Rch 63 GNDX － Ground pin for oscillator circuit 64 XI I Crystal oscillator connecting or clock input pin 5V intolerant Note 1: 5V tolerant pins can have voltage applied even when the power to the device is turned off. 4 2005-09-28 TC94A48FG Description of Operation 1. Timing System The TC94A48FG uses pulses from the XI-XO pins as the reference clock. The system is divided into blocks that use the reference clock directly or by dividing its frequency and blocks that operate on a clock the PLL generates based on the crystal resonation clock. The analog and microcontroller interface blocks operate on the crystal resonation clock while the DSP block operates on the PLL-generated clock. Dividing PLL Crystal Clock for DSP PLL-generated Clock for Analog Block (256fs) Input= 256fs Clock for Analog Block (256fs or 512fs) Timing output to pins (LRCKO,BCKO,MCKO) Divider Crystal precision Figure 1 Timing System MCKO Clock LRCKO BCKO MCKO The system can divide the clock from the crystal and provide three types of clock from output pins. LRCKO, BCKO Clock ADC, DAC Xi ×1/2 ～ ×1/512 fs256 fs128～fs0.5 MAF, ΣΔ Xo ｆxi = 11.2896MHz (44.1kHz×256) Audio I/F MCU I/F ×1/M REFCK VARCK Phase Comp. VCO ×1/Ｊ DSP ×1/Ｎ PLL Figure 2 Block diagram of clock generator circuit 5 2005-09-28 TC94A48FG 1.1 Timing register setting [AIFA] Bit 15-14 Contents Default ＊ 13-12 ＊ 11 ＊ 10 ＊ 9 ＊ 8 ＊ 7-6 ＊ 5-4 ＊ 3-2 ＊ 1-0 ＊ BCKi-1 clock frequency 00 32fs 01 48fs 10 64fs 11 64fs BCKi-0 clock frequency 00 32fs 01 48fs 10 64fs 11 64fs LRCKi-1 polarity Lch=Low (interrupt by fall edge) 0 Lch=High (interrupt by rise edge) 1 LRCKi-0 polarity Lch=Low (interrupt by fall edge) 0 Lch=High (interrupt by rise edge) 1 SDi clock select LRCKi-0/BCKi-0 0 LRCKi-1/BCKi-1 1 SDo clock select 0 LRCKi-0/BCKi-0 1 LRCKi-1/BCKi-1 SDi input format 00 LSB justified 01 MSB justified 10 I2S 11 I2 S SDi input bit clock 00 16bit 01 18bit 10 20bit 11 24bit SDo output format 00 LSB justified 01 MSB justified 10 I2 S 11 I2 S SDo output bit clock 00 16bit 01 18bit 10 20bit 11 24bit Note 2: In 48fs frequency setup of BCKi-1 and BCKi-0, LRCKi/BCKi coresponds only an input, and LRCKo / BCKo does not correspond. 6 2005-09-28 TC94A48FG [MOD_O] Bit 15-12 Default 11 ＊ 10 ＊ 9 ＊ 8 ＊ 7 6 5 ＊ 4 ＊ 3 ＊ 2 ＊ 1 ＊ 0 ＊ Contents Reserved Fixed to “0” SDo3 is used as a general-purpose output Po5. 0 Disable 1 Enable SDo2 is used as a general-purpose output Po4. 0 Disable 1 Enable SDo1 is used as a general-purpose output Po3. 0 Disable 1 Enable SDo0 is used as a general-purpose output Po2. 0 Disable 1 Enable Reserved Fixed to “0” Reserved Fixed to “1” Synchronization of LRCKi and LRCKo 0 Disable 1 Enable BCCMP/BCJMP Enable 0 Disable 1 Enable DAC Enable 0 Disable 1 Enable ADC Enable 0 Disable 1 Enable LRCKo is connected to LRCKi1. 0 It does not connect. 1 It connects. LRCKo is connected to LRCKi0. 0 It does not connect. 1 It connects. 7 2005-09-28 TC94A48FG [TMGA] Bit 15-14 Default 13 ＊ 12-7 6 ＊ 5-3 2-0 ＊ Contents Reserved Fixed to “0” DSP clock output select 0 Disable 1 Enable Reserved Fixed to “0” MCKO clock output select 1/1 Xi clock 0 1 1/2 Xi clock Reserved Fixed to “0” DSP clock divider setting (1/J) 000 1/1 001 1/2 010 1/4 011 1/8 100 1/16 101 1/3 110 1/6 111 Prohibit [TMGB] Bit 15-14 Default ＊ 13 ＊ 12-8 ＊ 7-0 ＊ Contents LRCKo/BCKo clock select 00 FS1/FS32(BCK=fs32) 01 FS1/FS64(BCK=fs64) 10 FS2/FS64(BCK=fs32) 11 FS2/FS128(BCK=fs64) LRCKo/BCKo output clock select 0 Disable 1 Enable Reference clock divider setting (1/M) 00h 1/1 01h 1/2 ・ ・ 09h 1/10 ・ 1Fh 1/32 Variable clock divider setting (1/N) 00h 1/1 01h 1/2 ・ ・ 3Fh 1/64 ・ FFh 1/256 8 2005-09-28 TC94A48FG 1.2 Timing Output LRCKO / BCKO Pin Output Settings Mode 0 1 2 3 4 LRCKO Pin Output Fixed to GND 1fs 1fs 2fs 2fs BCKO Pin Output Fixed to ground 32fs 64fs 64fs 128fs Remarks Initial Value MCKO Pin Output Settings Mode 0 1 2 Note 3: 1.3 MCKO Pin Output Fixed to GND XCKI (=XI) 0.5 × XCKI Remarks It can be initialized by reset. Undefined until set by microcontroller or built-in DSP program A setup of a timing output is performed by the built-in firmware. Example of oscillator circuit The example of a circuit at the time of the crystal oscillator use in an oscillation part is shown in figure 3. Crystal oscillator connection XI 64 1 XO 11.2896MHz 1MΩ 22pF 22pF Figure 3 Example of oscillator circuit Example of PLL circuit A PLL circuit can consist of connecting LPF to a PLLC terminal easily. The example of a circuit is shown in figure 4. Phase Comp. PLLC VDDP VCO GNDP 1.4 46 47 48 0.1uF 220Ω 47uF 0.01uF VDD Figure 4 Example of PLL circuit The above-mentioned external constant is a reference value. It may change with application. 9 2005-09-28 TC94A48FG 1.5 Audio Input/Output Format 1.5.1 Audio Serial Data Input Format The TC94A48FG supports MSB-first input only. In slave mode, it supports all setting formats for the number of bit clock slots. In master mode, it does not support 24 slots. M = MSB Number Data Word MO Length of DE (bit) Slots 0 16 16 L don't care(invalid data, padded with "0" when read by DSP = LSB internal firmware) Timing Chart Format MSBjustified (LSBjustified) Remarks M Initial Value L 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 I2S 1 M 15 MSBjustified 2 M 4 16 0 L 1 5 3 L 1 4 1 3 1 2 1 1 1 0 9 LSBjustified 8 7 6 5 4 3 2 1 0 M L 15 0 Unavailable in master mode(Note) I2S 24 5 24 MSBjustified (LSBjustified) M L 15 0 M L 23 0 I2S 6 M L 23 MSBjustified 7 0 M L 15 8 16 0 LSBjustified M L 15 I2S 9 M L 15 32 MSBjustified 10 0 M L 23 11 0 24 0 LSBjustified M L 23 12 0 I2S M L 23 0 Note 4: These formats cannot be used in master mode (when LRCK and BCK are supplied to external devices). 10 2005-09-28 TC94A48FG 1.5.2 Audio Serial Data Output Format The valid part of data is the same as that for the input format. The TC94A48FG supports MSB-first output only. In slave mode, it supports all setting formats for the number of bit clock slots. In master mode, it does not support 24 slots. M MO DE ＝MSB L Number Data Word Length of (bits) SLOT ＝LSB ＝fixed to “0” (data sent from DSP is ignored) Format Timing Chart Remarks Initial value 0 M 16 L 15 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 I2S 1 M 15 L 0 2 M L 1 5 3 4 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 16 M L 15 0 Unavailable in master mode(Note) I2S 24 M L 15 0 5 24 M L 23 0 I2S 6 M L 23 0 7 M L 15 8 0 16 M L 15 0 I2S 9 M L 15 32 0 10 M L 23 11 0 24 M L 23 12 0 I2S M L 23 0 Note 5: These formats cannot be used in master mode (when LRCK and BCK are supplied to external devices). 11 2005-09-28 TC94A48FG The audio input block and output block support different clock settings. Input and output port settings are, however, shared as follows: LR Clock Setting for Input Block Mode Master Mode Slave Mode Signal Signal delivered to LRCKO pin (crystal resonation clock divided) LRCKI0 pin input LRCKI1 pin input Bit Clock Setting for Input Block Mode Master Mode Slave Mode Signal Signal delivered to BCKO pin (crystal resonation clock divided) BCKI0 pin input BCKI1 pin input LR Clock Setting for Output Block Mode Master Mode Slave Mode Signal Signal delivered to LRCKO pin (crystal resonation clock divided) LRCKI0 pin input LRCKI1 pin input Bit Clock Setting for Input Block Mode Master Mode Slave Mode Signal Signal delivered to BCKO pin (crystal resonation clock divided) BCKI0 pin input BCKI1 pin input 12 2005-09-28 TC94A48FG 2. Microcontroller Interface The TC94A48FG can exchange data with a microcontroller in either normal transmission mode or I2C mode. It uses the MIMD pin to select the mode and inputs/outputs data in MSB-first format. Table 1 shows the features supported and the pins used in each mode. Table 2 shows the bit composition of a 24-bit command. Note 6: This data sheet shows general control methods. Refer to the separate program explanation data sheet for a complete command list or detailed description of control methods. Pins Used and Features Supported in Normal Transmission Mode and I2C Mode Table 1 Transmission Mode Pin Normal Transmission Mode (MIMD=L) I2C Mode (MIMD=H) Function Function Input/Output /MICS Input Chip select Input Not used (fixed to “L”) MILP Input Latch pulse input Not used (fixed to “L”) Data input / output Data input / output (SDA) Input /MIDIO Output (open-drain) /MICK Input, Input / Output (I2C mode) Clock input Clock input (SCL) /MIACK Output (open-drain) Acknowledge output Not used Note 7: The input High voltage for these pins should be VDD-0.2 V to 5.5V. Note 8: The open-drain /MIDIO and /MIACK pins require external pull-up resistors. 2 In I C mode, the /MICK pin also requires a pull-up resistor. The pulled-up voltage for these pins should be VDD-0.2V to 5.5V. 2 Note9: The I C bus write address is 30 h and read address is 31h. Table 2 Bit Composition of a 24-bit Command Bit 23-8 Function Remarks Refer to the command list in the program explanation data sheet. 16-bit address 7 Not used 6 Start program RAM boot "1" starts program RAM boot. 5 Specify soft reset "1" triggers a soft reset. 4 Specify read or write (R/W) "1" specifies a read. ― 0h” ; 1word 3-0 Set the number of words to be transmitted ↓ “7h” ; 8words 13 2005-09-28 TC94A48FG 2.1 2.1.1 Normal Transmission Mode Data Transfer Format in Normal Transmission Mode Figure 1 shows the data transfer format in normal transmission mode. In normal transmission mode, the system first drives /MICS low and then checks that /MIACK is low before transferring a 24-bit command MSB first. It cannot transfer data if /MIACK is high. The system then reads or writes as many 24-bit data words (one to eight) as specified with the 24-bit command and finally drives /MICS high. For a read, it should also make sure that /MIACK is low after transferring a 24-bit command because /MIACK becomes high temporarily after the command is transferred. 24bit DATA(1～8word) /MICS /MIACK /MILP /MICK /MIDIO COMMAND(24bit) DATA(24bit) DATA(24bit) Figure 5(a) Data Transfer Format in Normal Transmission Mode 2.1.2 (1) Data Transfer Method in Normal Transmission Mode Program boot and program start The TC94A48FG has 1k-word RAM assigned to program addresses 000h to 3FFh, in which 000h to 003h are interrupt vector addresses. To enable the TC94A48FG to operate, a program must be booted to an interrupt vector address. If you want to store a program in the area from 004h to 3FFh, a program loading process must follow the interrupt vector address. For a program boot, the 24-bit command transferred upon a reset must have the program RAM boot start bit and soft reset bit set to "1" (command = xxxx60h). The command must be followed by 16-bit program data, set in lower bits in 24-bit data. The write address is automatically incremented (by one) from the command (000h). The program boot completes once /MICS is driven high upon transferring the required number of words. The write address for a program boot always starts from the command (000h). To start the program, transfer a 24-bit command with the soft reset bit cleared and then drive /MICS high without transferring data. Figure 6 shows the program boot and program start procedure. 14 2005-09-28 TC94A48FG Hard reset (or soft reset) ／ＭＩＣＳ＝ ”Ｌ ” Check ＭＩＡＣＫ＝ =”Ｌ ” If ＭＩＡＣＫ＝ ”Ｈ ” , wait until ＭＩＡＣＫ＝ ”Ｌ ” Write 24-bit command (program boot = 000060h) Set the program boot and soft reset bits to “H” Write program data (16bits at address 000h) Program data stored in lower 16bits Bootable for address of up to 3FFh Write program data (16bits at address 001h) Write program data (Address 3FEh) Write program data (Address 3FFh) ／ＭＩＣＳ＝ ”Ｈ ” Program boot finished ／ＭＩＣＳ＝ ”Ｌ ” Check ＭＩＡＣＫ＝ =”Ｌ ” If ＭＩＡＣＫ＝ ”Ｈ ” , wait until ＭＩＡＣＫ＝ ”Ｌ ” Write 24-bit command (soft reset off = 000000h) ／ＭＩＣＳ＝ ”Ｈ ” Start program Figure 6 Program Boot and Program Start Procedure 15 2005-09-28 TC94A48FG (2) Writing 24-bit data When the host microcontroller writes data to the TC94A48FG during the execution of a program, it sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "0" and sets the number of words to be written. Then, it transfers the 24-bit command, followed by a required number of 24-bit data words. Figure 7 shows the 24 bit data write procedure. ／ＭＩＣＳ＝“Ｌ” Check MＩＡＣＫ = “Ｌ” (If MIACK = “H” , wait until MIACK = “L”) Write 24-bit command (data write = xxxx0xh) Set 16-bit address and the number of words to be transferred. Write 24-bit data (1) Can write up to eight 24-bit data words Write 24-bit data (2) Write 24-bit data (n) ／ＭＩＣＳ＝“Ｈ” Data write finished Figure 7 shows the 24-bit data write procedure. 16 2005-09-28 TC94A48FG (3) Reading 24-bit data When the host microcontroller reads data from the TC94A48FG during the execution of a program, it sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "1" and sets the number of words to be read. Then, it transfers the 24-bit command, check that /MIACK = "L", and read a required number of 24-bit data words. The host microcontroller should check that /MIACK = "L" because it has to wait until the data to be read is set in the data buffer. Figure 8 shows the 24 bit data read procedure. ／ＭＩＣＳ＝“Ｌ” Check ＭＩＡＣＫ＝“Ｌ” （If MＩＡＣＫ＝“Ｈ” , wait until MIACK = “Ｌ”) Transfer 24-bit command (data read = xxxx1xh) Set 16 bit address and the number of words to be transferred. Check ＭＩＡＣＫ＝“Ｌ” （If MＩＡＣＫ＝“Ｈ” , wait until MIACK = “Ｌ”) Can read up to eight 24-bit data word Read 24-bit data (1) Read 24-bit data (2) Read 24-bit data (n) ／ＭＩＣＳ＝“Ｈ” Data read finished Figure 8 shows the 24-bit data read procedure. 17 2005-09-28 TC94A48FG (4) Triggering and terminating a soft reset A soft reset is required before the system can start a program after program boot or restart a program. A 24-bit command with its soft reset bit set to "1" triggers a soft reset and a command with the bit cleared terminates a soft reset. When trigging or terminating a soft reset, drive /MICS high after transferring the 24-bit command because no data needs to follow the command. Figure 9 shows the procedure for trigging or terminating a soft reset. ／ＭＩＣＳ＝“Ｌ” Check MＩＡＣＫ = “Ｌ” (If MIACK = “H” , wait until MIACK = “L”) If a malfunction occurs, perform a hard reset prior to a soft reset. “1” triggers a reset “0” terminates a reset Transfer 24-bit command (soft reset ON/OFF = 0000x0h) ／ＭＩＣＳ＝“Ｈ” Soft reset triggered or terminated Figure 9 Procedure for Trigging or Terminating a Soft Reset 18 2005-09-28 TC94A48FG 2 2.2 I C Bus Mode 2 2.2.1 Data Transfer Format in I C Bus Mode Figure 10 shows the data transfer format in I2C bus mode. In I2C bus mode, the host microcontroller first transfers an I2C address (write = 30h) and then checks that the ACK bit is low. If the ACK bit is high, it retransmits a start condition (without transmitting a stop condition) and then transfers an I2C address of 30h. After transferring an I2C address, the host microcontroller transfers a 24-bit command. When the host microcontroller writes data to the TC94A48FG, it writes as many 24-bit data words as specified with the 24-bit command (1 to 8 words) and then transfers an end condition. When the host microcontroller reads data from the TC94A48FG, it transfers a 24-bit command and then, without transmitting an end condition, transfers an I2C address (read =31h) and check that the ACK bit is low. If the ACK bit is high, the host microcontroller retransmits a start condition (without transmitting a stop condition) and then transfers an I2C address of 31h. After checking that the ACK bit is low, the host microcontroller reads as many 24-bit data words as specified with the 24-bit command (1 to 8 words). During a read, the host microcontroller sets the ACK bit to low after reading every eight bits. The ACK bit accompanying the last eight bits must be set to high, after which the host microcontroller transmits a stop condition. When transferring only a 24-bit command without reading or writing data, transmit an end condition after transferring the command. Figures 11 to 13 show the data transfer formats for writing, reading, and transferring a command only. SDA I2C Address(30h) DATA Hi(8bit) R/W ACK ACK DATA Mid(8bit) DATA Low(8bit) ACK SCL I2C Address 24bit Command and 24bit DATA (1～8word) Start Condition Stop Condition Figure 10 Data Transmission Format in I2C Mode (30h) 24bit Write DATA(1word～ 8word) 24bit COMMAND START I2C Address W A COMMAND(H) A COMMAND(M) A COMMAND(L) A DATA(H) A DATA(M) A DATA(L) A STOP Each ACK signal sent from TC94A48FG to Host An interval of at least 1fs(32μs@1fs=32kHz) is required before next START Figure 11 Format for Writing (30h) START I2C Address 24bit COMMAND W A COMMAND(H) A COMMAND(M) A 24bit Read DATA(1word～ 8word) (31h) COMMAND(L) A START I2C Address R A RD(H) A RD(M) A RD(L) A STOP Each ACK signal sent from TC94A48FG to Host An interval of at least 1fs(32μs@1fs=32kHz) is required before next START These ACK signals are sent from host to TC94A48FG This ACK signal is set to “H” by the Host Figure 12 Format for Reading (30h) 24bit COMMAND START I2 C Address W A COMMAND(H) A COMMAND(M) A COMMAND(L) A STOP Each ACK signal sent from TC94A48FG to Host Figure 13 Format for Transferring a Command Only 19 2005-09-28 TC94A48FG 2.2.2 (1) 2 Data Transfer Method in I C Mode Program boot and program start The TC94A48FG has 1k-word RAM assigned to program addresses 000h to 3FFh, in which 000h to 003h are interrupt vector addresses. To enable the TC94A48FG to operate, a program must be booted to an interrupt vector address. If you want to store a program in the area from 004h to 3FFh, a program loading process must follow the interrupt vector address. For a program boot, the 24-bit command transferred upon a reset must have the program RAM boot start bit and soft reset bit set to "1" (command = xxxx60h). The command must be followed by 16-bit program data, set in lower bits in 24-bit data. The write address is automatically incremented (by one) from the command (000h). The program boot completes once an end condition is transmitted upon transferring the required number of words. The write address for a program boot always starts from the command (000h). To start the program, transfer a 24-bit command with the soft reset bit cleared and then transmit an end condition without transferring data. Figure 14 shows the program boot and program start procedure. 20 2005-09-28 TC94A48FG Hard reset (or soft reset) ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ If ACK = “H” , restart from START condition. Transfer I2C Ａｄｄｒｅｓｓ（３０ｈ） Check ACK bit = “L” Set the program boot and soft reset bits to “H” Write 24-bit command (program boot = 000060h) Write program data (16 bits at address 0000h) Program data stored in lower 16bits Bootable for address of up to 3FFh Write program data (16 bits at address 0001h) Write program data (16bits at address 3FEh) Write program data (16bits at address 3FFh) Program boot finished ＳＴＯＰ Ｃｏｎｄｉｔｉｏｎ ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ If ACK = “H” , restart from START condition. Transfer I2C Ａｄｄｒｅｓｓ（３０ｈ） Check ACK bit = “L” Write 24-bit command (soft reset OFF = 000000h) ＳＴＯＰ Ｃｏｎｄｉｔｉｏｎ Start program Figure 14 Program Boot and Program Start Procedure 21 2005-09-28 TC94A48FG (2) Writing 24-bit data When the host microcontroller writes data to the TC94A48FG during the execution of a program, it sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "0" and sets the number of words to be written. Then, it transfers the 24-bit command, followed by a required number of 24-bit data words. An interval of at least 1fs(32μs@1fs=32kHz) is required before next started. Figure 15 shows the 24 bit data write procedure. ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ If ACK = “H” , restart from START condition. Transfer I2C Ａｄｄｒｅｓｓ（３０ｈ） Check ACK bit = “L” Set 16-bit address and the number of words to be transferred. Write 24-bit command (data write = xxxx0xh) Write 24-bit data (1) Can write up to eight 24-bit data words Write 24-bit data (2) Write 24-bit data (n) ＳＴＯＰ Ｃｏｎｄｉｔｉｏｎ Data write finished Figure 15 shows the 24-bit Data Write Procedure. 22 2005-09-28 TC94A48FG (3) Reading 24-bit data When the host microcontroller reads data from the TC94A48FG during the execution of a program, it sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "1" and sets the number of words to be read. Then, it transfers the 24-bit command, waits about 1fs, and then transfers an I2C address of 31h, followed by a start condition. Finally, it reads a required number of 24-bit data words. During a read, the host microcontroller should set the ACK bits to low but the ACK bit accompanying the last eight bits of data must be high, thus causing the TC94A48FG to relinquish the SDA bus line so that the host microcontroller can transmit a stop condition. The host microcontroller should wait about 1fs after transferring a command because it has to wait until the data to be read is set in the data buffer of the TC94A48FG. Figure 16 shows the 24-bit data read procedure. ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ If ACK = “H” , restart from START condition. Transfer I2C Ａｄｄｒｅｓｓ (30h) Check ACK bit = “L” Set a 16-bit address and the number of words to be transferred. Transfer 24-bit command (data read = xxxx1xh) Wait about 1fs ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ If ACK = “H” , restart from START condition. Transfer I2C Ａｄｄｒｅｓｓ (31h) Check ACK bit = “L” Read 24-bit data (1) Can read up to eight 24-bit data words Read 24-bit data (2) Read 24-bit data (n) Set the last ACK bit to “H” ＳＴＯＰ Ｃｏｎｄｉｔｉｏｎ Data read finished Figure 16 shows the 24-bit Data Read Procedure 23 2005-09-28 TC94A48FG (4) Triggering and terminating a soft reset A soft reset is required before the system can start a program after program boot or restart a program. A 24-bit command with its soft reset bit set to "1" triggers a soft reset and a command with the bit cleared terminates a soft reset. When trigging or terminating a soft reset, transmit a stop condition after transferring the 24-bit command because no data needs to follow the command. Figure 17 shows the procedure for triggering or terminating a soft reset. ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ If ACK = “H” , restart from START Condition. If a system crash(malfunction) occurs, perform a hard reset prior to a soft reset. Transfer I2C Ａｄｄｒｅｓｓ（３０ｈ） Check ACK bit = “L” Transfer 24-bit command (soft reset ON/OFF = 0000x0h) “1” triggers a reset “0” terminates a reset ＳＴＯＰ Ｃｏｎｄｉｔｉｏｎ Soft reset triggered or terminated Figure 17 Procedure for Triggering or Terminating a Soft Reset 3. Write and Read Commands The specifications of write and read commands depend on the built-in program. For details, refer to the program explanation data sheet. 24 2005-09-28 TC94A48FG Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Supply Voltage VDD −0.3~4.0 V Input voltage 1 Vin1 −0.3~VDD + 0.1 V Input voltage 2 (Note10) Vin2 −0.3~+ 5.5 V Power dissipation PD 400 mW Operating temperature Topr −40~+85 °C Storage temperature Tstg −55~+150 °C Note10: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, /MICS, /MICK, /MIDIO, MILP, BTMD, MIMD, /RST Electrical Characteristics (unless otherwise specified, Ta = 25°C, VDD = VDDX = VDD12 = VDD3 = VDD45 = VDD6 = VDDP = VDDA = 3.3V) DC Characteristics Symbol Test circuit Operating supply voltage VDD ⎯ Operating frequency range fopr ⎯ PLL clock frequency range fplo ⎯ Operating supply current IDD ⎯ Symbol Test circuit Characteristics Test Condition Min. Typ. Max. Unit Ta = −40~85°C 3.0 3.3 3.6 V Using PLL for DSP clock 30 ⎯ 75 MHz fopr =75MHz (75MIPS) 90 ⎯ 225 MHz ⎯ 90 100 mA Min. Typ. Max. Unit 2.8 ⎯ ⎯ ⎯ ⎯ 0.5 Clock pins (XI,XO) Characteristics Input voltage(1) Output voltage(1) “H” level VIH1 “L” level VIL1 “H” level IOH1 “L” level IOL1 ⎯ ⎯ Test Condition XI pin VOH = 2.8 V VOL = 0.5 V XO pin ⎯ ⎯ −2.5 3.0 ⎯ ⎯ Min. Typ. Max. 2.8 ⎯ ⎯ ⎯ ⎯ 0.5 V mA Input pins Characteristics Symbol “H” level VIH2 “L” level VIL2 Input leakage “H” level IIH2 current “L” level IIL2 Input voltage(2) Test circuit ⎯ ⎯ Test Condition (Note 11) VIN = VDD (Note 11), ⎯ ⎯ 10 VIN = 0 V (Note 12) −10 ⎯ ⎯ Unit V µA Note 11: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, /MICS, /MICK, /MIDIO, MILP, BTMD, MIMD, /RST, TEST0~1, PLLC Note 12 : XI 25 2005-09-28 TC94A48FG Output pins Characteristics Output current(2) Output current(3) Output current(4) Symbol “H” level IOH2 “L” level IOL2 “H” level IOH3 Test circuit Test Condition ⎯ ⎯ Min. Typ. Max. VOH = 2.8 V (Note 13) ⎯ ⎯ −5 VOL = 0.5 V (Note 13) 5 ⎯ ⎯ VOH = 2.8 V (Note 14) ⎯ ⎯ −3 “L” level IOL3 VOL = 0.5 V (Note 14) 3 ⎯ ⎯ “L” level IOL4 ⎯ VOL = 0.5 V (Note 15) 5 ⎯ ⎯ IOZ5 ⎯ VOH = VDD (Note 15) ⎯ ⎯ ±10 Output-off leakage current Unit mA µA Note 13: SDO0~3, LRCKO, BCKO (push-pull output) Note 14: MCKO (push-pull output) Note 15: GPO0~1, /MIDIO, /MIACK (open-drain output) 26 2005-09-28 TC94A48FG AC Characteristics <Common test conditions unless otherwise specified> • The gain through the firmware is 0 dB (pass-through), except for +2 dB for DC-cut-HPF. • VDD (for all power supplies) = 3.3V, Ta = 25°C • Test circuit MCU Digital SG/Analyzer I/F 10kΩ 10kΩ 10kΩ 10kΩ 0.01uF /MICS GPI0 GPI1 38 37 36 35 34 65 33 BCKO 39 GPO1 40 MCKO 41 GPO0 42 VDD 43 GND 44 /MICK PLLC BTMD 50 MIMD 45 /MIDIO 46 MILP 47 /MIACK 48 GNDP 39 49 VDDP 220Ω 39 32 LRCKO SDO0 31 51 /RST SDO1 30 52 VDD SDO2 29 53 GND SDO3 28 54 TEST1 BCKI0 27 BCKI1 26 55 TEST0 Lch AGND 1kΩ 4.7μF 47μF 47μF 1kΩ 2200pF 4.7μF LRCKI0 25 TC94A48FG 57 LIN 2200pF Rch 56 GNDL LRCKI1 24 58 ADVL SDI0 23 59 VDDA SDI1 22 60 ADVR SDI2 21 61 RIN SDI3 20 62 GNDR GND 19 VDD1 DAO1 GND12 DAO2 VDD23 DAO3 GND3 VRI GND4 DAO4 VDD45 DAO5 GND56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 64 XI VDD6 17 DAO6 VDDX VDD 18 XO 63 GNDX 16 47uF 1MΩ 22pF Analog VDD Analog GND 22pF Digital Digital VDD GND 270Ω 2200pF 10μF 10kΩ 270Ω 270Ω 270Ω 270Ω 270Ω 2200pF 2200pF 10μF 10μF 2200pF 2200pF 10μF 10μF 2200pF 10μF 10kΩ 10kΩ 10kΩ DAC1 DAC2 27 10kΩ DAC3 DAC4 10kΩ DAC5 DAC6 2005-09-28 TC94A48FG AD Converter: LIN and RIN pin input, Vin_ref: 1 kHz, 800 mVrms (unless otherwise specified), SDO0 pin output monitored Characteristics Symbol Test Condition Min. Typ. Max. Unit Maximum input signal Vin Input level that drives ADC output to digital full scale. ⎯ ⎯ 800 mVrms Input impedance Zin Each of LIN and RIN pins 20 27 34 kΩ S/N ratio S/Na A-Weight, Input AC shorted, Crystal: 11.2896 MHz 87 93 ⎯ THD + N THDa 20 kHz LPF, Crystal: 11.2896 MHz ⎯ −83 −77 Crosstalk CTa 20 kHz LPF, Lch to Rch/ Rch to Lch, Crystal: 11.2896 MHz ⎯ −85 −78 Dynamic range DRa A-Weight, -60dB for Vin_ref input, Crystal: 11.2896 MHz 87 93 ⎯ L to R gain error Vdlr −0.5 0 0.5 dB DA Converter: SDO0 to SDO3 pin input, SDI0_ref = 0 dBFS, 1 kHz (unless otherwise specified), DAO1 to DAO6 pin output monitored. Characteristics Output signal level Symbol Test Condition Min. Typ. Max. Unit Ao Output voltage at digital full-scale input 790 830 870 mVrms S/N ratio S/Nd A-Weight, Crystal: 11.2896 MHz 90 98 ⎯ THD + N THDd 20 kHz LPF Crystal: 11.2896 MHz ⎯ −88 −75 Crosstalk CTd 20 kHz LPF, Crystal: 11.2896 MHz ⎯ −90 −83 Dynamic range DRd A-Weight Crystal: 11.2896 MHz 88 95 ⎯ Channel-to-channel gain error Vddo DAO1~DAO6 pin output monitored. −0.5 0 0.5 28 dB 2005-09-28 TC94A48FG Timing Clock input pin (XI) Characteristics Clock cycle Symbol tXI Test Condition fs=32kHz~48kHz, 256fs input Min. Typ. Max. 80.0 88.6 124.0 Unit Clock “H” duration tXIH ⎯ 40.0 44.3 62.0 Clock “L” duration tXIL ⎯ 40.0 44.3 62.0 Symbol Test Condition Min. Typ. Max. Unit ns Reset pin (/RST) Characteristics Standby time tRRS ⎯ 10 ⎯ ⎯ ms Reset pulse width tWRS ⎯ 1.0 ⎯ ⎯ µs Max. Unit Note 16: The /RST pin must be driven low at power-on. Audio Serial Interface (BCKI0~1, BCKO, LRCKI0~1, LRCKO, SDI0~3, SDO0~3) Characteristics Symbol Test Condition Min. Typ. LRCKIx setup time tLBS CL = 30 pF 75 ⎯ ⎯ LRCKIx hold time tLBH −75 ⎯ 75 SDIx setup time tSDI fs = 48 kHz or lower BCKI0 and BCKI1 input: 64 fs or lower 50 ⎯ ⎯ SDIx hold time tHDI 50 ⎯ ⎯ BCKIx clock cycle tBCK 300 ⎯ ⎯ BCKIx clock “H” duration tBCH 150 ⎯ ⎯ BCKIx clock “L” duration tBCL 150 ⎯ ⎯ SDOx output delay(1) tDO1 CL = 30 pF ⎯ ⎯ 60 SDOx output delay(2) tDO2 CL = 30 pF ⎯ ⎯ 60 LRCKO output delay tDCLR CL = 30 pF ⎯ ⎯ 40 29 ns 2005-09-28 TC94A48FG Microcontroller Interface Normal Transmission Mode (/MICS, /MICK, /MIDIO, MILP, /MIACK) Characteristics Symbol Test Condition Min. Typ. Max. Unit tSTB ⎯ 20 ⎯ ⎯ ms /MICS fall to /MICK rise setup time t1 ⎯ 0.5 ⎯ ⎯ /MIACK fall to /MICK rise setup time t2 ⎯ 0.5 ⎯ ⎯ /MICK clock cycle t3 ⎯ 1.0 /MICK “L” duration t4 ⎯ 0.5 ⎯ ⎯ /MICK “H” duration t5 ⎯ 0.5 ⎯ ⎯ /MICK rise to /MILP fall setup time t6 ⎯ 0.5 ⎯ ⎯ MILP “L” duration t7 ⎯ 0.5 ⎯ ⎯ /MIDIO input data setup time t8 ⎯ 0.5 ⎯ ⎯ /MIDIO input data hold time t9 ⎯ 0.5 ⎯ ⎯ /MIDIO output data delay t10 ⎯ ⎯ ⎯ 0.5 /MICS “H” duration t11 ⎯ 0.5 ⎯ ⎯ /MIACK output delay t12 ⎯ ⎯ ⎯ 1.0 MILP rise to /MICS rise setup time t13 ⎯ 0.5 ⎯ ⎯ Min. Typ. Max. Unit kHz Standby time µs Note 17: The /MIACK output timing and /MIACK "H" duration vary with the firmware. I2C Mode (/MICK, /MIDIO) Characteristics /MICK clock frequency /MICK “H” duration Symbol Test Condition fIFCK CL = 400 pF 0 ⎯ 400 tH CL = 400 pF 0.6 ⎯ ⎯ tL CL = 400 pF 1.3 ⎯ ⎯ Data setup time tDS CL = 400 pF 0.2 ⎯ ⎯ Data hold time tDH CL = 400 pF 0 ⎯ 0.9 Transmission start condition hold time tSCH CL = 400 pF 0.6 ⎯ ⎯ Repeated transmission start condition setup time tSCS CL = 400 pF 0.6 ⎯ ⎯ Transmission end condition setup time tECS CL = 400 pF 0.6 ⎯ ⎯ Data transmission interval /MICK “L” duration tBUF CL = 400 pF 1.3 ⎯ ⎯ 2 tR CL = 400 pF ⎯ ⎯ 0.3 2 tF CL = 400 pF ⎯ ⎯ 0.3 I C rise time I C fall time 30 µs 2005-09-28 TC94A48FG AC Characteristics Measurement Points 1. Clock Pin (XI) XI 50% tXIH tXIL tXI 2. Reset Pin (/RST) 100% VDD 90% 0% 50% /RST tRRS 3. tWRS Audio Serial Interface (LRCKIx, BCKIx, SDIx, LRCKO, BCKO, SDOx, MCKO) XI 50% tDCLR 100% LRCKO 50% 0% tBCK tBCL tBCH LRCKIx/ LRCKO tLBH tLBS BCKIx/ BCKO SDIx tSDI tHDI SDOx tDO1 31 tDO2 2005-09-28 TC94A48FG 4. Microcontroller Interface 4-1. Serial Mode (/MICS, /MICK, /MIDIO, MILP, /MIACK) /RST /MICS tSTB t1 /MICS t2 /MIACK t3 t12 t4 t5 t6 /MICK t7 MILP t8 /MIDIO t9 DATA IN /MIDIO DATA OUT t10 t13 t11 /MICS /MIACK /MICK t7 MILP /MIDIO /MIDIO t6 DATA IN DATA OUT 32 2005-09-28 TC94A48FG 4-2. 2 I C Mode (/MICK, /MIDIO) /RST /MIDIO (SDA) tSTB tBUF /MIDIO (SDA) /MICK (SCL) tSCH tR tL tH 33 tDS tDH tSCS tF tECS 2005-09-28 TC94A48FG Equivalent Circuit Diagrams Type Equivalent Circuit Diagram Description Schmitt Input A Schmitt Input. 5V tolerant. B A voltage can be applied to this pin even when the power supply pin of the TC94A48FG is driven to 0V. Push-pull output. The amplitude is 3.3 V. If external devices require 5V amplitude, perform a level conversion. C Open-drain output This pin must be pulled up to VDD or 5V externally. D Schmitt input and open-drain output This pin must be pulled up to VDD or 5V externally. A voltage can be applied to this pin even when the power supply pin of the TC94A48FG is driven to 0V. E [Caution] When using the pin for input, connect it to an open-drain output pin of an external device. Type A: TEST0, TEST1 Type B: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, BTMD, MILP, /MICK, /MICS, MIMD, /RST Type C: SDO0~3, MCKO, BCKO, LRCKO Type D: GPO0~1, /MIACK Type E: /MIDIO 34 2005-09-28 TC94A48FG Package Dimensions L Q F P 6 4 - P- 1 0 1 0 - 0 . 5 0 E U n it: m m (Note) Palladium plate Weight : 0.4g (typ.) 35 2005-09-28 TC94A48FG 36 2005-09-28