TCD1709D TOSHIBA CCD Linear Image Sensor CCD (Charge Coupled Device) TCD1709D The TCD1709D is a high sensitive and low dark current 7500 pixels CCD image sensor. The sensor is designed for facsimile, imagescanner and OCR. The device contains a row of 7500 pixels photodiodes which provide a 24 lines/mm (600DPI) across a A3 size paper. The device is operated by 5-V (pulse), and 12-V power supply. Features · Number of image sensing pixels: 7500 pixels · Image sensing pixel size: 7 µm by 7 µm on 7-µm center · Photo Sensing Region : High sensitive and low voltage dark signal pn photodiode · Clock: CMOS 5-V drive · Power supply voltage: 12-V power supply · Package: 68-pin CERDIP Weight: 16.0 g (typ.) Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Clock pulse voltage Vf Shift pulse voltage VSH Reset pulse voltage VRS Clamp pulse voltage VCP Power supply voltage VOD −0.3 to 15 Operating temperature Topr 0 to 60 °C Storage temperature Tstg −25 to 85 °C −0.3 to 8 V Note 1: All voltages are with respect to SS pins (ground). 1 2002-11-14 TCD1709D Pin Connections (top view) 68 CP 67 RS 3 66 SS OD 4 65 f2B f1A1 5 64 f1A2 f2A1 6 63 f2A2 NC 7 62 NC NC 8 61 NC NC 9 60 NC NC 10 59 NC NC 11 58 NC NC 12 57 NC NC 13 56 NC NC 14 55 NC NC 15 54 NC NC 16 53 NC NC 17 52 NC NC 18 51 NC f2A3 19 50 f2A4 f1A3 20 49 f1A4 f2B 21 48 OD SH 22 47 SS OS2 1 OS1 2 OD 1 RS 23 46 OS4 CP 24 45 OS3 NC 25 44 NC NC 26 43 NC NC 27 42 NC NC 28 41 NC NC 29 40 NC NC 30 39 NC NC 31 38 NC NC 32 37 NC NC 33 36 NC NC 34 35 NC 7500 2 2002-11-14 TCD1709D Circuit Diagram OS2 SS CP RS f2B 66 68 67 f2A2 f2A4 f1A4 OD SS 64 63 50 49 48 47 65 Signal output buffer 1 f1A2 CCD analog shift register 2 Signal output buffer CCD analog shift register 4 22 SH Photo diode …. D28 D27 D26 S7498 S7499 S7500 D127 D126 D126 D127 S1 S2 S3 D26 D27 D28 Shift gate 2 …. 46 OS4 Shift gate 1 OS1 Signal output buffer 2 CCD analog shift register 1 Signal output buffer CCD analog shift register 3 3 4 5 6 19 20 OD OD f1A1 f2A1 f2A3 f1A3 21 23 24 f2B RS CP 45 OS3 Pin Names f1A1, 2, 3, 4 Clock (phase 1) f2A1, 2, 3, 4 Clock (phase 2) f2B Last stage clock (phase 2) SH Shift gate RS Reset gate CP Clamp gate OS1 Output signal 1 OS2 Output signal 2 OS3 Output signal 3 OS4 Output signal 4 OD Power supply SS Ground NC No connect 3 2002-11-14 TCD1709D Optical/Electrical Characteristics (Ta = 25°C, VOD = 12 V, VB= VSH = VRS = VCP = 5 V (Pulse), fB = 1 MHz, tINT (integration time) = 10 ms, light source = daylight fluorescent lamp, load resistance = 100 kW W) Characteristics Symbol Min Typ. Max Unit R 12 15 18 V/(lx･s) PRNU ¾ 3 10 % (Note 2) PRNU (3) ¾ 5 12 mV (Note 8) Sensitivity Photo response non uniformity Note VSAT 1.5 2.0 ¾ V (Note 3) Saturation exposure SE 0.08 0.16 ¾ lx･s (Note 4) Dark signal voltage VDRK ¾ 1 3 mV (Note 5) Dark signal non uniformity DSNU ¾ 2 6 mV (Note 5) DC power dissipation PD ¾ 800 1040 mW Total transfer efficiency TTE 92 98 ¾ % Output impedance Zo ¾ 0.2 1 kW Dynamic range DR ¾ 2500 ¾ ¾ (Note 6) DC signal output voltage VOS 4.5 6 7.5 V (Note 7) |VOSX-VOSY| ¾ ¾ 300 mV (Note 9) NDs ¾ 0.7 ¾ mV (Note 10) Saturation output voltage DC differential error voltage Random noise Note 2: Measured at 50% of SE (typ.) Definition of PRNU : PRNU = Dc c ´ 100 % Where ? is average of total signal outputs and ,? is maximum deviation from ? under uniform illumination (Channel 1). In the case of 1875 pixels (channel 2, channel 3 and channel 4), the condition is the same as above too. Note 3: VSAT is defined as minimum saturation output voltage of all effective pixels. Note 4: Definition of SE: SE = VSAT (lx･s) R 4 2002-11-14 TCD1709D Note 5: VDRK is defined as average dark signal voltage of all effective pixels. DSNU is defined by the difference between average value (VDRK) and the maximum value of the dark voltage. OS VDRK DSNU Note 6: Definition of DR : DR = VSAT VDRK VDRK is proportional to tINT (integration time). So the shorter tINT condition makes wider DR values. Note 7: DC signal output voltage is defined as follows: OS VOS SS Note 8: PRNU (3) is defined as maximum voltage with next pixel, where measured 5% of SE (typ.) Note 9: DC differential error voltage is defined as follows: Definition of DC differential error voltage = |VOSX − VOSY| VOSX : Maximum DC signal output voltage VOSY : Minimum DC signal output voltage 5 2002-11-14 TCD1709D Note 10: Random noise is defined as the standard deviation (sigma) of the output level difference between two adjacent effective pixels under no illumination (i.e. dark condition) calculated by the following procedure. Output waveform (effective pixels under dark condition) Video output Video output 200 ns 200 ns s pixel n pixel (n + 1) 1) Two adjacent pixels (pixel n and n + 1) in one reading are fixed as measurement points. 2) Each of the output levels at video output periods averaged over 200 nanosecond period to get Vn and Vn + 1. 3) Vn + 1 is subtracted from Vn to get ∆V. ∆V= Vn − Vn + 1 4) The standard deviation of ∆V is calculated after procedure 2) and 3) are repeated 30 times (30 readings). DV = 1 30 å DVi 30 i=1 s= 2 1 30 å DVi - DV 30 i=1 5) Procedure 2), 3) and 4) are repeated 10 times to get 10 sigma values. s= 1 10 å sj 10 j=1 6) I value calculated using the above procedure is observed 2 times larger than that measured relative to the ground level. So we specify the random noise as follows. Random noise = 1 2 I 6 2002-11-14 TCD1709D Operating Condition Characteristics Symbol Min Typ. Max Vf1A Vf2A 4.5 5 5.5 0 ¾ 0.5 4.5 5 5.5 0 ¾ 0.5 4.5 5 5.5 0 ¾ 0.5 4.5 5 5.5 0 ¾ 0.5 4.5 5 5.5 0 ¾ 0.5 VOD 11.4 12 13 V Symbol Min Typ. Max Unit Clock pulse frequency ff ¾ 1 25 MHz Reset pulse frequency fRS ¾ 1 25 MHz CfA ¾ 200 ¾ pF Clock pulse voltage Last stage clock voltage Shift pulse voltage Reset pulse voltage Clamp pulse voltage High level Low level High level Low level High level Low level High level Low level High level Low level Power supply voltage Vf2B VSH VRS VCP Unit V V V V V Clock Characteristics (Ta = 25°C) Characteristics Clock capacitance (Note 11) Last stage clock capacitance CfB ¾ 20 ¾ pF Shift gate capacitance CSH ¾ 40 ¾ pF Reset gate capacitance CRS ¾ 20 ¾ pF Clamp gate capacitance CCP ¾ 20 ¾ pF Note 11: VOD = 12V 7 2002-11-14 *1 *1: RS and CP stopped. OS4 OS3 OS2 OS1 CP RS f2A1, 2, 3, 4 f2B f1A1, 2, 3, 4 SH Timing Chart Dummy outputs (13 pixels ´ 4) 1 line readout period (1939 pixels ´ 4) Dummy outputs (64 pixels ´ 4) S3753 S3754 S3755 S3756 S3757 S3758 S3759 S3760 S7497 S7498 S7499 S7500 D127 D126 D125 D124 D123 D122 D121 D120 D43 D42 D41 D40 D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D5 D4 D3 D2 D1 D0 D1 D3 D5 D0 0 D2 1 D4 2 3 D27 D29 D31 D33 D35 D37 D39 D41 D43 D26 13 D28 14 D30 15 D32 16 D34 17 D36 18 D38 19 D40 20 D42 21 tINT (integration time) Light shild outputs (48 pixels ´ 4) S3751 S3752 22 8 D121 (3 pixels ´ 4) D123 D125 D127 S2 Signal outputs (1875 pixels ´ 4) S4 S3742 S3744 S3746 S3748 S3750 D120 60 D122 61 D124 62 D126 63 S1 64 S3 65 1935 S3743 1934 S3741 S3745 1936 S3747 1937 S3749 1938 2002-11-14 TCD1709D TCD1709D Timing Requirements SH, f1 Timing f2, RS, CP, OS Timing t2 t3 t4 t6 t7 f2B SH t1 t5 t8 f1A t9 t10 RS t15 t16 t17 CP t12 t13 t14 t11 SH, RS, CP Timing OS1 OS2 OS3 OS4 SH t19 RS f1, f2 Cross point t17 t18 t16 f1 CP f2 GND RS, CP period (Note 12) 1.5 V (min) 1.5 V (min) Note 12: RS and CP must be stopped during this period. 9 2002-11-14 TCD1709D Symbol Min Typ. (Note 13) Max Unit Pulse timing of SH and f1A t1, t5 500 1000 ¾ ns SH pulse rise time, fall time t2, t4 0 50 ¾ ns t3 1000 1500 ¾ ns f2B pulse rise time, fall time t6, t7 0 100 ¾ ns RS pulse rise time, fall time t8, t10 0 20 ¾ ns t9 10 100 ¾ ns t11 ¾ 10 ¾ ns t12, t14 0 20 ¾ ns CP pulse width t13 10 200 ¾ ns Pulse timing of f2B and CP t15 0 50 ¾ ns t16 0 0 ¾ t17 10 100 ¾ Pulse timing of SH and CP t18 200 ¾ ¾ ns Pulse timing of SH and RS t19 200 ¾ ¾ ns Characteristics SH pulse width RS pulse width Video data delay time (Note 14) CP pulse rise time, fall time Pulse timing of RS and CP ns Note 13: Measured with fRS = 1 MHz. Note 14: Load resistance is 100 kW. 10 2002-11-14 TCD1709D Caution 1. Electrostatic Breakdown Store in shorting clip or in conductive foam to avoid electrostatic breakdown. CCD Image Sensor is protected against static electricity, but interior puncture mode device due to static electricity is sometimes detected. In handing the device, it is necessary to execute the following static electricity preventive measures, in order to prevent the trouble rate increase of the manufacturing system due to static electricity. a. b. c. Prevent the generation of static electricity due to friction by making the work with bare hands or by putting on cotton gloves and non-charging working clothes. Discharge the static electricity by providing earth plate or earth wire on the floor, door or stand of the work room. Ground the tools such as soldering iron, radio cutting pliers of or pincer. It is not necessarily required to execute all precaution items for static electricity. It is all right to mitigate the precautions by confirming that the trouble rate within the prescribed range. 2. Window Glass The dust and stain on the glass window of the package degrade optical performance of CCD sensor. Keep the glass window clean by saturating a cotton swab in alcohol and lightly wiping the surface, and allow the glass to dry, by blowing with filtered dry N2. Care should be taken to avoid mechanical or thermal shock because the glass window is easily to damage. 3. Incident Light CCD sensor is sensitive to infrared light. Note that infrared light component degrades resolution and PRNU of CCD sensor. 4. Soldering Soldering by the solder flow method cannot be guaranteed because this method may have deleterious effects on prevention of window glass soiling and heat resistance. Using a soldering iron, complete soldering within ten seconds for lead temperatures of up to 260°C, or within three seconds for lead temperatures of up to 350°C. 11 2002-11-14 TCD1709D Package Dimensions Unit: mm Weight: 16.0 g (typ.) 12 2002-11-14 TCD1709D RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 13 2002-11-14