JBT6K48-AS TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic JBT6K48-AS Gate Driver for TFT LCD Panel The JBT6K48-AS is a 240-channel output gate driver for TFT-LCD. Combining the source driver JBT6K47-AS for TFT-LCD panel and the power supply IC JBT6K49-AS enables low power consumption operation. Based on high-speed CMOS, the JBT6K48-AS offers both low power consumption and high-speed operation. Features · LCD panel drive output pins: Switching 220 pins /240 pins output · LCD panel drive output voltage: 13.0 to 33.0 V · Power supply voltage (VDD): 2.5 to 3.6 V · Data transfer method: Bidirectional shift registers · Operating temperature: −20 to 75°C · Package: Gold bump chip · CMOS process · Recommended driver: Source driver JBT6K47-AS for TFT-LCD panel Power supply IC JBT6K49-AS Block Diagram DI CPV U/D OCM /OE1 /OE2 VDDL/R VSSL/R VGGL/R VEEL/R Bidirectional shift registers Input circuit block Control circuit block Output pin switching circuit Output circuit block G1 G3 G2 1 G238 G240 G239 2002-03-06 JBT6K48-AS PAD Specification Item Chip size Size Unit 15470 ´ 1240 mm (1) -7735, 620 (2) 7735, -620 (3) -7735, -620 (4) 7735, 620 Chip end coordinates mm Bump pitch 60 mm Bump height 15 mm Pin Name Numbers of Pin Input pin 96 Output pin 240 TEG pin 16 DUMMY pin 46 (Include DUV, DUG, DU) Alignment mark 2 Note 1: The TEG pin is a test pin reserved for electrical characteristics measurements, and must be left open. Alignment mark specification Pattern prohibited Al Coordinates entry point 50 mm 30 mm 30 mm 30 mm 50 mm 50 mm 30 mm 30 mm 50 mm 30 mm 2 2002-03-06 4 DUV 4 OCM 4 DUG 8 DU VSSL VDDL VEEL 50 50 100 50 50 50 50 20 40 20 40 20 40 105 40 20 40 20 40 20 40 105 · Long-side output PAD (G1 to G240) 40 3 4 U/D 10 20 4 DUG 8 80 4 CPV 12 65 4 DI 20 65 20 65 20 65 20 65 20 65 80 · Long-side power supply PAD (VEEL/R, VDDL/R, VSSL/R) 65 65 4 DU · Long-side input PAD 4 /OE2 · Long-side power supply PAD (VGGL/R) 4 /OE1 · Short-side dummy PAD (DU) 12 8 10 16 4 4 4 DUV JBT6K48-AS Chip size: 15.47 ´ 1.24 mm TEST17 7 Alignment mark_L Output PAD 240 60 mm pitch single layout DU DU G240 TEG G239 VSSR G2 VDDR VGGL 4 G1 VEER PAD Layout VGGR 4 7 DU [Unit: mm] Alignment mark_R 2002-03-06 JBT6K48-AS JBT6K48-AS PAD Coordinates (1) No. Name 1 VEEL -7258 2 VEEL 3 [Unit: mm] X POINT Y POINT No. Name X POINT Y POINT No. Name -482 44 OCM -2701 -7173 -482 45 OCM VEEL -7088 -482 46 4 VEEL -7003 -482 5 VEEL -6918 -482 6 VEEL -6833 7 VEEL 8 -482 87 DU 2364 -482 -2616 -482 88 DU 2449 -482 OCM -2531 -482 89 DU 2534 -482 47 DUV -2311 -482 90 DU 2619 -482 48 DUV -2226 -482 91 TEG1 2848 -482 -482 49 DUV -2141 -482 92 TEG2 2933 -482 -6748 -482 50 DUV -2056 -482 93 TEG3 3018 -482 VEEL -6663 -482 51 U/D -1836 -482 94 TEG4 3103 -482 9 VEEL -6578 -482 52 U/D -1751 -482 95 TEG5 3188 -482 10 VEEL -6493 -482 53 U/D -1666 -482 96 TEG6 3273 -482 11 VEEL -6408 -482 54 U/D -1581 -482 97 TEG7 3358 -482 12 VEEL -6323 -482 55 DUG -1361 -482 98 TEG8 3443 -482 13 VDDL -5948 -482 56 DUG -1276 -482 99 TEG9 3528 -482 14 VDDL -5863 -482 57 DUG -1191 -482 100 TEG10 3613 -482 15 VDDL -5778 -482 58 DUG -1106 -482 101 TEG11 3698 -482 16 VDDL -5693 -482 59 CPV -886 -482 102 TEG12 3783 -482 17 VDDL -5608 -482 60 CPV -801 -482 103 TEG13 3868 -482 18 VDDL -5523 -482 61 CPV -716 -482 104 TEG14 3953 -482 19 VDDL -5438 -482 62 CPV -631 -482 105 TEG15 4038 -482 20 VDDL -5353 -482 63 DI -436 -482 106 TEG16 4123 -482 21 VSSL -5108 -482 64 DI -351 -482 107 VSSR 4343 -482 22 VSSL -5023 -482 65 DI -266 -482 108 VSSR 4428 -482 23 VSSL -4938 -482 66 DI -181 -482 109 VSSR 4513 -482 24 VSSL -4853 -482 67 DU 39 -482 110 VSSR 4598 -482 25 VSSL -4768 -482 68 DU 124 -482 111 VSSR 4683 -482 26 VSSL -4683 -482 69 DU 209 -482 112 VSSR 4768 -482 27 VSSL -4598 -482 70 DU 294 -482 113 VSSR 4853 -482 28 VSSL -4513 -482 71 /OE2 514 -482 114 VSSR 4938 -482 29 VSSL -4428 -482 72 /OE2 599 -482 115 VSSR 5023 -482 30 VSSL -4343 -482 73 /OE2 684 -482 116 VSSR 5108 -482 31 DU -4098 -482 74 /OE2 769 -482 117 VDDR 5353 -482 32 DU -4013 -482 75 /OE1 964 -482 118 VDDR 5438 -482 33 DU -3928 -482 76 /OE1 1049 -482 119 VDDR 5523 -482 34 DU -3843 -482 77 /OE1 1134 -482 120 VDDR 5608 -482 35 DU -3758 -482 78 /OE1 1219 -482 121 VDDR 5693 -482 36 DU -3673 -482 79 DUV 1439 -482 122 VDDR 5778 -482 37 DU -3588 -482 80 DUV 1524 -482 123 VDDR 5863 -482 38 DU -3503 -482 81 DUV 1609 -482 124 VDDR 5948 -482 39 DUG -3261 -482 82 DUV 1694 -482 125 VEER 6323 -482 40 DUG -3176 -482 83 TEST17 1914 -482 126 VEER 6408 -482 41 DUG -3091 -482 84 TEST17 1999 -482 127 VEER 6493 -482 42 DUG -3006 -482 85 TEST17 2084 -482 128 VEER 6578 -482 43 OCM -2786 -482 86 TEST17 2169 -482 129 VEER 6663 -482 4 X POINT Y POINT 2002-03-06 JBT6K48-AS PAD Coordinates (2) No. Name 130 VEER 6748 131 VEER 132 [Unit: mm] X POINT Y POINT No. Name X POINT Y POINT No. Name -482 173 G26 5670 6833 -482 174 G27 VEER 6918 -482 175 133 VEER 7003 -482 134 VEER 7088 -482 135 VEER 7173 136 VEER 137 411 216 G69 3090 411 5610 411 217 G70 3030 411 G28 5550 411 218 G71 2970 411 176 G29 5490 411 219 G72 2910 411 177 G30 5430 411 220 G73 2850 411 -482 178 G31 5370 411 221 G74 2790 411 7258 -482 179 G32 5310 411 222 G75 2730 411 DU 7587 -305 180 G33 5250 411 223 G76 2670 411 138 DU 7587 -205 181 G34 5190 411 224 G77 2610 411 139 DU 7587 -105 182 G35 5130 411 225 G78 2550 411 140 DU 7587 -5 183 G36 5070 411 226 G79 2490 411 141 DU 7587 95 184 G37 5010 411 227 G80 2430 411 142 DU 7587 195 185 G38 4950 411 228 G81 2370 411 143 DU 7587 295 186 G39 4890 411 229 G82 2310 411 144 VGGR 7463 411 187 G40 4830 411 230 G83 2250 411 145 VGGR 7403 411 188 G41 4770 411 231 G84 2190 411 146 VGGR 7343 411 189 G42 4710 411 232 G85 2130 411 147 VGGR 7283 411 190 G43 4650 411 233 G86 2070 411 148 G1 7170 411 191 G44 4590 411 234 G87 2010 411 149 G2 7110 411 192 G45 4530 411 235 G88 1950 411 150 G3 7050 411 193 G46 4470 411 236 G89 1890 411 151 G4 6990 411 194 G47 4410 411 237 G90 1830 411 152 G5 6930 411 195 G48 4350 411 238 G91 1770 411 153 G6 6870 411 196 G49 4290 411 239 G92 1710 411 154 G7 6810 411 197 G50 4230 411 240 G93 1650 411 155 G8 6750 411 198 G51 4170 411 241 G94 1590 411 156 G9 6690 411 199 G52 4110 411 242 G95 1530 411 157 G10 6630 411 200 G53 4050 411 243 G96 1470 411 158 G11 6570 411 201 G54 3990 411 244 G97 1410 411 159 G12 6510 411 202 G55 3930 411 245 G98 1350 411 160 G13 6450 411 203 G56 3870 411 246 G99 1290 411 161 G14 6390 411 204 G57 3810 411 247 G100 1230 411 162 G15 6330 411 205 G58 3750 411 248 G101 1170 411 163 G16 6270 411 206 G59 3690 411 249 G102 1110 411 164 G17 6210 411 207 G60 3630 411 250 G103 1050 411 165 G18 6150 411 208 G61 3570 411 251 G104 990 411 166 G19 6090 411 209 G62 3510 411 252 G105 930 411 167 G20 6030 411 210 G63 3450 411 253 G106 870 411 168 G21 5970 411 211 G64 3390 411 254 G107 810 411 169 G22 5910 411 212 G65 3330 411 255 G108 750 411 170 G23 5850 411 213 G66 3270 411 256 G109 690 411 171 G24 5790 411 214 G67 3210 411 257 G110 630 411 172 G25 5730 411 215 G68 3150 411 258 G111 570 411 5 X POINT Y POINT 2002-03-06 JBT6K48-AS PAD Coordinates (3) No. Name 259 G112 510 260 G113 261 [Unit: mm] X POINT Y POINT No. Name X POINT Y POINT No. Name 411 302 G155 -2070 450 411 303 G156 G114 390 411 304 262 G115 330 411 263 G116 270 411 264 G117 210 265 G118 266 411 345 G198 -4650 411 -2130 411 346 G199 -4710 411 G157 -2190 411 347 G200 -4770 411 305 G158 -2250 411 348 G201 -4830 411 306 G159 -2310 411 349 G202 -4890 411 411 307 G160 -2370 411 350 G203 -4950 411 150 411 308 G161 -2430 411 351 G204 -5010 411 G119 90 411 309 G162 -2490 411 352 G205 -5070 411 267 G120 30 411 310 G163 -2550 411 353 G206 -5130 411 268 G121 -30 411 311 G164 -2610 411 354 G207 -5190 411 269 G122 -90 411 312 G165 -2670 411 355 G208 -5250 411 270 G123 -150 411 313 G166 -2730 411 356 G209 -5310 411 271 G124 -210 411 314 G167 -2790 411 357 G210 -5370 411 272 G125 -270 411 315 G168 -2850 411 358 G211 -5430 411 273 G126 -330 411 316 G169 -2910 411 359 G212 -5490 411 274 G127 -390 411 317 G170 -2970 411 360 G213 -5550 411 275 G128 -450 411 318 G171 -3030 411 361 G214 -5610 411 276 G129 -510 411 319 G172 -3090 411 362 G215 -5670 411 277 G130 -570 411 320 G173 -3150 411 363 G216 -5730 411 278 G131 -630 411 321 G174 -3210 411 364 G217 -5790 411 279 G132 -690 411 322 G175 -3270 411 365 G218 -5850 411 280 G133 -750 411 323 G176 -3330 411 366 G219 -5910 411 281 G134 -810 411 324 G177 -3390 411 367 G220 -5970 411 282 G135 -870 411 325 G178 -3450 411 368 G221 -6030 411 283 G136 -930 411 326 G179 -3510 411 369 G222 -6090 411 284 G137 -990 411 327 G180 -3570 411 370 G223 -6150 411 285 G138 -1050 411 328 G181 -3630 411 371 G224 -6210 411 286 G139 -1110 411 329 G182 -3690 411 372 G225 -6270 411 287 G140 -1170 411 330 G183 -3750 411 373 G226 -6330 411 288 G141 -1230 411 331 G184 -3810 411 374 G227 -6390 411 289 G142 -1290 411 332 G185 -3870 411 375 G228 -6450 411 290 G143 -1350 411 333 G186 -3930 411 376 G229 -6510 411 291 G144 -1410 411 334 G187 -3990 411 377 G230 -6570 411 292 G145 -1470 411 335 G188 -4050 411 378 G231 -6630 411 293 G146 -1530 411 336 G189 -4110 411 379 G232 -6690 411 294 G147 -1590 411 337 G190 -4170 411 380 G233 -6750 411 295 G148 -1650 411 338 G191 -4230 411 381 G234 -6810 411 296 G149 -1710 411 339 G192 -4290 411 382 G235 -6870 411 297 G150 -1770 411 340 G193 -4350 411 383 G236 -6930 411 298 G151 -1830 411 341 G194 -4410 411 384 G237 -6990 411 299 G152 -1890 411 342 G195 -4470 411 385 G238 -7050 411 300 G153 -1950 411 343 G196 -4530 411 386 G239 -7110 411 301 G154 -2010 411 344 G197 -4590 411 387 G240 -7170 411 6 X POINT Y POINT 2002-03-06 JBT6K48-AS PAD Coordinates (4) [Unit: mm] No. Name X POINT Y POINT 388 VGGL -7283 411 389 VGGL -7343 411 390 VGGL -7403 411 391 VGGL -7463 411 392 DU -7587 295 393 DU -7587 195 394 DU -7587 95 395 DU -7587 -5 396 DU -7587 -105 397 DU -7587 -205 398 DU -7587 -305 ¾ Alignment mark_L -7548 -433 ¾ Alignment mark_R 7548 -433 7 2002-03-06 JBT6K48-AS Pin Description Pin Name I/O Function Data transfer direction switching pin Specifies the shift direction of the shift registers. U/D I · U/D = H: G1 ® G2 ® G3 ® G4 ® G5 ® … ® G240 · U/D = L: G240 ® G239 ® G238 ® G237 ® … ® G1 Use the pin at DC level. For High, VDD; for Low, VSS. CPV I Vertical shift clock Shift clock for the shift registers. Data are shifted in sync with the rising edge of CPV. DI I Vertical shift data input pin The data is input in the first stage of the shift register and latched in the shift register at the first rising edge of the CPV. Output switching This pin switches numbers of LCD panel drive pins. OCM I OCM = H: 220 Output mode (G221 to G240 pin output indefinite voltage.) OCM = L: 240 Output mode Output mode switching pin (1) Mode /OE1 Output Mode I H Normal mode L All output off mode (ASYNC) Output mode switching pin (2) Mode /OE2 Output Mode I H Normal mode L All output off mode (sync with CPV) G1 to G240 O LCD panel drive pins. VDDL/VDDR ¾ Power supply pin for internal logic VSSL/VSSR ¾ Power supply pin for internal logic VGGL/VGGR ¾ LCD panel drive pins VEEL/VEER ¾ LCD panel drive pins TEST17 I Test pin (1) The pull down resistor is connected to this pin, and must be left open. TEG1 to 16 I Test pin (2) This is a test pin, and must be left open. Dummy pin These pins are dummies, and each pin has an electric function such as, VDD, VSS or floating. The details are listed below. Pin Name DUG DUV DU ¾ Remarks DUG DUG … A dummy pin for VSS. DUV DUV … A dummy pin for VDD. DU Note 2: DU … A dummy pin for floating. The DUG pin and the DUV pin are used to fix the level by the adjacent input pin. Do not use them as the reference power supply. 8 2002-03-06 JBT6K48-AS Device Function and Operation · Setting the Data Transferring Direction Setting U/D pin enables JBT6K48-AS shift the shift register in sync with the falling edge of the vertical shift clock input from the CPV pin. When the U/D pin data is fixed before the DI data is input, the function becomes valid. · Inputting Data The data is latched at the first falling edge of the CPV. The signal is output from the first falling edge of the CPV recognized the data. · Switching Numbers of the Output Pin The valid output pin can be switched either 220 pins or 240 pins using the COM pin. The details about the valid output pins are listed below. OCM Valid output pin 0 G1 to G240 1 G1 to G220 Remarks G221 to G240 output indefinite voltage level OCM U/D Shifting Direction 0 0 G240 ® G239 ® G238 ® …… ® G3 ® G2 ® G1 0 1 G1 ® G2 ® G3 ® …… ® G238 ® G239 ® G240 1 0 G220 ® G219 ® G218 ® …… ® G3 ® G2 ® G1 1 1 G1 ® G2 ® G3 ® …… ® G218 ® G219 ® G220 9 2002-03-06 JBT6K48-AS · Output mode switching function JBT6K48-AS is capable to control the output signal using /OE1 and /OE2 pins. The /OE2 signal proceeds the /OE1 signal at output-off mode. /OE2 1 /OE1 Functions 1 Normal mode (Fig. 1) 0 Output signals turn off unsynchronizing with CPV (Fig. 3) 1 Output signals turn off synchronizing with CPV (Fig. 2) 0 /OE2 has priority no relation to /OE1 and output signals turn off 0 a) Normal operation mode DI 1 2 3 4 5 236 237 238 239 240 CPV G1 (G240) G2 (G239) G3 (G238) G4 (G237) G237 (G4) G238 (G3) G239 (G2) G240 (G1) ( ) indicates when U/D is Low. Figure 1 10 2002-03-06 JBT6K48-AS b) Normal mode + Sync off mode (/OE2) DI 1 2 3 4 5 CPV /OE2 G1 (G240) G2 (G239) G3 (G238) G4 (G237) G5 (G236) G6 (G235) G7 (G234) G8 (G233) G9 (G232) G10 (G231) G11 (G230) G239 (G2) G240 (G1) Figure 2 11 2002-03-06 JBT6K48-AS c) Normal mode+ ASYNC off mode (/OE1) DI 1 2 3 4 5 CPV /OE1 G1 (G240) G2 (G239) G3 (G238) G4 (G237) G5 (G236) G6 (G235) G7 (G234) G8 (G233) G239 (G2) G240 (G1) Figure 3 12 2002-03-06 JBT6K48-AS d) Synchronizing off mode + un-synchronizing off mode DI 1 2 3 4 5 CPV /OE1 /OE2 G1 (G240) G2 (G239) G3 (G238) G4 (G237) G5 (G236) G6 (G235) G7 (G234) G8 (G233) G9 (G232) Figure 4 13 2002-03-06 JBT6K48-AS · Recommended Power-on and Power-off Sequence If the logic power supply is applied under the floating condition, the device might be destructed by the large amounts of current because the LCD panel drive voltage is high. For this reason, apply the logic power supply first, then turn the LCD panel drive power supply on, or turn the both power supply on at the same timing. The internal logic condition is instable immediately after the logic power-on. Therefore, initialize the internal logic by transferring the clock for the continuous connecting and setting period using the CPV and DI input. Turn the LCD panel drive power off first, then turn the logic power off, or turn the both power off at the same timing. VGG VDD t VEE VEE/VOFF Figure 1 · Relations between power supplies LCD drive output VGG VDD Logic input Internal logic Level shifter VSS VEE Maximum Ratings (Unless Otherwise Noted, VSS = 0 V, Ta = 25°C) Characteristics Symbol Rating Unit Supply voltage (1) VDD -0.3 to 6.5 V Supply voltage (2) VEE -20.0 to 0.3 V Supply voltage (3) VGG - VEE -0.3 to 45.0 V Input voltage VIN -0.3 to VDD + 0.3 V Operating temperature Topr -20 to 75 °C Storage temperature Tstg -55 to 125 °C 14 2002-03-06 JBT6K48-AS Electrical Characteristics DC Characteristics (1) Unless Otherwise Noted, VGG - VEE = 16.0 to 33.0 V, VDD = 2.5 to 3.6 V, Ta = -20 to 75°C Symbol Test Circuit Test Condition Min Typ. Max Unit Relevant Pin Supply voltage 1) VDD ¾ ¾ 2.5 ¾ 3.6 V VDDL/R Supply voltage (2) VEE ¾ ¾ -16.5 -11.0 -5 V VEEL/R Supply voltage (3) VGG ¾ ¾ 8 12.5 16.5 V VGGL/R Supply voltage (4) ïVGG - VEEï ¾ ¾ 16.0 ¾ 33.0 V VGGL/R, VEEL/R VSS ¾ 0.2 VDD V DI, CPV, U/D, /OE1, /OE2, OCM kW G1 to G240 Characteristics Low level VIL ¾ Input voltage Output resistance High level VIH Low level ROL High level ROH ¾ ¾ 0.8 VDD ¾ VDD VOUT = VOFF + 0.5 V ¾ ¾ 7.5 VOUT = VGG - 0.5 V ¾ ¾ 7.5 Input leakage current IIN ¾ ¾ -1 ¾ 1 mA DI, CPV, U/D, /OE1, /OE2, OCM Operating frequency fCPV1 ¾ ¾ ¾ 20 50 kHz CPV CL1 ¾ ¾ 36 100 pF G1~G240 Output load capacitance (Note 3) Note 3: Load capacitance per an output pin. DC Characteristics (2) Unless Otherwise Noted, VGG - VEE = 16.0 to 33.0 V, VDD = 2.5 to 3.6 V, Ta = -20 to 75°C Typical value is VDD = 3.0 V, VGG - VEE = 30.0 V, CPV = 20 kHz, Ta = 25°C Symbol Test Circuit Current dissipation (1) IGG ¾ Current dissipation (2) IEE Current dissipation (3) Current dissipation (4) Characteristics Current dissipation (5) Min Typ. Max (Note 4, 5) ¾ 3.2 30.0 VGGL/R ¾ (Note 4, 5) ¾ 3.3 -30.0 VEEL/R IDD ¾ (Note 4) ¾ 1.8 12.5 VDDL/R ISS ¾ (Note 4) ¾ 1.7 -13.0 STB Test Condition ¾ (Note 6) -1 ¾ 1 Unit mA Relevant Pin VSSL/R VGGL/R, VEEL/R, VDDL/R, VSSL/R Note 4: CPV = 50 kHz Note 5: fFram = 70 Hz Note 6: CPV = “L” 15 2002-03-06 JBT6K48-AS AC Characteristics Unless Otherwise Noted, VGG - VEE = 30.0 V, VDD = 2.5 to 3.6 V, Ta = -20 to 75°C Symbol Test Circuit Test Condition tcycCPV ¾ ¾ CPV pulse width Low level tCPVL ¾ ¾ 500 ns CPV pulse width High level tCPVH ¾ ¾ 5 ms ¾ ¾ twOE ¾ ¾ 1 tsDI ¾ ¾ 100 tsOE ¾ ¾ 100 thDI ¾ ¾ 300 thOE ¾ ¾ 300 Output delay time (1) tpdG ¾ CL = 100 pF 2 ms Output delay time (2) tpdOE ¾ CL = 100 pF 2 ms ¾ CL = 100 pF 1.5 ms Characteristics CPV cycle time CPV rising/falling time trCPV /tfCPV /OE enable time Data setup time Data hold time Output rising/falling time trOG /tfOG 16 Min Typ. Max Unit 10 ms 100 ns ms ns ns 2002-03-06 JBT6K48-AS tcycCPV tCPVH CPV VIH tCPVL trCPV VIH VIH VIL tfCPV VIH VIL VIL tsDI VIH DI VIL CPV VIL tsOE /OE1 thOE VIL VIL CPV G1 to G240 thDI VIL tpdG VIL tpdG 90% 50% 10% 90% 50% 10% tfOG trOG twOE /OE1 50% 50% tpdOE G1 to G240 tpdOE 50% 50% 17 2002-03-06 JBT6K48-AS RESTRICTIONS ON PRODUCT USE 000707EBM · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 18 2002-03-06