TPD7203F
TOSHIBA Intelligent Power Device
Silicon Monolithic Power MOS Integrated Circuit
TPD7203F
Power MOSFET Gate Driver for 3-Phase DC Motor
The TPD7203F is a power MOSFET gate driver for 3-phase full-bridge
circuits that use a charge pump system. The inclusion of a charge
pump circuit for high-side drive inside the IC makes it easy to
configure a 3-phase full-bridge circuit.
Features
z Power MOSFET gate driver for 3-phase DC motor
z Built-in power MOSFET protection and diagnosis function:
low-voltage protection
z Built-in charge pump circuit
z Package: SSOP-24 (300 mil) with embossed-tape packing
Pin Assignment
Weight: 0.29 g (typ.)
Marking
Lot No.
TPD7203F
A dot indicates
lead (Pb)-free package or
lead (Pb)-free finish.
Part No. (or abbreviation code)
Due to its MOS structure, this product is sensitive to static electricity.
1
Handle with care.
2006-10-31
TPD7203F
Block Diagram / Application Circuit
*1:
Optimum conditions depend on the switching loss, EMI, etc., of the external MOSFET.
*2:
This is a laminated ceramic capacitor.
*3:
High-speed diode trr = 100 ns max (Recommended: CRH01)
Note:
For details on selecting external parts, see "Method for selecting external parts" described later.
2
2006-10-31
TPD7203F
Pin Description
Pin No.
Symbol
Pin Description
1
COSC
This pin sets the oscillation frequency for the charge pump drive.
Connect a 1500 pF (recommended) capacitor.
2
ROSC
This pin sets the oscillation frequency for the charge pump drive.
Connect a 100 kΩ (recommended) resistor.
3
IN5
Input pin: it controls the power MOSFET connected to VB. Built-in pull-down resistor
(100 kΩ typ.)
4
IN6
Input pin: it controls the power MOSFET connected to WB. Built-in pull-down resistor
(100 kΩ typ.)
5
IN1
Input pin: it controls the power MOSFET connected to UU. Built-in pull-down resistor
(100 kΩ typ.)
6
IN2
Input pin: it controls the power MOSFET connected to VU. Built-in pull-down resistor
(100 kΩ typ.)
7
IN3
Input pin: it controls the power MOSFET connected to WU. Built-in pull-down resistor
(100 kΩ typ.)
8
IN4
Input pin: it controls the power MOSFET connected to UB. Built-in pull-down resistor
(100 kΩ typ.)
9
FAULT
Diagnosis output pin: when low-voltage 6 V (typ.) is detected, output “H”. Circuit configuration is
N-ch open drain.
10
SGND
Signal block GND pin
11
CP1
Capacitor pin for charge pump
Connect a 0.47 μF (recommended) laminated ceramic capacitor.
12
CP2
Capacitor pin for charge pump
Connect a 0.47 μF (recommended) laminated ceramic capacitor.
13
VDD
Power supply pin: when low voltage (6 V typ.) is detected, all outputs are shut down.
14
WB
Drives the power MOSFET connected to the low side of the W phase.
15
PGND
Power block GND pin
16
VB
Drives the power MOSFET connected to the low side of the V phase.
17
UB
Drives the power MOSFET connected to the low side of the U phase.
18
WU
Drives the power MOSFET connected to the high side of the W phase.
19
W
W phase output pin
20
VU
Drives the power MOSFET connected to the high side of the V phase.
21
V
22
UU
23
U
24
CPV
V phase output pin
Drives the power MOSFET connected to the high side of the U phase.
U phase output pin
Final stage capacitor for the charge pump
Connect 1 μF (recommended) laminated ceramic capacitor and 10 μF (recommended) aluminum
electrolytic capacitor in parallel.
3
2006-10-31
TPD7203F
Truth Table
(All outputs go to low for input in high-side/low-side arm shorting mode)
Mode
No.
*:
Input
Output
In1 In2
In3
In4 In5
In6 Out
(UU) (VU) (WU) (UB) (VB) (WB) UU
Out
VU
Out
WU
Out
UB
Out
VB
Out
WB
Remarks
01
L
L
L
L
L
L
L
L
L
L
L
L
02
H
L
L
L
L
L
H
L
L
L
L
L
03
L
H
L
L
L
L
L
H
L
L
L
L
04
L
L
H
L
L
L
L
L
H
L
L
L
05
L
L
L
H
L
L
L
L
L
H
L
L
06
L
L
L
L
H
L
L
L
L
L
H
L
07
L
L
L
L
L
H
L
L
L
L
L
H
08
H
L
L
H
L
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
09
H
L
L
L
H
L
H
L
L
L
H
L
120° square wave conducting normal mode
10
H
L
L
L
L
H
H
L
L
L
L
H
120° square wave conducting normal mode
11
L
H
L
H
L
L
L
H
L
H
L
L
120° square wave conducting normal mode
12
L
H
L
L
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
13
L
H
L
L
L
H
L
H
L
L
L
H
120° square wave conducting normal mode
14
L
L
H
H
L
L
L
L
H
H
L
L
120° square wave conducting normal mode
15
L
L
H
L
H
L
L
L
H
L
H
L
120° square wave conducting normal mode
16
L
L
H
L
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
17
H
H
L
L
L
L
H
H
L
L
L
L
18
L
H
H
L
L
L
L
H
H
L
L
L
19
H
L
H
L
L
L
H
L
H
L
L
L
20
L
L
L
H
H
L
L
L
L
H
H
L
21
L
L
L
L
H
H
L
L
L
L
H
H
22
L
L
L
H
L
H
L
L
L
H
L
H
23
H
H
L
H
L
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
24
H
H
L
L
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
25
H
H
L
L
L
H
H
H
L
L
L
H
26
L
H
H
H
L
L
L
H
H
H
L
L
27
L
H
H
L
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
28
L
H
H
L
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
29
H
L
H
H
L
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
30
H
L
H
L
H
L
H
L
H
L
H
L
High-side/low-side arm shorting mode is disabled by the internal logic. (FAULT is kept low.) When
undervoltage (6 V typ.) is detected, all outputs are pulled low regardless of input signals. At this time, FAULT
output goes high (open-drain, high-impedance).
4
2006-10-31
TPD7203F
Mode
No.
*:
Input
Output
In1 In2
In3
In4 In5
In6 Out
(UU) (VU) (WU) (UB) (VB) (WB) UU
Out
VU
Out
WU
Out
UB
Out
VB
Out
WB
Remarks
31
H
L
H
L
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
32
H
L
L
H
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
33
H
L
L
L
H
H
H
L
L
L
H
H
34
H
L
L
H
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
35
L
H
L
H
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
36
L
H
L
L
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
37
L
H
L
H
L
H
L
H
L
H
L
H
38
L
L
H
H
H
L
L
L
H
H
H
L
39
L
L
H
L
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
40
L
L
H
H
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
41
H
H
H
L
L
L
H
H
H
L
L
L
42
L
L
L
H
H
H
L
L
L
H
H
H
43
H
H
L
H
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
44
H
H
L
L
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
45
H
H
L
H
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
46
L
H
H
H
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
47
L
H
H
L
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
48
L
H
H
H
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
49
H
L
H
H
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
50
H
L
H
L
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
51
H
L
H
H
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
53
H
H
H
L
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
54
H
H
H
L
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
55
H
L
L
H
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
56
L
H
L
H
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
57
L
L
H
H
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
58
H
H
H
H
H
L
L
L
L
L
L
L
High-side/low-side arm shorting mode *
59
H
H
H
L
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
60
H
H
H
H
L
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
61
H
H
L
H
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
62
L
H
H
H
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
63
H
L
H
H
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
64
H
H
H
H
H
H
L
L
L
L
L
L
High-side/low-side arm shorting mode *
High-side/low-side arm shorting mode is disabled by the internal logic. (FAULT is kept low.) When
undervoltage (6 V typ.) is detected, all outputs are pulled low regardless of input signals. At this time, FAULT
output goes high (open-drain, high-impedance).
5
2006-10-31
TPD7203F
Absolute Maximum Ratings (Ta = 25°C)
Characteristic
Power supply voltage
Output current
Input voltage
Fault pin voltage
U, V and pin negative voltage
PGND pin negative voltage
Fault pin current
Symbol
Rating
Unit
VDD
− 0.5 ~ 30
V
ISOURCE
1
ISINK
1
A
Remarks
Pulse width ≤10μs
VIN
− 0.5 ~ 7.0
V
VFAULT
30
V
U (−)
V (−)
W (−)
− 0.5
V
Negative voltage that can be applied to U,
V and W pins (Reference to SGND pin)
PGND(−)
− 0.5
V
Negative voltage that can be applied to
PGND pin
(reference to SGND pin)
IFAULT
5
mA
0.8
Power dissipation
PD
Operating temperature
Topr
− 40 ~ 125
°C
Storage temperature
Tstg
− 40 ~ 150
°C
1.2
Note
W
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Thermal Resistance
Characteristic
Junction to ambient thermal resistance
Note:
Symbol
Rth (j-a)
Rating
156.3
104.2
Note
Unit
°C / W
When the device is mounted on a 60 mm × 60 mm × 1.6 mm glass epoxy PCB
6
2006-10-31
TPD7203F
Electrical Characteristics
(Unless otherwise specified, Ta = −40 ~ 125°C)
Characteristic
Operating supply
voltage
Supply current
Symbol
Test
Circuit
Condition
Min
Typ.
Max
Unit
VDD
⎯
⎯
7
13.5
18
V
IDD(1)
1
VDD = 13.5 V
⎯
⎯
10
IDD(2)
2
VDD = 13.5 V,
VIN1 ~ VIN6
=0V
⎯
⎯
100
3.5
⎯
⎯
2
VDD = 7 ~ 18 V,
IO = 0 A
⎯
⎯
1.5
VDD = 7 ~ 18 V,
VIN = 5 V,
IO = 0 A
⎯
⎯
1
VDD = 7 ~ 18 V,
VIN = 0 V,
IO = 0 A
− 10
⎯
10
VDD = 13.5 V,
VIN = 5 V,
IO = 0 A
VCPV
−2
⎯
VCPV
VCPV denotes CPV pin
voltage. (reference to SGND
pin)
0.1
UU pin voltage (reference to U
pin)
VU pin voltage (reference to V
pin)
WU pin voltage (reference to
W pin)
VIH
Input voltage
VIL
IIH
Input current
2
IIL
VOH
Oscillation circuit stops
mA
V
Output
voltage
⎯
VOH
VDD = 13.5 V,
VIN = 5 V,
IO = 0 A
11.5
⎯
13.5
VOL
VDD = 13.5 V,
VIN = 0 V,
IO = 0 A
⎯
⎯
0.1
Low side
IN1- IN6 high-level input
voltage
IIN1-IN6 low-level input
voltage
IN1-IN6 input current
VDD = 13.5 V,
VIN = 0 V,
IO = 0 A
2
When oscillation circuit is
operating f = 20 kHz, mean
current
mA
μA
High side
VOL
Remarks
⎯
V
UB pin voltage (reference to
PGND pin)
VB pin voltage (reference to
PGND pin)
WB pin voltage (reference to
PGND pin)
Charge pump voltage
VCPV
2
VDD = 13.5 V
30
⎯
35
V
CPV pin voltage (reference to
SGND pin)
Active clamp voltage
(low side)
VCLAMP
⎯
VIN = 5 V,
IO = 10 mA
⎯
18
⎯
V
UB, VB and WB pins clamp
voltage
(reference to PGND pin)
VDD = 13.5 V,
VIN = 5 V,
IO = 0.5 A
⎯
7
10
VDD = 13.5 V,
VIN = 0 V,
IO = 0.5 A
Ω
⎯
UU, VU, WU, UB, VB and WB
output resistance
pulse width≤10 μs
RSOURCE
Output ON resistance
2
RSINK
7
4.5
10
2006-10-31
TPD7203F
Characteristic
Lowvoltage
protection
Switching
time
Detection
Hysteresis
Symbol
VSD (L)
∆VSD (L)
Turn-on
delay
time
td (ON)
Turn-on
time
tON
Turn-off
delay
time
td (OFF)
Turn-off
time
tOFF
Oscillating frequency
Fault pin voltage
Test
Circuit
Condition
3
⎯
4
VDD = 7 to 18 V,
COUT = 0.047μF,
RG = 47Ω
Min
Typ.
Max
5.5
6
6.5
⎯
0.5
⎯
⎯
⎯
4
⎯
⎯
6
⎯
⎯
4
⎯
⎯
6
Unit
Remarks
V
Low voltage detection
voltage and hysteresis
(VDD voltage detected)
μs
UU, VU, WU, UB, VB
and WB switching
time
fOSC calculation formula
fOSC ≈ 3 / {COSC (ROSC
+ 2 k)} (Hz)
fosc
2
VDD = 7 ~ 18 V,
ROSC = 100 kΩ,
COSC = 1500 pF
⎯
20
⎯
kHz
VFAULT
2
IFAULT = 1 mA
⎯
⎯
0.8
V
FAULT pin low-level
voltage (open - drain)
⎯
1
⎯
3
RFAULT = 5.1 kΩ,
VFAULT = 5 V
(External power
supply)
μs
⎯
1
⎯
Time from low
voltage / overvoltage
detection or
restoration to FAULT
output inversion
tON
Fault delay time
tOFF
8
2006-10-31
TPD7203F
Test Circuit 1
Testing Circuit 2
IDD(1)
IDD(2), VIH, VIL, IIH, IIL, VOH, VOL, VCPV, VFAULT
9
2006-10-31
TPD7203F
Testing Circuit 3
VSD(L), ΔVSD, VSD(H), ΔVSD(H), FAULT delay time tON, tOFF
Low voltage
10
Low voltage
2006-10-31
TPD7203F
Testing Circuit 4
td(ON), tON, td(OFF), tOFF
11
2006-10-31
TPD7203F
IDD(1)
-
Ta
AMBIENT TEMPERATURE
IDD(1)
Ta
(℃)
-
Ta
AMBIENT TEMPERATURE
Ta
Ta=25℃
VIH
-
Ta=25℃
Ta
AMBIENT TEMPERATURE
VIL -
Ta
(℃)
(℃)
Ta
AMBIENT TEMPERATURE
12
Ta
(℃)
2006-10-31
TPD7203F
IIH
-
IIL -
Ta
AMBIENT TEMPERATURE
Ta
Ta
AMBIENT TEMPERATURE
(℃)
Ta
Ta=25℃, IO=0A
VDROP
(℃)
Ta=25℃
-
VOL
Ta
AMBIENT TEMPERATURE
Ta
-
Ta
AMBIENT TEMPERATURE
(℃)
13
Ta
(℃)
2006-10-31
TPD7203F
RSOURCE
-
Ta
AMBIENT TEMPERATURE
VSD(L)
-
RSINK
Ta
AMBIENT TEMPERATURE
(℃)
Ta
AMBIENT TEMPERATURE
VSD(L)
Ta
Ta
-
(℃)
-
Ta
Ta
AMBIENT TEMPERATURE
Ta=25℃
(℃)
Ta
(℃)
Ta=25℃
14
2006-10-31
TPD7203F
tOFF- Ta
tON - Ta
AMBIENT TEMPERATURE
fOSC
-
Ta
(℃)
AMBIENT TEMPERATURE
Ta
AMBIENT TEMPERATURE
VFAULT
Ta
(℃)
-
(℃)
Ta
(℃)
Ta
AMBIENT TEMPERATURE
15
Ta
2006-10-31
TPD7203F
Method for Selecting External Parts
Recommended Value /
Recommended Product
Pin
No.
Pin Name
1
COSC
Capacitor
1500 pF (ceramic)
Sets the charge pump oscillation frequency.
2
ROSC
Resistor
100 kΩ
Sets the charge pump oscillation frequency.
11
12
CP1
CP2
Capacitor
0.47 μF
(laminated ceramic )
Capacitor for the charge pump: The greater this capacitance, the larger the charging current to the capacitor and the greater the loss in the IC.
Capacitor
1 μF (laminated ceramic) and
10 μF (aluminum electrolytic )
connected in parallel
The greater this capacitance, the larger the current
supply capacity of the charge pump (CPV pin) but the
greater the loss in the IC. Take care not to exceed the
allowable loss.
trr = 100 ns (max)
CRH01 (trr = 35 ns max)
recommended
Diode for the charge pump. An electric charge equal
to the diode's Qrr component goes out of the capacitor's charged electricity. Therefore, use a
high-speed diode. Diode for the charge pump： An
electric charge equal to the Qrr component of the
diode goes out of the electrical charge of the
capacitor. Therefore use a high-speed diode.
24
CPV
Type
11
12
24
CP1
CP2
CPV
High-speed
iode
22
20
18
17
16
14
UU
VU
WU
UB
VB
WB
Resistor
Description
Gate resistor for external power MOSFET. Choose
the optimum value by considering the switching loss
and EMI of the power MOSFET.
⎯
16
2006-10-31
TPD7203F
Usage Precautions
Note 1:
Feeding the charge pump voltage to external devices
Current can be taken out of the final stage (CPV pin) of the charge pump and fed to external devices
without causing any problem. In this case, because the charge pump voltage drops, increase the
capacitance of the capacitor connected to the CPV pin. However, this will cause the charging current to the
capacitor and, hence, loss in the IC to increase. Therefore be careful not to exceed the allowable loss.
Note 2:
Heat sink design
Because this IC contains a charge pump function, loss in it affects external capacitor capacitance and
diode characteristics. It is recommended that the junction temperature, Tj, be judged from the on-voltage of
the FAULT pin (open-drain). When VDD is within the range of operating power supply voltages, the FAULT
pin outputs a low. For details about on-voltage characteristics, see Tj-VFAULT characteristic curves.
Note 3:
Dead time setting
For arm-shorting input logic, all outputs (UU, VU, WU, UB, VB and WB) are pulled low. When
operating in forward or reverse mode, take into account the IC output switching time and the switching time
(including temperature characteristic) of the external power MOSFET when setting the dead time. The dead
time required for only the IC, not including the external power MOSFET, is 4μs (within all operating power
supply voltages and all operating temperatures).
Note 4:
Shorting between outputs, short-circuit of outputs and VDD pin or short-circuit of outputs and GND pin may
cause the IC to break down. Therefore, pay careful attention to the design of output lines and VDD and
GND lines.
Note 5:
Precautions on dry packing
After unpacking dry or moisture-proof packing, make sure the device is mounted in place within 48
hours at a temperature and humidity of 30°C and 60% RH or less. Because the device is emboss-taped
and cannot be processed by baking, always be sure to use it within the said allowable time after unpacking.
Standard tape packing quantity: 2000 devices / reel (EL1).
17
2006-10-31
TPD7203F
Package Dimensions
Unit: mm
Weight: 0.29 g (typ.)
18
2006-10-31
TPD7203F
RESTRICTIONS ON PRODUCT USE
20070701-EN
• The information contained herein is subject to change without notice.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc.
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his
document shall be made at the customer’s own risk.
• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patents or other rights of
TOSHIBA or the third parties.
• Please contact your sales representative for product-by-product details in this document regarding RoHS
compatibility. Please use these products in this document in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses
occurring as a result of noncompliance with applicable laws and regulations.
19
2006-10-31