BSI BS616LV8016 Very low power/voltage cmos sram 512k x 16 bit Datasheet

BSI
Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Dual CE Pins)
BS616LV8016
„ FEATURES
• Wide Vcc operation voltage : 2.4~5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 75mA (@55ns) operating current
I -grade: 76mA (@55ns) operating current
C-grade: 60mA (@70ns) operating current
I -grade: 61mA (@70ns) operating current
8.0uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ DESCRIPTION
The BS616LV8016 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.5uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616LV8016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8016 is available in 48-pin BGA package.
„ PRODUCT FAMILY
OPERATING
TEMPERATURE
PRODUCT FAMILY
Vcc
RANGE
POWER DISSIPATION
STANDBY
Operating
SPEED
(ns)
55ns : 3.0~5.5V
70ns : 2.7~5.5V
(ICCSB1, Max)
Vcc=3V
PKG TYPE
(ICC, Max)
Vcc=5V
Vcc=3V
Vcc=5V
70ns
70ns
BS616LV8016FC
+0 O C to +70 O C
2.4V ~ 5.5V
55 / 70
5uA
55uA
24mA
60mA
BGA-48-0912
BS616LV8016FI
-40 O C to +85 O C
2.4V ~ 5.5V
55 / 70
10uA
110uA
25mA
61mA
BGA-48-0912
„ PIN CONFIGURATIONS
A
„ BLOCK DIAGRAM
1
2
3
4
5
6
LB
OE
A0
A1
A2
CE2
B
D8
UB
A3
A4
CE1
D0
C
D9
D10
A5
A6
D1
D2
D
E
VSS
VCC
D11
D12
A17
VSS
A7
A16
D3
D4
A4
A3
A2
A1
Address
A0
A17
A16
A15
A14
A13
A12
Input
Buffer
D14
D13
A14
A15
D5
D0
VCC
.
.
.
.
VSS
D6
G
D15
NC
.
A12
A13
WE
D7
H
A 18
A8
A9
A10
A11
NC
2048
Row
Memory Array
Decoder
2048 x 4096
4096
16
.
.
.
.
Data
Input
Buffer
16
Column I/O
Write Driver
Sense Amp
16
Data
Output
Buffer
D15
F
22
256
16
Column Decoder
CE2
CE1
16
WE
OE
UB
LB
Control
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18
Vcc
Vss
48-Ball CSP top View
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8016
1
Revision 2.1
Jan.
2004
BSI
BS616LV8016
„ PIN DESCRIPTIONS
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Vss
Ground
„ TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
CE1
H
CE2
WE
OE
LB
UB
D0~D7
D8~D15
X
X
X
X
X
High Z
High Z
ICCSB , I CCSB1
X
L
X
X
X
X
High Z
High Z
ICCSB , I CCSB1
L
H
H
H
X
X
High Z
High Z
ICC
L
L
Dout
Dout
ICC
H
L
High Z
Dout
ICC
L
H
Dout
High Z
ICC
L
L
Din
Din
ICC
L
Write
H
L
„ ABSOLUTE MAXIMUM
SYMBOL
H
H
L
L
X
H
L
X
Din
ICC
L
H
Din
X
ICC
„ OPERATING RANGE
RATINGS(1)
PARAMETER
with
RATING
-0.5 to
Vcc+0.5
Vcc CURRENT
UNITS
VTERM
Terminal Voltage
Respect to GND
TBIAS
Temperature Under Bias
-40 to +85
O
TSTG
Storage Temperature
-60 to +150
O
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
V
C
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0 O C to +70O C
2.4V ~ 5.5V
Industrial
C
O
O
-40 C to +85 C
2.4V ~ 5.5V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
Input
CIN
VIN=0V
10
pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
Capacitance
RATINGS may cause permanent damage to the device. This is a
Input/Output
CDQ
VI/O=0V
12
pF
stress rating only and functional operation of the device at these
Capacitance
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
1. This parameter is guaranteed and not 100% tested.
maximum rating conditions for extended periods may affect reliability.
R0201-BS616LV8016
2
Revision 2.1
Jan.
2004
BSI
BS616LV8016
„ DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER
NAME
PARAMETER
VIL
Guaranteed Input Low
Voltage(3)
VIH
Guaranteed Input High
Voltage(3)
IIL
Input Leakage Current
ILO
VOL
VOH
TEST CONDITIONS
ICC
ICCSB
(5)
ICCSB1
-0.5
-0.5
(1)
MAX.
--
UNITS
2.0
2.2
----
0.8
0.8
Vcc+0.3
Vcc+0.3
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
Output Leakage Current
Vcc = Max, CE1 = VIH , or CE2 = V iL , or
OE = VIH, VI/O = 0V to Vcc
--
--
1
uA
Output Low Voltage
Vcc = Max, IOL= 2mA
Vcc=3V
Vcc=5V
Vcc = Min, IOH= -1mA
Vcc=3V
Vcc=5V
--2.4
2.4
-----
0.4
0.4
---
70ns
Vcc=3V
--
--
25
70ns
Vcc=5V
--
--
61
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
Output High Voltage
(4)
MIN. TYP.
Operating Power Supply
Current
CE1 = VIL and CE2 = VIH
, IDQ = 0mA, F = Fmax(2)
Standby Current-TTL
CE1 = VIH or CE2 = VIL
, IDQ = 0mA
Vcc=3V
--
--
1
Vcc=5V
--
--
2
CE1≧ Vcc-0.2V or
CE2≦ 0.2V ;VIN≧ Vcc - 0.2V
or VIN≦ 0.2V
Vcc=3V
--
1.5
10
Standby Current-CMOS
Vcc=5V
--
8.0
110
V
V
V
V
mA
mA
uA
1. Typical characteristics are at TA = 25oC.
2. Fmax = 1/tRC .
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc_Max. is 31mA(@3.0V) / 76mA(@5.0V) under 55ns operation.
5.IccsB1 is 5uA/55uA at Vcc=3.0V/5.0V and TA=70oC.
„ DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
Vcc for Data Retention
CE1 ≧ Vcc - 0.2V or CE2≦0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE1 ≧ Vcc - 0.2V or CE2≦0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
--
0.8
2.5
uA
tCDR
Chip Deselect to Data
Retention Time
--
--
ns
--
--
ns
VDR
(3)
tR
See Retention Waveform
Operation Recovery Time
0
TRC
(2)
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR(Max.) is 1.3uA at TA=70OC.
„ LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
CE1
Vcc
tR
t CDR
CE1≥ Vcc - 0.2V
VIH
VIH
„ LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
VDR ≧ 1.5V
Vcc
CE2
R0201-BS616LV8016
VIL
Vcc
tR
t CDR
CE2 ≦ 0.2V
3
VIL
Revision 2.1
Jan.
2004
BSI
BS616LV8016
„ KEY TO SWITCHING WAVEFORMS
„ AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
WAVEFORM
INPUTS
OUTPUTS
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
CYCLE TIME : 70ns CYCLE TIME : 55ns
DESCRIPTION
Vcc = 2.7~5.5V
Vcc = 3.0~5.5V
MIN. TYP. MAX.
MIN. TYP. MAX.
UNIT
tAVAX
tAVQV
tELQV
tRC
tAA
t ACS1
Read Cycle Time
70
--
--
55
--
--
ns
Address Access Time
--
--
70
--
--
55
ns
Chip Select Access Time
(CE1)
--
--
70
--
--
55
ns
tELQV
tBA
t ACS2
tBA (1)
Chip Select Access Time
(CE2)
--
--
70
--
--
55
ns
(LB,UB)
--
--
35
--
--
30
ns
tGLQV
tELQX
tBE
tGLQX
tOE
tCLZ
tBE
tOLZ
Output Enable to Output Valid
--
--
35
--
--
30
ns
(CE2,CE1)
10
--
--
10
--
--
ns
5
--
--
5
--
--
ns
Output Enable to Output in Low Z
5
--
--
5
--
--
ns
tEHQZ
tBDO
tCHZ
tBDO
Chip Deselect to Output in High Z (CE2,CE1)
--
--
35
--
--
30
ns
Data Byte Control to Output High Z (LB,UB)
--
--
35
--
--
30
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
--
--
30
--
--
25
ns
tAXOX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
Data Byte Control Access Time
Chip Select to Output Low Z
Data Byte Control to Output Low Z
(LB,UB)
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV8016
4
Revision 2.1
Jan.
2004
BSI
BS616LV8016
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t RC
ADDRESS
t
t
AA
t
ACS2
t
ACS1
t OH
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
CE1
t
t CHZ(5)
(5)
CLZ
D OUT
READ CYCLE3 (1,4)
t RC
ADDRESS
t
AA
OE
t
CE2
t
t
CE1
t
t
t
OE
OH
ACS2
OLZ
t
ACS1
(5)
CLZ
OHZ
(5)
(1,5)
t
CHZ
t
BDO
LB,UB
t
BE
t
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
R0201-BS616LV8016
5
Revision 2.1
Jan.
2004
BSI
BS616LV8016
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to +
WRITE CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
t AVAX
t E1LWH
t AVWL
t AVWH
t WLWH
t WHAX
t BW
t WLQZ
t DVWH
t WHDX
t GHQZ
t WC
t CW
t AS
t AW
t WP
t WR
t BW (1)
t WHZ
t DW
t DH
t OHZ
t WHOX
t OW
85oC
)
CYCLE TIME : 70ns CYCLE TIME : 55ns
DESCRIPTION
Vcc = 3.0~5.5V
Vcc = 2.7~5.5V
MIN. TYP. MAX.
MIN. TYP. MAX.
UNIT
Write Cycle Time
70
--
--
55
--
--
ns
Chip Select to End of Write
55
--
--
ns
70
--
--
Address Setup Time
0
--
--
0
--
--
ns
Address Valid to End of Write
70
--
--
55
--
--
ns
Write Pulse Width
35
--
--
30
--
--
ns
0
--
--
0
--
--
ns
Date Byte Control to End of Write (LB,UB)
(CE2,CE1,WE)
30
--
--
25
--
--
ns
Write to Output in High Z
--
--
30
--
--
25
ns
Data to Write Time Overlap
30
--
--
25
--
--
ns
Data Hold from Write Time
0
--
--
0
--
--
ns
Output Disable to Output in High Z
--
--
30
--
--
25
ns
End of Write to Output Active
5
--
--
5
--
--
ns
Write recovery Time
NOTE :
1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
(3)
t WR
OE
CE2
(5)
(11)
t CW
(5)
CE1
t
BW
(5)
LB,UB
t AW
WE
(3)
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t DH
t DW
D IN
R0201-BS616LV8016
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Revision 2.1
Jan.
2004
BSI
BS616LV8016
WRITE CYCLE2 (1,6)
t WC
ADDRESS
CE2
(11)
t
(5)
CE1
t
BW
(5)
LB,UB
t
WE
CW
AW
t WR
t WP
(3)
(2)
t AS
(4,10)
t WHZ
D OUT
t
OW
t
DH
(7)
(8)
t DW
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV8016
7
Revision 2.1
Jan.
2004
BSI
BS616LV8016
„ ORDERING INFORMATION
BS616LV8016 X X
Z
YY
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
F :BGA-48-0912
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
1.4 Max.
0.25± 0.05
„ PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D 0.1
3.375
D1
N
D
E
D1
E1
e
48
12.0
9.0
5.25
3.75
0.75
E1
2.625
E ± 0.1
e
SOLDER BALL 0.35±0.05
VIEW A
48 mini-BGA (9mm x 12mm)
R0201-BS616LV8016
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Revision 2.1
Jan.
2004
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