Revised May 2005
74ALVC16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
Features
The ALVC16240 contains sixteen inverting buffers with 3STATE outputs to be employed as a memory and address
driver, clock driver, or bus oriented transmitter/receiver.
The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74ALVC16240 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
■ 1.65V to 3.6V VCC supply operation
The 74ALVC16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
■ 3.6V tolerant inputs and outputs
■ tPD
3.0 ns max for 3.0V to 3.6V VCC
3.5 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Uses patented noise/EMI reduction circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package Number
Package Descriptions
74ALVC16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
Pin Descriptions
DS500689
Pin Names
Description
OEn
Output Enable Input (Active LOW)
I0–I15
Inputs
O0–O15
Outputs
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74ALVC16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
October 2001
74ALVC16240
Connection Diagram
Truth Tables
Inputs
Outputs
OE1
I0–I3
O0–O3
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE2
I4–I7
O4–O7
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE3
I8–I11
O8–O11
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE4
I12–I15
O12–O15
L
L
H
L
H
L
H
X
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial (HIGH or LOW, inputs may not float)
Z High Impedance
Functional Description
trolled by an Output Enable (OEn) input. When OEn is
LOW, the outputs are in the 2-state mode. When OEn is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the inputs.
The 74ALVC16240 contains sixteen inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
each other. The control pins may be shorted together to
obtain full 16-bit operation.The 3-STATE outputs are con-
Logic Diagram
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2
Supply Voltage (VCC )
DC Input Voltage (VI)
Output Voltage (VO) (Note 3)
Recommended Operating
Conditions (Note 4)
0.5V to 4.6V
0.5V to 4.6V
0.5V to VCC 0.5V
Power Supply
Operating
DC Input Diode Current (IIK)
VI 0V
0V to VCC
50 mA
Output Voltage (VO)
0V to VCC
50 mA
Minimum Input Edge Rate ('t/'V)
DC Output Diode Current (IOK)
Free Air Operating Temperature (TA)
VO 0V
DC Output Source/Sink Current
VIN
r50 mA
(IOH/IOL)
Supply Pin (ICC or GND)
0.8V to 2.0V, VCC
40qC to 85qC
3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
DC VCC or GND Current per
Storage Temperature Range (TSTG)
1.65V to 3.6V
Input Voltage (VI)
r100 mA
65qC to 150qC
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC
Conditions
(V)
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Min
1.65 -1.95
0.65 x VCC
2.3 - 2.7
1.7
2.7 - 3.6
2.0
Max
V
1.65 -1.95
0.35 x VCC
2.3 - 2.7
0.7
2.7 - 3.6
0.8
IOH
100 PA
1.65 - 3.6
VCC - 0.2
IOH
4 mA
1.65
1.2
IOH
6 mA
2.3
2
IOH
12 mA
2.3
1.7
2.7
2.2
Units
V
V
3.0
2.4
IOH
24 mA
3.0
2
IOL
100 PA
1.65 - 3.6
0.2
IOL
4 mA
1.65
0.45
IOL
6 mA
2.3
0.4
IOL
12mA
2.3
0.7
IOL
24 mA
2.7
0.4
3
0.55
V
II
Input Leakage Current
0 d VI d 3.6V
3.6
r5.0
PA
IOZ
3-STATE Output Leakage
0 d VO d 3.6V
3.6
r10
PA
ICC
Quiescent Supply Current
VI
3.6
40
PA
'ICC
Increase in ICC per Input
VIH
3 -3.6
750
PA
V CC or GND, IO
VCC 0.6V
3
0
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74ALVC16240
Absolute Maximum Ratings(Note 2)
74ALVC16240
AC Electrical Characteristics
TA
Symbol
CL
Parameter
V CC
tPHL, tPLH
Propagation Delay
Bus to Bus
40qC to 85qC, RL
50 pF
3.3V r 0.3V
V CC
2.7V
V CC
500:
CL
30 pF
2.5V r 0.2V
V CC
1.8V r 0.15V
Units
Min
Max
Min
Max
Min
Max
Min
Max
1.3
3.0
1.5
3.5
1.0
3.0
1.5
6.0
ns
tPZL, tPZH
Output Enable Time
1.3
4.0
1.5
4.6
1.0
4.1
1.5
8.2
ns
tPLZ, tPHZ
Output Disable Time
1.3
4.0
1.5
4.3
1.0
3.8
1.5
7.6
ns
Capacitance
Symbol
Parameter
Conditions
TA
25qC
VCC
Typical
Units
CIN
Input Capacitance
VI
0V or VCC
3.3
6
pF
COUT
Output Capacitance
VI
0V or VCC
3.3
7
pF
CPD
Power Dissipation Capacitance
3.3
20
2.5
20
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Outputs Enabled f
10 MHz, CL
4
50 pF
pF
TABLE 1. Values for Figure 1
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VL
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f 1MHz; tr tf 2 ns; Z0
Symbol
50:)
VCC
3.3V r 0.3V
2.7V
2.5V r 0.2V
1.8V r 0.15V
Vmi
1.5V
1.5V
VCC/2
VCC/2
Vmo
1.5V
1.5V
VCC/2
VCC/2
VX
VOL 0.3V
VOL 0.3V
VOL 0.15V
VOL 0.15V
VY
VOH 0.3V
VOH 0.3V
VOH 0.15V
VOH 0.15V
VL
6V
6V
VCC*2
VCC*2
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and
Disable Times for Low Voltage Logic
5
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74ALVC16240
AC Loading and Waveforms
74ALVC16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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