SILABS C8051F587-IQ Programmable gain maximizes input signal span Datasheet

C8051F587
50 MIPS, 96 kB Flash, 12-Bit ADC, 32-Pin Automotive MCU
Analog Peripherals
High-Speed 8051 µC Core
-
12-Bit ADC, 5 V input signal; up to 25 external inputs
-
±1 LSB INL; guaranteed monotonic
Programmable throughput up to 200 ksps
-
Data-dependent windowed interrupt generator
Memory
-
Programmable gain maximizes input signal span
Built-in Temperature Sensor (±3 °C)
Three Comparators
Precision Internal Voltage Reference
VDD Monitor/Brown-out Detector
-
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watch-points
-
8448 bytes data RAM (256 + 8 kB)
Up to 25 digital I/O; all are 5 V push-pull
Hardware I2C, SPI™, and two UART serial ports available concurrently
Two independent programmable 16-bit counter array with six capture/
compare modules
Six general-purpose 16-bit counter/timers
Clock Sources
Inspect/modify memory, registers, and stack
-
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Internal programmable ±0.5% oscillator: Up to 50 MHz
External oscillator: Crystal, RC, C, or CMOS Clock
Ordering Part Numbers
Temperature Range: –40 to +125 °C
Operating Voltage: 1.8 to 5.25 V
-
96 kB Flash; in-system programmable; flexible security features
Digital Peripherals
On-Chip Debug
-
Pipelined instruction architecture; executes 70% of instructions in one or
two system clocks
Up to 50 MIPS throughput
-
C8051F587-IM, 32-Pin QFN (RoHS-compliant), 5 x 5 mm2
C8051F587-IQ, 32-Pin QFP (RoHS-compliant), 9 x 9 mm2
Multiple power saving sleep and shutdown modes
Development Kit: C8051F580DK
Power On
Reset
Reset
C2CK/RST
Debug /
Programming
Hardware
VREGIN
Port 0
Drivers
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Digital Peripherals
96 kB Flash Program
Memory
C2D
VIO
Port I/O Configuration
CIP-51 8051 Controller
Core (50 MHz)
UART0
UART1
256 Byte RAM
Timers 0,
1,2,3,4,5
8 kB XRAM
Priority
Crossbar
Decoder
2x6
channel
PCA/WDT
Voltage Regulator
(LDO)
SPI
VDD
I2C
GND
System Clock Setup
SFR
Bus
Crossbar Control
XTAL1 XTAL2
Internal Oscillator
(±0.5%)
External Oscillator
Analog Peripherals
Voltage
Reference
Clock Multiplier
VDD
VREF
Port 3
Driver
P3.0/C2D
VREF
VDD
A
M
U
X
12-bit
200ksps
ADC
CP0, CP0A
Comparator 0
CP2, CP2A
Comparator 2
Automotive
P0 – P3
Temp
Sensor
GND
+
-
CP1, CP1A
Comparator 1
VDDA
GNDA
VREF
+
-
+
-
Copyright © 2008 by Silicon Laboratories
11.21.2008
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