Catalyst CAT24FC02ZETE13REV-F The cat24fc02 is a 2-kb serial cmos eeprom internally organized as 256 words of 8 bits each Datasheet

CAT24FC02
2-kb I2C Serial EEPROM
FEATURES
■ 400 kHz (2.5 V) I2C bus compatible
■ 1,000,000 program/erase cycles
■ 2.5 to 5.5 volt operation
■ 100 year data retention
■ Low power CMOS technology
■ 8-pin DIP, SOIC, TSSOP and MSOP packages
- “Green” package option available
■ 16-byte page write buffer
■ Industrial and extended temperature ranges
■ 256 x 8 memory organization
■ Self-timed write cycle with auto-clear
■ Hardware write protect
DESCRIPTION
The CAT24FC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements.
The CAT24FC02 features a 16-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP, SOIC, TSSOP and MSOP
packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L, GL)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
EXTERNAL LOAD
SOIC Package (J, W, GW)
VCC
WP
SCL
SDA
1
2
3
4
A0
A1
A2
VSS
8
7
6
5
VCC
VSS
TSSOP Package (U, Y, GY)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
WP
CONTROL
LOGIC
XDEC
COLUMN
DECODERS
E2PROM
MSOP Package (R, Z, GZ)
DATA IN STORAGE
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
HIGH VOLTAGE/
TIMING CONTROL
SCL
PIN FUNCTIONS
Pin Name
A0
A1
A2
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
2.5 V to 5.5 V Power Supply
VSS
Ground
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I2C Bus Protocol.
1
Doc. No. 1045, Rev. G
CAT24FC02
Lead Soldering Temperature (10 seconds) ...... 300°C
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
Output Short Circuit Current(2) ....................... 100 mA
–55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
*COMMENT
Voltage on Any Pin with
Respect to Ground(1) ............ –2.0 V to VCC + 2.0 V
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
VCC with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
RELIABILITY CHARACTERISTICS (3)
Symbol
Parameter
Min
Typ
Max
Units
NEND
Endurance
1,000,000
Cycles/Byte
TDR
Data Retention
100
Years
VZAP
ESD Susceptibility
4000
Volts
ILTH(4)
Latch-up
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = 2.5 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC
Power Supply Current (Read)
ICC
Min
Typ
Max
Units
fSCL = 400 kHz
1
mA
Power Supply Current (Write)
fSCL = 400 kHz
3
mA
ISB(5)
Standby Current (VCC = 5.0 V)
VIN = GND or VCC
1
µA
ILI
Input Leakage Current
VIN = GND to VCC
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
1
µA
VIL
Input Low Voltage
–1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL
Output Low Voltage (VCC = 3.0 V)
0.4
V
IOL = 3 mA
CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol
Test
Conditions
CI/O(3)
Input/Output Capacitance (SDA)
Input Capacitance (other pins)
CIN
(3)
Min
Typ
Max
Units
VI/O = 0 V
8
pF
VIN = 0 V
6
pF
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to VCC + 1.0 V.
(5) Maximum standby current (ISB) = 10µA for the Extended Automotive temperature range.
Doc. No. 1072, Rev. G
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC02
A.C. CHARACTERISTICS
VCC = 2.5 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
2.5 V - 5.5 V
Min
Max
Units
0
400
kHz
FSCL
Clock Frequency
TI(1)
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
SCL Low to SDA Data Out and ACK Out
900
ns
tAA
tBUF
(1)
Time the Bus Must be Free Before a New Transmission
Can Start
1300
ns
tHD:STA
Start Condition Hold Time
600
ns
tLOW
Clock Low Period
1300
ns
tHIGH
Clock High Period
600
ns
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
600
ns
tHD:DAT
Data In Hold Time
0
ns
tSU:DAT
Data In Setup Time
100
ns
tR(1)
SDA and SCL Rise Time
300
ns
SDA and SCL Fall Time
300
ns
tF
(1)
tSU:STO
Stop Condition Setup Time
600
ns
tDH
Data Out Hold Time
100
ns
Power-Up Timing(1)(2)
Symbol
Parameter
tPUR
tPUW
Min
Typ
Max
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
1
ms
Max
Units
5
ms
Write Cycle Limits
Symbol
Parameter
tWR
Write Cycle Time
Min
Typ
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1072, Rev. G
CAT24FC02
FUNCTIONAL DESCRIPTION
data transfers into or out of the device. This is an input
pin.
The CAT24FC02 supports the I2C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC02 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated. A maximum of
8 devices may be connected to the bus as determined by
the device address inputs A0, A1, and A2.
SDA: Serial Data/Address
The CAT24FC02 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24FC02 when this pin is tied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24FC02 serial clock input pin is used to clock all
Figure 1. Bus Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1072, Rev. G
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC02
I2C BUS PROTOCOL
eight CAT24FC02 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
The following defines the features of the I2C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
address byte, the CAT24FC02 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC02 then performs a Read or a Write operation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC02 monitors the
SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The CAT24FC02 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
and define which device the Master is accessing. Up to
When the CAT24FC02 begins a READ mode, it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24FC02 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
Normal Read and Write
DEVICE ADDRESS
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1072, Rev. G
CAT24FC02
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24FC02 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24FC02. After receiving another
acknowledge from the Slave, the Master device transmits
the data byte to be written into the addressed memory
location. The CAT24FC02 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24FC02 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC02 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC02 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
Page Write
WRITE PROTECTION
The CAT24FC02 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24FC02 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
The CAT24FC02 is designed with a hardware protect
pin that enables the user to protect the entire memory.
Thehardware protection feature of the CAT24FC02 is
designed into the part to provide added flexibility to the
design engineers. The write protection feature of
CAT24FC02 allows the user to protect against inadvertent
programming of the memory array. If the WP pin is tied
to Vcc, the entire memory array is protected and becomes
read only. The entire memory becomes write protected
regardless of whether the write protect register has been
written or not. When WP pin is tied to Vcc, the user
cannot program the write protect register. If the WP pin
is left floating or tied to Vss, the device can be written
into.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
S
DATA n
DATA n+1
S
T
O
P
DATA n+P
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1072, Rev. G
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC02
Read Operations
address, the Master device resends the START condition
and the slave address, this time with the R/W bit set to
one. The CAT24FC02 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
The READ operation for the CAT24FC02 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Sequential Read
Immediate Address Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC02 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC02 will continue to output a byte for
each acknowledge sent by the Master. The operation
will terminate operation when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The CAT24FC02 address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to address
N, the READ immediately following would access data
from address N + 1. If N = 255, the counter will ‘wrap
around’ to address 0 and continue to clock out data. After
the CAT24FC02 receives its slave address information
(with the R/W bit set to one), it issues an acknowledge,
then transmits the 8-bit byte requested. The master
device does not send an acknowledge but will generate
a STOP condition.
The data being transmitted from the CAT24FC02 is
outputted sequentially with data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT24FC02
address bits so that the entire memory array can be read
during one operation. If more than the 256 bytes are read
out, the counter will “wrap around” and continue to clock
out data bytes.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24FC02 acknowledge the word
Figure 8. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
NO ACK
7
STOP
Doc No. 1072, Rev. G
CAT24FC02
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
S
T
O
P
SLAVE
ADDRESS
S
A
C
K
P
A
C
K
A
C
K
DATA n
N
O
A
C
K
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1072, Rev. G
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC02
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
24FC02
Product
Number
Suffix
J
I
Temperature Range
I = Industri
E = Extended (-40°C to +125°C)
Package
P: PDIP
J: SOIC, JEDEC
R: MSOP
U: TSSOP
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
Z: MSOP (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)
TE13
REV-E
Die Revision: E, F
Tape & Reel
Notes:
(1) The device used in the above example is a CAT24FC02JI-TE13 REV-E (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc No. 1072, Rev. G
REVISION HISTORY
Date
Revision Comments
03/01/04
A
Initial Issue
05/15/04
B
D.C. Operating Characteristics
Write Cycle Limits
Update Ordering Information
Update Revision History
Update Rev Number
06/07/04
C
Update Write Cycle Limits
7/27/2004
D
Updated notes on page 2
1/27/2005
E
Added Die Revision E in Ordering Information
03/23/2005
F
Updated
Updated
Updated
Updated
Updated
Updated
Updated
08/02/2005
G
Update Pin Configuration
Update Ordering Information
Features
Description
Pin Function
Reliability Characteristics
Operating Characteristics
A.C. Characteristics
Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Publication #:
Revison:
Issue date:
1072
G
08/02/05
Similar pages