Cypress CY7C197-15PC 256kx1 static ram Datasheet

97
CY7C197
256Kx1 Static RAM
Features
vided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C197 has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
• High speed
— 12 ns
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory location specified on
the address pins (A0 through A17).
• CMOS for optimum speed/power
• Low active power
— 880 mW
Reading the device is accomplished by taking chip enable
(CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the data output (DOUT) pin.
• Low standby power
— 220 mW
• TTL-compatible inputs and outputs
The output pin stays in a high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
• Automatic power-down when deselected
The CY7C197 utilizes a die coat to insure alpha immunity.
Functional Description
The CY7C197 is a high-performance CMOS static RAM organized as 256K words by 1 bit. Easy memory expansion is pro-
Logic Block Diagram
Pin Configurations
DI
DIP/SOJ
Top View
SENSE AMPS
ROW DECODER
A13
A14
A15
A16
A17
A0
A1
A2
A3
A4
1024 x 256
ARRAY
COLUMN
DECODER
DO
POWER
DOWN
DOUT
WE
GND
A2
A1
A0
VCC
A 17
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
DIN
CE
1
24
2
23
3
22
4
21
5
20
7C197
6
19
18
7
8
17
9
16
10
15
14
11
12
13
NC
A3
A4
A5
A6
A7
A8
DOUT
NC
3 2 1 28 27
4
26 NC
5
25 A16
6
24 A15
7
23 A14
8
7C197 22 A13
9
21 A12
10
20 A11
11
19 A10
12
18 NC
1314151617
WE
GND
CE
DIN
A9
A0
A1
A2
A3
A4
A5
A6
A7
A8
INPUT BUFFER
LCC
Top View
C197-2
C197-3
CE
A5 A6 A7 A8 A9 A10 A11 A12
WE
C197-1
Selection Guide
7C197-12
7C197-15
7C197-20
7C197-25
7C197-35
7C197-45
Maximum Access Time (ns)
12
15
20
25
35
45
Maximum Operating Current (mA)
150
140
135
95
95
Maximum Standby Current (mA)
30
30
30
30
30
Cypress Semiconductor Corporation
Document #: 38-05049 Rev. **
•
3901 North First Street
•
San Jose
•
30
CA 95134 • 408-943-2600
Revised August 24, 2001
CY7C197
DC Input Voltage[1].................................... −0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ....................................... −0.5V to VCC + 0.5V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
7C197-12
Parameter
Description
Test Conditions
Min.
Max.
7C197-15
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min.
VIH
Input HIGH Voltage
2.2
VCC
+ 0.3V
VIL
Input LOW Voltage[1]
−0.5
IIX
Input Load Current
GND < VI < VCC
−5
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
−5
+5
µA
IOS
Output Short
Circuit Current[2]
VCC = Max., VOUT = GND
−300
−300
mA
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
150
140
mA
ISB1
Automatic CE Power-Down
Current—TTL Inputs[3]
Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
30
30
mA
ISB2
Automatic CE Power-Down
Current—CMOS Inputs[3]
Max. VCC, CE > VCC − 0.3V,
VIN > VCC − 0.3V or VIN < 0.3V
10
10
mA
2.4
IOL =12.0 mA
2.4
0.4
V
0.4
V
2.2
VCC
+0.3V
V
0.8
−0.5
0.8
V
+5
−5
+5
µA
+5
−5
Notes:
1. V(min.) = −2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
Document #: 38-05049 Rev. **
Page 2 of 10
CY7C197
Electrical Characteristics Over the Operating Range (continued)
7C197-20
Parameter
Description
Test Conditions
Min.
7C197-25, 35, 45
Max.
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min.
VIH
Input HIGH Voltage
2.2
VCC
+ 0.3V
VIL
Input LOW Voltage[1]
−0.5
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
IOS
Output Short
Circuit Current[2]
VCC = Max., VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
2.4
IOL =12.0mA
Max.
Unit
2.4
V
0.4
0.4
V
2.2
VCC
+ 0.3V
V
0.8
−0.5
0.8
V
−5
+5
−5
+5
µA
−5
+5
−5
+5
µA
−300
−300
mA
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
135
95
mA
Automatic CE Power Down
Current—TTL Inputs[3]
Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
30
30
mA
Automatic CE Power-Down
Current—CMOS Inputs[3]
Max. VCC, CE > VCC − 0.3V,
VIN > VCC − 0.3V or VIN < 0.3V
15
15
mA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
8
pF
10
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms[5]
R1 329 Ω
R1 329 Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
5 pF
202Ω
(255Ω MIL) INCLUDING
JIG AND
SCOPE
3.0V
R2
255Ω
(255Ω MIL)
(b)
C197-4
10%
90%
90%
10%
GND
< tr
< tr
C197-5
Equivalent to:
THÉVENIN EQUIVALENT
125Ω
OUTPUT
1.90V
Commercial
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. tr = < 3 ns for the -12 and -15 speeds. tr = < 5 ns for the -20 and slower speeds.
Document #: 38-05049 Rev. **
Page 3 of 10
CY7C197
Switching Characteristics Over the Operating Range[6]
7C197-12
Parameter
Description
Min.
Max.
7C197-15
Min.
Max.
7C197-20
Min.
Max.
7C197-25
Min.
Max.
7C197-35
Min.
Max.
7C197-45
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to
Data Valid
tOHA
Output Hold from
Address Change
tACE
CE LOW to
Data Valid
tLZCE
CE LOW to
Low Z[7]
tHZCE
CE HIGH to
High Z[7, 8]
tPU
CE LOW to
Power-Up
tPD
CE HIGH to
Power-Down
12
15
12
3
20
15
3
12
3
3
3
0
20
15
5
0
25
20
0
9
35
25
0
11
45
35
0
15
45
0
ns
ns
15
0
25
ns
ns
3
0
20
ns
3
3
0
20
45
3
3
0
15
35
3
3
7
12
25
ns
ns
30
ns
WRITE CYCLE[9]
tWC
Write Cycle Time
12
15
20
25
35
45
ns
tSCE
CE LOW to
Write End
9
10
15
20
30
40
ns
tAW
Address Set-Up to
Write End
9
10
15
20
30
40
ns
tHA
Address Hold from
Write End
0
0
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
0
0
ns
tPWE
WE Pulse Width
8
9
15
20
25
30
ns
tSD
Data Set-Up to
Write End
8
9
10
15
17
20
ns
tHD
Data Hold from
Write End
0
0
0
0
0
0
ns
tLZWE
WE HIGH to
Low Z[7]
2
2
3
3
3
3
ns
tHZWE
WE LOW to
High Z[7,8]
7
7
0
10
0
11
0
15
0
15
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of
1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05049 Rev. **
Page 4 of 10
CY7C197
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
C197-6
Read Cycle No. 2 [10]
tRC
CE
tACE
tHZCE
tLZCE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
ICC
50%
50%
ISB
C197-7
Write Cycle No.1 (WE Controlled) [9]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA IN
DATA VALID
tHZWE
DATA OUT
tHD
DATA UNDEFINED
tLZWE
HIGH IMPEDANCE
C197-8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = VIL.
Document #: 38-05049 Rev. **
Page 5 of 10
CY7C197
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
[9, 12]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tHD
tSD
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
C197-9
Note:
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05049 Rev. **
Page 6 of 10
CY7C197
ICC
0.8
0.6
VIN =5.0V
TA =25°C
0.4
0.2
ISB
0.0
4.0
4.5
5.0
5.5
1.0
0.8
0.6
VCC =5.0V
VIN =5.0V
0.4
0.2
ISB
0.0
-55
6.0
25
125
AMBIENT TEMPERATURE(°C)
SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED t AA
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.1
TA =25°C
1.0
0.9
0.8
4.0
4.5
5.0
5.5
1.2
1.0
VCC =5.0V
0.8
0.6
−55
6.0
120
100
80
VCC =5.0V
TA =25°C
60
40
20
0
0.0
140
3.0
2.5
(ns)
25.0
DELTA tAA
20.0
2.0
1.5
1.0
15.0
VCC =4.5V
TA =25°C
10.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE(V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
VCC =5.0V
TA =25°C
40
20
0
0.0
125
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE(V)
NORMALIZED I CC vs. CYCLE TIME
1.25
1.00
VCC =5.0V
TA =25°C
VIN =0.5V
0.75
5.0
0.5
0.0
0.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE(°C)
SUPPLY VOLTAGE(V)
NORMALIZED I PO
25
NORMALIZED I CC
1.0
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.4
ICC
1.2
OUTPUT SINK CURRENT (mA)
SB
1.2
NORMALIZED I,CC
I
NORMALIZED I,CC
I SB
1.4
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-05049 Rev. **
5.0
0.0
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 7 of 10
CY7C197
CY7C197 Truth Table
CE
WE
Input/Output
Mode
H
X
High Z
Deselect/Power-Down
L
H
Data Out
Read
L
L
Data In
Write
Ordering Information
Speed
(ns)
12
15
20
25
35
45
Ordering Code
Package
Name
Package Type
CY7C197-12PC
P13
24-Lead (300-Mil) Molded DIP
CY7C197-12VC
V13
24-Lead Molded SOJ
CY7C197-15PC
P13
24-Lead (300-Mil) Molded DIP
CY7C197-15VC
V13
24-Lead Molded SOJ
CY7C197-20PC
P13
24-Lead (300-Mil) Molded DIP
CY7C197-20VC
V13
24-Lead Molded SOJ
CY7C197-25PC
P13
24-Lead (300-Mil) Molded DIP
CY7C197-25VC
V13
24-Lead Molded SOJ
CY7C197-35PC
P13
24-Lead (300-Mil) Molded DIP
CY7C197-35VC
V13
24-Lead Molded SOJ
CY7C197-45PC
P13
24-Lead (300-Mil) Molded DIP
CY7C197-45VC
V13
24-Lead Molded SOJ
Document #: 38-05049 Rev. **
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Page 8 of 10
CY7C197
Package Diagrams
24-Lead (300-Mil) Molded DIP P13/P13A
51-85013-A
24-Lead (300-Mil) Molded SOJ V13
51-85030-A
Document #: 38-05049 Rev. **
Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C197
Document Title: CY7C197 256K x 1 Static RAM
Document Number: 38-05049
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
107151
09/10/01
SZV
Change from Spec number: 38-00078 to 38-05049
Document #: 38-05049 Rev. **
Page 10 of 10
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