Cypress CY62136FV30LL-45ZSXI 2-mbit (128 k x 16) static ram automatic power down when deselected Datasheet

CY62136FV30 MoBL®
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62136V, CY62136CV30/CV33, and
CY62136EV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A (Industrial)
■
Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin thin small outline package (TSOP) II
packages
The CY62136FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90 percent when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or
during a write operation (CE LOW and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
128 K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
•
A16
A15
A14
A13
A11
Cypress Semiconductor Corporation
Document Number: 001-08402 Rev. *J
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 17, 2011
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CY62136FV30 MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Document Number: 001-08402 Rev. *J
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY62136FV30 MoBL®
Product Portfolio
Power Dissipation
Product
VCC Range (V)
Range
CY62136FV30LL
Min
Typ [1]
Max
Industrial/Auto-A
2.2
3.0
3.6
Auto-E
2.2
3.0
3.6
Speed
(ns)
Operating ICC (mA)
f = 1 MHz
Standby ISB2
(A)
f = fmax
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
45
1.6
2.5
13
18
1
5
55
2
3
15
25
1
20
Pin Configuration
Figure 1. 48-ball VFBGA Pinout [2, 3]
Figure 2. 44-pin TSOP II [2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS I/O11
NC
A7
VCC
D
VCC
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
Document Number: 001-08402 Rev. *J
Page 3 of 16
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CY62136FV30 MoBL®
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage to ground
potential ........................... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
DC voltage applied to outputs
in High Z State [4, 5] .......... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
DC input voltage
[4, 5]
Static discharge voltage ......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch up current ..................................................... > 200 mA
Operating Range
Device
Range
CY62136FV30LL Industrial/
Auto-A
Auto-E
Ambient
Temperature
VCC[6]
–40 °C to +85 °C 2.2 V to 3.6 V
–40 °C to +125 °C
....... –0.3 V to 3.9 V (VCC(max) + 0.3 V)
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
IIX
IOZ
ICC
ISB1[8]
ISB2 [8]
Description
Output high voltage
Test Conditions
2.2 < VCC < 2.7 IOH = –0.1 mA
2.7 < VCC < 3.6 IOH = –1.0 mA
Output low voltage
2.2 < VCC < 2.7 IOL = 0.1 mA
2.7 < VCC < 3.6 IOL = 2.1 mA
Input high voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
Input low voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
Input leakage current
GND < VI < VCC
Output leakage current GND < VO < VCC, Output disabled
VCC operating supply
f = fmax = 1/tRC VCC = VCCmax
f = 1 MHz
current
IOUT = 0 mA
CMOS levels
CE > VCC –0.2 V,
Automatic CE power
down current — CMOS VIN > VCC – 0.2 V, VIN < 0.2 V,
inputs
f = fmax (Address and data only),
f = 0 (OE, WE, BHE, and BLE),
VCC = 3.60 V
CE > VCC – 0.2 V,
Automatic CE power
down current — CMOS VIN > VCC – 0.2 V or VIN < 0.2 V,
inputs
f = 0, VCC = 3.60 V
-45 (Industrial/Auto-A)
-55 (Auto-E)
Unit
Min Typ [7] Max
Min Typ [7] Max
2.0
–
–
2.0
–
–
V
2.4
–
–
2.4
–
–
V
–
–
0.4
–
–
0.4
V
–
–
0.4
–
–
0.4
V
1.8
–
VCC + 0.3 1.8
–
VCC + 0.3 V
2.2
–
VCC + 0.3 2.2
–
VCC + 0.3 V
–0.3
–
0.6
–0.3
–
0.6
V
–0.3
–
0.8
–0.3
–
0.8
V
–1
–
+1
–4
–
+4
A
–1
–
+1
–4
–
+4
A
–
13
18
–
15
25
mA
–
1.6
2.5
–
2
3
–
1
5
–
1
20
A
–
1
5
–
1
20
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max)=VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
Document Number: 001-08402 Rev. *J
Page 4 of 16
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CY62136FV30 MoBL®
Capacitance
Parameter [9]
Description
Input capacitance
CIN
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch, two
layer printed circuit board
75
77
C/W
10
13
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
R2
30 pF
INCLUDING
JIG AND
SCOPE
Parameters
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
2.5 V (2.2 V to 2.7 V)
3.0 V (2.7 V to 3.6 V)
Unit
R1
16667
1103

R2
15385
1554

RTH
8000
645

VTH
1.20
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-08402 Rev. *J
Page 5 of 16
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CY62136FV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Min
Typ [10]
Max
Unit
1.5
–
–
V
Industrial/
Automotive-A
–
–
4
A
Automotive-E
–
–
12
0
–
–
ns
CY62136FV30LL-45
45
–
–
ns
CY62136FV30LL-55
55
–
–
Conditions
VCC for data retention
[11]
Data retention current
VCC = 1.5 V,
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
tCDR [12]
Chip deselect to data retention
time
tR [13]
Operation recovery time
Data Retention Waveform
Figure 4. Data Retention Waveform [14]
VCC
CE or
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min)
tR
BHE.BLE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR specification. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-08402 Rev. *J
Page 6 of 16
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CY62136FV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
-45 (Industrial/Automotive-A) -55 (Automotive-E)
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
55
–
ns
tAA
Address to data valid
–
45
–
55
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE LOW to data valid
–
45
–
55
ns
tDOE
OE LOW to data valid
–
22
–
25
ns
tLZOE
OE LOW to low Z [17]
5
–
5
–
ns
tHZOE
OE HIGH to high Z [17, 18]
–
18
–
20
ns
tLZCE
CE LOW to low Z [17]
10
–
10
–
ns
–
18
–
20
ns
[17, 18]
tHZCE
CE HIGH to high Z
tPU
CE LOW to power up
0
–
0
–
ns
tPD
CE HIGH to power down
–
45
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
22
–
25
ns
tLZBE
BLE/BHE LOW to low Z [17]
5
–
5
–
ns
BLE/BHE HIGH to high Z [17, 18]
–
18
–
20
ns
tWC
Write cycle time
45
–
55
–
ns
tSCE
CE LOW to write end
35
–
40
–
ns
tAW
Address setup to write end
35
–
40
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tBW
BLE/BHE LOW to write end
35
–
40
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data Hold From Write End
0
–
0
–
ns
tHZWE
WE LOW to high Z [17, 18]
–
18
–
20
ns
tLZWE
WE HIGH to low Z [17]
10
–
10
–
ns
tHZBE
Write Cycle
[19]
Notes
15. Test conditions for all parameters other than tristate parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5.
16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
Document Number: 001-08402 Rev. *J
Page 7 of 16
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CY62136FV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle No.1: Address Transition Controlled [20, 21]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2: OE Controlled [21, 22]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
20. The device is continuously selected. OE, CE = VIL, BHE and BLE = VIL.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-08402 Rev. *J
Page 8 of 16
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CY62136FV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No 1: WE Controlled [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 26
tHD
DATAIN
tHZOE
Figure 8. Write Cycle 2: CE Controlled [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 26
tHZOE
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
24. Data I/O is high impedance if OE = VIH.
25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-08402 Rev. *J
Page 9 of 16
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CY62136FV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle 3: WE controlled, OE LOW [27]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 28
tHD
DATAIN
tLZWE
tHZWE
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [27]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 28
tSD
tHD
DATAIN
tLZWE
Notes
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-08402 Rev. *J
Page 10 of 16
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CY62136FV30 MoBL®
Truth Table
CE
WE
OE
BHE
BLE
[29]
[29]
X
X
Inputs or Outputs
Mode
Power
High Z
Deselect or power-down
Standby (ISB)
Output disabled
Active (ICC)
H
X
X
L
X
X
H
H
High Z
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
L
H
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
29. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate
voltage levels on these pins is not permitted.
Document Number: 001-08402 Rev. *J
Page 11 of 16
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CY62136FV30 MoBL®
Ordering Information
Speed
(ns)
45
55
Ordering Code
CY62136FV30LL-45BVXI
Package
Diagram
Package Type
51-85150 48-ball VFBGA (Pb-free)
Operating
Range
Industrial
CY62136FV30LL-45ZSXI
51-85087 44-pin TSOP II (Pb-free)
CY62136FV30LL-45ZSXA
51-85087 44-pin TSOP II (Pb-free)
Automotive-A
CY62136FV30LL-55ZSXE
51-85087 44-pin TSOP II (Pb-free)
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 3
6
F V30 LL - XX XX X
X
Temperature Grade: X = I or A or E
I = Industrial; A = Automotive-A or E = Automotive-E
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: XX = 45 ns or 55 ns
Low Power
Voltage Range: 3 V typical
Process Technology: 90 nm
Bus width = × 16
Density = 2-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-08402 Rev. *J
Page 12 of 16
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CY62136FV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48, 51-85150
51-85150 *F
Document Number: 001-08402 Rev. *J
Page 13 of 16
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CY62136FV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP Z44-II, 51-85087
PIN 1 I.D.
11.938 (0.470)
11.735 (0.462)
10.262 (0.404)
10.058 (0.396)
1
22
Z Z Z
Z X Z
AA
44
23
BOTTOM VIEW
TOP VIEW
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
EJECTOR MARK
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
BASE PLANE
10.262 (0.404)
10.058 (0.396)
0.10 (.004)
18.517 (0.729)
18.313 (0.721)
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
0.210 (0.0083)
0.120 (0.0047)
0°-5°
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
DIMENSION IN MM (INCH)
MAX
MIN.
Acronyms
Acronym
51-85087 *C
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
degree Celsius
CE
chip enable
MHz
Mega Hertz
CMOS
complementary metal oxide semiconductor
A
micro Amperes
I/O
input/output
s
micro seconds
OE
output enable
mA
milli Amperes
SRAM
static random access memory
ns
nano seconds
TSOP
thin small outline package
%
percent
VFBGA
very fine-pitch ball gird array
pF
pico Farads
WE
write enable

ohms
V
Volts
W
Watts
Document Number: 001-08402 Rev. *J
Symbol
Unit of Measure
Page 14 of 16
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CY62136FV30 MoBL®
Document History Page
Document Title: CY62136FV30 MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 001-08402
Submission
Orig. of
Rev. ECN No.
Date
Change
Description of Change
**
467351
See ECN
NXR
New datasheet
*A
797956
See ECN
VKN
Converted from preliminary to final
Changed ISB1(typ) and ISB1(max) specification from 0.5 A to 1.0 A and
2.5 A to 5.0 A, respectively
Changed ISB2(typ) and ISB2(max) specification from 0.5 A to 1.0 A and
2.5 A to 5.0 A, respectively
Changed ICCDR(typ) and ICCDR(max) specification from 0.5 A to 1.0 A and
2.5 A to 4.0 A, respectively
Changed ICC(max) specification from 2.25 A to 2.5 A
*B
869500
See ECN
VKN
Added Automotive information
Updated Ordering information table
Added footnote 12 related to tACE
*C
901800
See ECN
VKN
Added footnote 9 related to ISB2 and ICCDR
Made footnote 13 applicable to AC parameters from tACE
*D
1371124
See ECN
VKN/AESA Converted Automotive information from preliminary to final
Changed IIX min spec from –1 A to –4 A and IIX max spec from +1 A to +4 A
Changed IOZ min spec from –1 A to –4 A and IOZ max spec from +1 A to +4 A
Changed tDBE spec from 55 ns to 25 ns for automotive part
*E
2594937
10/22/08
NXR/PYRS Added Automotive-A information
Changed tLZBE from 10 ns to 5 ns for -55.
*F
2675375 03/17/2009 VKN/PYRS Corrected typo on page 2 (Corrected ISB2 unit to A from mA)
*G
2882113 02/19/2010 VKN/AESA Corrected typo in the Truth Table
Added Table of Contents
Updated package diagrams
*H
2943752 06/03/2010
VKN
Added footnote related to Chip enable and Byte enables in Truth Table
Updated Package Diagrams
*I
3055169 10/12/2010
RAME
Updated all footnote from tablenote
Added Acronyms and Units of Measure and Ordering Code Definitions.
Updated Package Diagrams
*J
3263825 06/17/2011
RAME
Updated Functional Description (Removed “For best practice recommendations,
refer to the Cypress application note AN1064, SRAM System Guidelines.”).
Updated Data Retention Characteristics (Minimum value of tR parameter).
Updated in new template.
Document Number: 001-08402 Rev. *J
Page 15 of 16
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CY62136FV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-08402 Rev. *J
Revised June 17, 2011
Page 16 of 16
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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