TI ADS8405IBPFBT 16-bit, 1.25-msps, unipolar pseudo differential input, micropower sampling analog-to-digital converter with parallel interface Datasheet

 ADS8405
SLAS427 – DECEMBER 2004
16-BIT, 1.25-MSPS, UNIPOLAR PSEUDO-DIFFERENTIAL INPUT, MICROPOWER
SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Unipolar Pseudo-Differential Input, 0 V to Vref
16-Bit NMC at 1.25 MSPS
±2 LSB INL Max, -1/+1.5 LSB DNL
86 dB SNR, -90 dB THD at 100 kHz Input
Zero Latency
Internal 4.096-V Reference
High-Speed Parallel Interface
Single 5-V Analog Supply
Wide I/O Supply: 2.7 V to 5.25 V
Low Power: 155 mW at 1.25 MHz Typ
Pin Compatible With ADS8411/8401
48-Pin TQFP Package
•
•
•
DWDM
Instrumentation
High-Speed, High-Resolution, Zero Latency
Data Acquisition Systems
Transducer Interface
Medical Instruments
Communications
DESCRIPTION
The ADS8405 is a 16-bit, 1.25-MHz A/D converter
with an internal 4.096-V reference. The device includes a 16-bit capacitor-based SAR A/D converter
with inherent sample and hold. The ADS8405 offers a
full 16-bit interface and an 8-bit option where data is
read using two 8-bit read cycles if necessary.
The ADS8405 has a unipolar pseudo-differential input. It is available in a 48-lead TQFP package and is
characterized over the industrial -40°C to 85°C temperature range.
High Speed SAR Converter Family
Type/Speed
18-Bit Pseudo-Diff
500 kHz
~600 kHz
ADS8383
750 kHz
1 MHz
1.25 MHz
2 MHz
3 MHz
4 MHz
ADS8381
ADS8380 (S)
18-Bit Pseudo-Bipolar, Fully Diff
ADS8382 (S)
16-Bit Pseudo-Diff
ADS8401/05
ADS8411
16-Bit Pseudo-Bipolar, Fully Diff
ADS8371
ADS8402/06
ADS8412
14-Bit Pseudo-Diff
ADS7890 (S)
12-Bit Pseudo-Diff
ADS7891
ADS7886
SAR
+IN
−IN
+
_
CDAC
ADS7881
Output
Latches
and
3-State
Drivers
BYTE
16-/8-Bit
Parallel DATA
Output Bus
Comparator
REFIN
REFOUT
4.096-V
Internal
Reference
Clock
Conversion
and
Control Logic
RESET
CONVST
BUSY
CS
RD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
ORDERING INFORMATION (1)
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES
RESOLUTION
(BIT)
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ADS8405I
–4 to +4
–2 to +2
15
48 Pin TQFP
PFB
–40°C to 85°C
ADS8405IB
(1)
–2 to +2
–1 to +1.5
16
48 Pin TQFP
PFB
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
ADS8405IPFBT
Tape and reel
250
ADS8405IPFBR
Tape and reel
1000
ADS8405IBPFBT
Tape and reel
250
ADS8405IBPFBR
Tape and reel
1000
–40°C to 85°C
For the most current specifications and package information, refer to our website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Voltage
+IN to AGND
–0.4 V to +VA + 0.1 V
–IN to AGND
–0.4 V to 0.5 V
+VA to AGND
–0.3 V to 7 V
+VBD to BDGND
+VA to +VBD
–0.3 V to 7 V
–0.3 V to 2.55 V
Digital input voltage to BDGND
–0.3 V to +VBD + 0.3 V
Digital output voltage to BDGND
–0.3 V to +VBD + 0.3 V
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–65°C to 150°C
Junction temperature (TJ max)
TQFP package
Power dissipation
θJA thermal impedance
Lead temperature, soldering
(1)
2
150°C
(TJMax – TA)/θJA
86°C/W
Vapor phase (60 sec)
215°C
Infrared (15 sec)
220°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage
(1)
+IN – (–IN)
Absolute input voltage
0
Vref
+IN
–0.2
Vref + 0.2
–IN
–0.2
0.2
V
V
Input capacitance
25
pF
Input leakage current
0.5
nA
16
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
(2) (3)
INL
Integral linearity
DNL
Differential linearity
EO
Offset error (4)
15
ADS8405IB
16
ADS8405I
–4
±2
4
ADS8405IB
–2
±1
2
ADS8405I
–2
±1
2
ADS8405IB
–1
±0.75
1.5
ADS8405I
–3
±1
3
mV
–1.5
±0.5
1.5
mV
ADS8405IB
ADS8405I
Gain error (4) (5)
EG
ADS8405I
ADS8405IB
–0.15
0.15
–0.098
0.98
Noise
DC Power supply rejection ratio
Bits
At FFFFh output code, +VA = 4.75 V
to 5.25 V, Vref = 4.096 V (4)
LSB
LSB
%FS
60
µV RMS
2
LSB
SAMPLING DYNAMICS
Conversion time
500
Acquisition time
150
650
ns
1.25
MHz
ns
Throughput rate
Aperture delay
2
ns
Aperture jitter
25
ps
Step response
100
ns
Overvoltage recovery
100
ns
VIN = 4 Vp-p at 100 kHz
–90
dB
VIN = 4 Vp-p at 500 kHz
–88.5
dB
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion (6)
SNR
Signal-to-noise ratio
VIN = 4 Vp-p at 100 kHz
86
dB
SINAD
Signal-to-noise + distortion
VIN = 4 Vp-p at 100 kHz
85
dB
VIN = 4 Vp-p at 100 kHz
90
dB
VIN = 4 Vp-p at 500 kHz
88
dB
5
MHz
SFDR
Spurious free dynamic range
-3dB Small signal bandwidth
EXTERNAL VOLTAGE REFERENCE INPUT
Reference voltage at REFIN, Vref
Reference resistance
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(7)
2.5
4.096
500
4.2
V
kΩ
Ideal input span, does not include gain or offset error.
LSB means least significant bit
This is endpoint INL, not best fit.
Measured relative to an ideal full-scale input (+IN – (–IN)) of 4.096 V.
This specification does not include the internal reference voltage error and drift.
Calculated on the first nine harmonics of the input frequency.
Can vary ±20%
3
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
SPECIFICATIONS (continued)
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
120
ms
INTERNAL REFERENCE OUTPUT
Internal reference start-up time
From 95% (+VA), with 1-µF storage
capacitor
Vref range
IOUT = 0
Source current
Static load
Line regulation
+VA = 4.75 V to 5.25 V
0.6
mV
Drift
IOUT = 0
36
PPM/C
4.065
4.096
4.13
V
10
µA
DIGITAL INPUT/OUTPUT
Logic family - CMOS
VIH
High-level input voltage
IIH = 5 µA
+VBD – 1
VIL
Low-level input voltage
IIL = 5 µA
–0.3
+VBD + 0.3
0.8
VOH
High-level output voltage
IOH = 2 TTL loads
+VBD – 0.6
+VBD
VOL
Low-level output voltage
IOL = 2 TTL loads
0
0.4
V
Data format - straight binary
POWER SUPPLY REQUIREMENTS
Power supply voltage
+VA Supply current
Power dissipation (8)
(8)
+VBD
2.7
+VA
4.75
3
5.25
V
5
5.25
fs = 1.25 MHz
31
34
mA
V
fs = 1.25 MHz
155
170
mW
85
°C
TEMPERATURE RANGE
Operating free-air
(8)
4
–40
This includes only VA+ current. +VBD current is typically 1 mA with 5-pF load capacitance on output pins.
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V
(1) (2) (3)
PARAMETER
MIN
tCONV
Conversion time
500
tACQ
Acquisition time
150
tpd1
CONVST low to BUSY high
tpd2
Propagation delay time, end of conversion to BUSY low
tw1
Pulse duration, CONVST low
tsu1
Setup time, CS low to CONVST low
tw2
Pulse duration, CONVST high
TYP
MAX
UNIT
650
ns
ns
40
ns
5
ns
20
ns
0
ns
20
ns
CONVST falling edge jitter
10
tw3
Pulse duration, BUSY signal low
tw4
Pulse duration, BUSY signal high
th1
Hold time, first data bus data transition (RD low, or CS low for read
cycle, or BYTE input changes) after CONVST low
td1
tsu2
tw5
Pulse duration, RD low
ten
Enable time, RD low (or CS low for read cycle) to data valid
td2
Delay time, data hold from RD high
0
td3
Delay time, BYTE rising edge or falling edge to data valid
2
tw6
Pulse duration, RD high
20
ns
tw7
Pulse duration, CS high
20
ns
th2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
50
ns
tsu3
Setup time, BYTE transition to RD falling edge
0
ns
th3
Hold time, BYTE transition to RD falling edge
0
tdis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
20
ns
td5
Delay time, end of conversion to MSB data valid
10
ns
tsu4
Byte transition setup time, from BYTE transition to next BYTE
transition
50
ns
td6
Delay time, CS rising edge to BUSY falling edge
50
ns
td7
Delay time, BUSY falling edge to CS rising edge
50
ns
tsu(AB)
Setup time, from the falling edge of CONVST (used to start the valid
conversion) to the next falling edge of CONVST (when CS = 0 and
CONVST used to abort) or to the next falling edge of CS (when CS is
used to abort)
60
tsu5
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
th4
Hold time, data (MSB) from previous conversion hold valid from
falling edge of CONVST
(1)
(2)
(3)
Min(tACQ)
ps
ns
610
ns
40
ns
Delay time, CS low to RD low (or BUSY low to RD low when CS = 0)
0
ns
Setup time, RD high to CS high
0
ns
50
ns
20
ns
ns
20
ns
ns
500
MAX(tCONV) + MAX(td5)
ns
ns
MIN(tCONV)
ns
All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
See timing diagrams.
All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins.
5
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V (1) (2) (3)
PARAMETER
MIN
TYP
MAX
UNIT
650
ns
tCONV
Conversion time
500
tACQ
Acquisition time
150
tpd1
CONVST low to BUSY high
50
ns
tpd2
Propagation delay time, end of conversion to BUSY low
10
ns
tw1
Pulse duration, CONVST low
tsu1
Setup time, CS low to CONVST low
tw2
Pulse duration, CONVST high
ns
20
ns
0
ns
20
ns
CONVST falling edge jitter
10
tw3
Pulse duration, BUSY signal low
tw4
Pulse duration, BUSY signal high
th1
Hold time, first data bus transition (RD low, or CS low for read cycle,
or BYTE input changes) after CONVST low
40
ns
td1
Delay time, CS low to RD low (or BUSY low to RD low when CS = 0)
0
ns
tsu2
Setup time, RD high to CS high
0
ns
tw5
Pulse duration, RD low
50
ns
ten
Enable time, RD low (or CS low for read cycle) to data valid
td2
Delay time, data hold from RD high
0
td3
Delay time, BYTE rising edge or falling edge to data valid
2
tw6
Pulse duration, RD high
20
ns
tw7
Pulse duration, CS high
20
ns
th2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
50
ns
tsu3
Setup time, BYTE transition to RD falling edge
0
ns
th3
Hold time, BYTE transition to RD falling edge
0
tdis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
30
ns
td5
Delay time, end of conversion to MSB data valid
20
ns
tsu4
Byte transition setup time, from BYTE transition to next BYTE
transition
50
ns
td6
Delay time, CS rising edge to BUSY falling edge
50
ns
td7
Delay time, BUSY falling edge to CS rising edge
50
ns
tsu(AB)
Setup time, from the falling edge of CONVST (used to start the valid
conversion) to the next falling edge of CONVST (when CS = 0 and
CONVST used to abort) or to the next falling edge of CS (when CS is
used to abort)
70
tsu5
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
th4
Hold time, data (MSB) from previous conversion hold valid from
falling edge of CONVST
(1)
(2)
(3)
6
Min(tACQ)
ps
ns
610
ns
30
ns
ns
30
ns
ns
500
MAX(tCONV) + MAX(td5)
ns
ns
MIN(tCONV)
All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
See timing diagrams.
All timings are measured with 10-pF equivalent loads on all data bits and BUSY pins.
ns
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
PIN ASSIGNMENTS
BUSY
BDGND
+VBD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
BDGND
PFB PACKAGE
(TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
3
4 5
6 7 8
13
9 10 11 12
REFIN
REFOUT
NC
+VA
AGND
+IN
-IN
AGND
+VA
+VA
1 2
+VBD
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
AGND
AGND
+VA
AGND
AGND
+VBD
RESET
BYTE
CONVST
RD
CS
+VA
AGND
AGND
+VA
REFM
REFM
NC - No connection
7
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
Terminal Functions
NAME
AGND
BDGND
NO.
I/O
DESCRIPTION
5, 8, 11, 12, 14,
15, 44, 45
–
Analog ground
25, 35
–
Digital ground for bus interface digital supply
BUSY
36
O
Status output. High when a conversion is in progress.
BYTE
39
I
Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most
significant bits is folded back to high byte of the 16 most significant pins DB[15:8].
CONVST
40
I
Convert start. The falling edge of this input ends the acquisition period and starts the hold
period.
CS
42
I
Chip select. The falling edge of this input starts the acquisition period.
8-Bit Bus
Data Bus
16-Bit Bus
BYTE = 0
BYTE = 1
BYTE = 0
DB15
16
O
D15 (MSB)
D7
D15 (MSB)
DB14
17
O
D14
D6
D14
DB13
18
O
D13
D5
D13
DB12
19
O
D12
D4
D12
DB11
20
O
D11
D3
D11
DB10
21
O
D10
D2
D10
DB9
22
O
D9
D1
D9
DB8
23
O
D8
D0 (LSB)
D8
DB7
26
O
D7
All ones
D7
DB6
27
O
D6
All ones
D6
DB5
28
O
D5
All ones
D5
DB4
29
O
D4
All ones
D4
DB3
30
O
D3
All ones
D3
DB2
31
O
D2
All ones
D2
DB1
32
O
D1
All ones
D1
DB0
33
O
D0 (LSB)
All ones
D0 (LSB)
–IN
7
I
Inverting input channel
+IN
6
I
Noninverting input channel
NC
3
–
No connection
REFIN
1
I
Reference input
REFM
47, 48
I
Reference ground
REFOUT
2
O
Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when the
internal reference is used.
RESET
38
I
Current conversion is aborted and output latches are cleared (set to zeros) when this pin is
asserted low. RESET works independantly of CS.
RD
41
I
Synchronization pulse for the parallel output. When CS is low, this serves as the output enable
and puts the previous conversion result on the bus.
+VA
4, 9, 10, 13, 43,
46
–
Analog power supplies, 5-V dc
24, 34, 37
–
Digital power supply for bus
+VBD
8
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TIMING DIAGRAMS
tw2
tw1
CONVST
(used in normal
conversion)
tcycle
CONVST
(used in ABORT)
tsu(AB)
tpd1
tsu(AB)
tpd2
tw4
tpd1
tw3
BUSY
tsu1
tw7
td7
CS
td6
CONVERT†
tCONV
tCONV
SAMPLING†
(When CS Toggle)
tACQ
BYTE
tsu4
th1
tsu2
td1
th2
RD
Data to
be read†
Invalid
Previous Conversion
th4
tdis
ten
tsu5
DB[15:8]
Invalid
Current Conversion
Hi−Z
Hi−Z
D [15:8]
DB[7:0]
Hi−Z
D [7:0]
Hi−Z
D [7:0]
†Signal
internal to device
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
9
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TIMING DIAGRAMS (continued)
tw1
CONVST
(used in normal
conversion)
tw2
tcycle
CONVST
(used in ABORT)
tsu(AB)
tpd1
tsu(AB)
tpd2
tw4
tw3
BUSY
tw7
tsu1
td7
CS
td6
CONVERT†
tCONV
tCONV
SAMPLING†
(When CS Toggle)
tACQ
BYTE
th1
RD = 0
Data to
be read†
tdis
ten
DB[15:8]
DB[7:0]
†Signal
Invalid
Current Conversion
tsu5
Hi−Z
Previous
D [15:8]
Hi−Z
Hi−Z
Previous
D [7:0]
Hi−Z
internal to device
tdis
Invalid
Previous Conversion
th4
tsu4
th2
ten
D [15:8]
D [7:0]
D [7:0]
Hi−Z
Repeated
D [15:8]
Hi−Z
Repeated
D [7:0]
ten
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
10
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TIMING DIAGRAMS (continued)
tw1
tw2
CONVST
(used in normal
conversion)
tcycle
CONVST
(used in ABORT)
tsu(AB)
tpd1
tsu(AB)
tpd2
tw4
tpd1
tw3
BUSY
CS = 0
CONVERT†
tCONV
tCONV
t(ACQ)
SAMPLING†
(When CS = 0)
BYTE
tsu4
th1
th2
RD
tdis
ten
Data to
be read†
th4
DB[15:8]
DB[7:0]
†Signal
Invalid
Invalid
Previous Conversion
Current Conversion
tsu5
Hi−Z
Hi−Z
D [15:8]
D [7:0]
D [7:0]
Hi−Z
Hi−Z
internal to device
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
11
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TIMING DIAGRAMS (continued)
tw1
CONVST
(used in normal
conversion)
tw2
tcycle
CONVST
(used in ABORT)
tsu(AB)
tpd1
tsu(AB)
tpd2
tw4
tpd1
tpd2
tw3
BUSY
CS = 0
CONVERT†
tCONV
tCONV
tACQ
SAMPLING†
(When CS Toggle)
th1
th1
BYTE
RD = 0
td3
td3
td5
th4
tsu5
Previous
MSB
Invalid
DB[15:8]
Previous Previous
LSB
LSB
Invalid
DB[7:0]
†Signal
td5
th4
td3
tsu5
Invalid
MSB
LSB
MSB
MSB
LSB
MSB
Invalid
internal to device
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read
CS
RD
tsu4
BYTE
ten
tdis
tdis
ten
DB[15:0]
td3
Hi−Z
Valid
Hi−Z
Valid
Valid
Figure 5. Detailed Timing for Read Cycles
12
Hi−Z
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TYPICAL CHARACTERISTICS
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz
(unless otherwise noted)
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
HISTOGRAM (DC Code Spread)
HALF SCALE 131071 CONVERSIONS
86.8
80000
70000
60000
SNR − Signal-to-Noise Ratio − dB
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Code = 65292
50000
40000
30000
20000
10000
86.4
86.2
86
85.8
85.6
85.4
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
65295
65292
65289
85.2
−40 −25 −10 5
20
35
50
65
80
TA − Free-Air Temperature − C
Figure 6.
Figure 7.
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
83.6
13.6
ENOB − Effective Number of Bits − Bits
SINAD − Signal-to-Noise and Distortion − dB
0
86.6
83.4
83.2
83
82.8
82.6
82.4
82.2
82
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
81.8
−40 −25 −10 5
20 35 50 65
TA − Free-Air Temperature − C
Figure 8.
13.55
13.5
13.45
13.4
13.35
13.3
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
13.25
80
−40 −25 −10 5
20
35
50
65
80
TA − Free-Air Temperature − C
Figure 9.
13
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
95
−90
THD − Total Harmonic Distortion − dB
SFDR − Spurious Free Dynamic Range − dB
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
94
93
92
91
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
90
−40 −25 −10 5
20
35
50
65
−94
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
86.7
86.6
86.5
86.4
86.3
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
86
13.9
13.85
13.8
13.75
13.7
13.65
13.6
13.55
13.45
13.4
10 20 30 40 50 60 70 80 90 100
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
13.5
0
50 60
70 80 90 100
Figure 12.
Figure 13.
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
85.5
85
84.5
84
83.5
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
83
82.5
0
10 20 30 40 50 60 70 80 90 100
fi − Input Frequency − kHz
Figure 14.
SFDR − Spurious Free Dynamic Range − dB
SINAD − Signal-to-Noise and Distortion − dB
10 20 30 40
fi − Input Frequency − kHz
fi − Input Frequency − kHz
14
80
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
ENOB − Effective Number of Bits − Bits
SNR − Signal-to-Noise Ratio − dB
−93
Figure 11.
86.8
0
−92
Figure 10.
86.9
86.1
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
−95
−40 −25 −10 5
20 35 50 65
TA − Free-Air Temperature − C
80
TA − Free-Air Temperature − C
86.2
−91
101
100
99
98
97
96
95
94
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
93
92
91
0
10 20 30 40 50 60 70 80 90 100
fi − Input Frequency − kHz
Figure 15.
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
29
fi = 50 kHz,
Full Scale Input,
+VA = 5 V,
+VBD = 3 V,
Int Ref = 4.096 V
−92
−93
−94
−95
−96
−97
−98
−99
0
27.5
27
26.5
26
25
250
10 20 30 40 50 60 70 80 90 100
fi − Input Frequency − kHz
750
1000
Figure 16.
Figure 17.
GAIN ERROR
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
SUPPLY VOLTAGE
+VBD = 3.3 V,
TA = 25°C,
Ext Ref = 4.096 V
Offset Voltage − mV
0.25
0.05
0
−0.05
0.2
0.15
0.1
0.05
−0.1
−0.15
4.75
5
0
4.75
5.25
VCC − Supply Voltage − V
5
VCC − Supply Voltage − V
Figure 18.
Figure 19.
INTERNAL VOLTAGE REFERENCE
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
4.093
0.5
4.092
0.4
4.091
0.3
Gain Error − mV
4.090
4.089
4.088
4.087
4.086
5.25
+VA = 5 V,
+VBD = 3.3 V,
Ext Ref = 4.096 V
0.2
0.1
0
−0.1
−0.2
4.085
+VA = 5 V
+VBD = 3.3 V
4.084
−0.3
−0.4
4.083
4.082
1250
0.3
+VBD = 3.3 V,
TA = 25°C,
Ext Ref = 4.096 V
0.1
Internal Reference Output Voltage − V
500
Sample Rate − KSPS
0.15
Gain Error − mV
28
25.5
−100
−101
+VA = 5 V,
+VBD = 3.3 V,
TA = 25°C,
Int Ref = 4.096 V
28.5
I CC − Supply Current − mA
THD − Total Harmonic Distortion − dB
−91
SUPPLY CURRENT
vs
SAMPLE RATE
−40 −25 −10
5
20
35
50
65
TA − Free-Air Temperature − C
Figure 20.
80
−0.5
−40 −25 −10 5
20 35 50 65
TA − Free-Air Temperature − C
80
Figure 21.
15
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
29.2
0.5
+VA = 5 V,
+VBD = 3.3 V,
Ext Ref = 4.096 V
Offset Voltage − mV
0.4
0.35
0.3
0.25
0.2
0.15
0.1
28.8
28.6
28.4
28.2
28
0.05
0
−40 −25 −10 5
20
35
50
65
27.8
80
−40 −25 −10
35
50
65
Figure 22.
Figure 23.
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
80
1.5
Max
INL − Integral Nonlinearity − Bits
0.6
0.4
0.2
+VA = 5 V,
+VBD = 3.3 V,
Ext Ref = 4.096 V
0
−0.2
Min
−0.4
−0.6
20
35
50
65
Max
1
0.5
+VA = 5 V,
+VBD = 3.3 V,
Ext Ref = 4.096 V
0
−0.5
Min
−1
−1.5
−40 −25 −10
80
TA − Free-Air Temperature − C
5
20
35
50
65
80
TA − Free-Air Temperature − C
Figure 24.
Figure 25.
DIFFERENTIAL NONLINEARITY
vs
REFERENCE VOLTAGE
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
2
2
1.5
INL − Integral Nonlinearity − Bits
DNL − Differential Nonlinearity − Bits
20
TA − Free-Air Temperature − C
−0.8
−40 −25 −10 5
Max
1
0.5
+VA = 5 V,
+VBD = 3.3 V,
Ext Ref = Varied
0
−0.5
Min
−1
−1.5
1.5
Max
1
0.5
0
+VA = 5 V,
+VBD = 3.3 V,
Ext Ref = Varied
−0.5
−1
Min
−1.5
−2
2.5
3
3.5
VREF − Reference Voltage − V
Figure 26.
16
5
TA − Free-Air Temperature − C
0.8
DNL − Differential Nonlinearity − Bits
+VA = 5 V,
+VBD = 3.3 V
29
I CC − Supply Current − mA
0.45
4
−2
2.5
3
3.5
VREF − Reference Voltage − V
Figure 27.
4
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
DNL
2.5
+VA = 5 V,
+VBD = 5 V,
TA = 25°C,
Ext Ref = 4.096 V
2
1.5
DNL − LSBs
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
16384
32768
Code
49152
65536
Figure 28.
INL
2.5
+VA = 5 V,
+VBD = 5 V,
TA = 25°C,
Ext Ref = 4.096 V
2
1.5
INL − LSBs
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
16384
32768
Code
49152
65536
Figure 29.
FFT
0
+VA = 5 V,
+VBD = 3.3 V,
REF +32768 Points,
fi = 100 kHz,
fs = 1.25 MHz,
TA = 25°C,
Int Ref = 4.096 V
Amplitude
−50
−100
−150
−200
0
200
400
Frequency − kHz
600
Figure 30.
17
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
APPLICATION INFORMATION
MICROCONTROLLER INTERFACING
ADS8405 to 8-Bit Microcontroller Interface
Figure 31 shows a parallel interface between the ADS8405 and a typical microcontroller using the 8-bit data bus.
The BUSY signal is used as a falling-edge interrupt to the microcontroller.
Analog 5 V
0.1 µF
AGND
10 µF
Ext Ref Input
0.1 µF
1 µF
Micro
Controller
−IN
REFM
AGND
+IN
+VA
REFIN
Analog Input
Digital 3 V
GPIO
CS
BYTE
GPIO
P[7:0]
ADS8405
DB[15:8]
RD
CONVST
BUSY
RD
GPIO
INT
0.1 µF
BDGND
BDGND
+VBD
Figure 31. ADS8405 Application Circuitry (Using an External Reference)
Analog 5 V
0.1 µF
AGND
10 µF
0.1 µF
AGND
AGND
REFM
REFIN
REFOUT
+VA
1 µF
ADS8405
Figure 32. Using the Internal Reference
PRINCIPLES OF OPERATION
The ADS8405 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 31
for the application circuit for the ADS8405.
The conversion clock is generated internally. The conversion time of 650 ns is capable of sustaining a 1.25-MHz
throughput.
18
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
REFERENCE
The ADS8405 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal
reference is included. When an internal reference is used, pin 2 (REFOUT) should be connected to pin 1
(REFIN) with a 0.1-µF decoupling capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47
and 48 (REFM) (see Figure 32). The internal reference of the converter is double buffered. If an external
reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer
is also used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left
unconnected (floating) if an external reference is used.
ANALOG INPUT
When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the
internal capacitor array. The voltage on the –IN input is limited between –0.2 V and 0.2 V, allowing the input to
reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to
Vref + 0.2 V. The input span (+IN – (–IN)) is limited to 0 V to Vref.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8405 charges the internal capacitor array during the sample
period. After this capacitance has been fully charged, there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition
time (150 ns) of the device. When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used.
Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different setting times. This may result in offset error,
gain error, and linearity error which varies with temperature and input voltage. A typical input circuit using TI's
THS4031 is shown in Figure 33.
300 15 V
0.1 F
1 F
300 G = +2
_
15 THS4031
VIN
+
+IN
ADS8405
1 F
6800 pF
−IN
0.1 F
−15 V
Figure 33. Using the THS4031 with the ADS8405
19
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
DIGITAL INTERFACE
Timing And Control
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8405 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high) while CS is low. The ADS8405 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high after CONVST
goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended.
Sampling starts as soon as the conversion is over when CS is tied low or starts with the falling edge of CS when
BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
Reading Data
The ADS8405 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active
when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST.
This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be
attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used
for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the higher
byte of the bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
ANALOG VALUE
DIGITAL OUTPUT
Full scale range
+Vref
Least significant bit (LSB)
(+Vref)/65536
STRAIGHT BINARY
Full scale
(+Vref) – 1 LSB
1111 1111 1111 1111
FFFF
Midscale
(+Vref)/2
1000 0000 0000 0000
8000
Midscale – 1 LSB
(+Vref)/2 – 1 LSB
0111 1111 1111 1111
7FFF
Zero
0V
0000 0000 0000 0000
0000
BINARY CODE
HEX CODE
The output data is a full 16-bit word (D15 – D0) on the DB15 – DB0 pins (MSB-LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15 – DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15 – DB8, then bringing BYTE high. When BYTE is high, the low bits (D7 – D0) appear on pins DB15 –
D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Conversion Data Readout
BYTE
20
DATA READ OUT
DB15–DB8 Pins
DB7–DB0 Pins
High
D7–D0
All one's
Low
D15–D8
D7-D0
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
RESET
RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time
is 25 ns. The current conversion is aborted no later than 50 ns after the converter is in reset mode. In addition, all
output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation mode no
later than 20 ns after the RESET input is brought high.
The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except
for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling
edge of CS, whichever is later.
Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when
the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific
converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an
internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does
not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following
steps.
• Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy
the timing as specified by the timing parameter tsu(AB) specified in the timing characteristics table to ensure a
reset. The falling edge of CONVST starts a reset. The timing is the same as a reset using the dedicated
RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
• Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by
the timing parameter tsu(AB) specified in the timing characteristics table to ensure a reset. The falling edge of
CS causes a reset. The timing is the same as a reset using the dedicated RESET pin except the instance of
the falling edge is replaced by the falling edge of CS.
POWER-ON INITIALIZATION
RESET is not required after power on. An internal power-on reset circuit generates the reset. To ensure that all
of the registers are cleared, the three conversion cycles must be given to the converter after power on.
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8405 circuitry.
As the ADS8405 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving
any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient
voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS8405 draws very little current from an external reference, as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and a 1-µF storage capacitor
are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the
same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
21
ADS8405
www.ti.com
SLAS427 – DECEMBER 2004
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. Power to the ADS8405
should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device
as possible. See Table 2 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is
recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor
or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply,
removing the high frequency noise.
Table 2. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE SUPPLY PINS
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
Pin pairs that require shortest path to decoupling capacitors
(4,5), (8,9), (10,11), (13,15),
(43,44), (45,46)
(24,25), (34, 35)
Pins that require no decoupling
12, 14
37
22
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS8405IBPFBR
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8405I
B
ADS8405IBPFBRG4
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8405I
B
ADS8405IBPFBT
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8405I
B
ADS8405IBPFBTG4
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8405I
B
ADS8405IPFBR
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8405I
ADS8405IPFBRG4
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8405I
ADS8405IPFBT
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8405I
ADS8405IPFBTG4
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8405I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS8405IBPFBR
TQFP
PFB
48
ADS8405IBPFBT
TQFP
PFB
ADS8405IPFBR
TQFP
PFB
ADS8405IPFBT
TQFP
PFB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
48
250
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
48
250
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8405IBPFBR
TQFP
PFB
48
1000
367.0
367.0
38.0
ADS8405IBPFBT
TQFP
PFB
48
250
367.0
367.0
38.0
ADS8405IPFBR
TQFP
PFB
48
1000
367.0
367.0
38.0
ADS8405IPFBT
TQFP
PFB
48
250
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
Similar pages