AD AD1970 Digital btsc encoder with integrated adc and dac Datasheet

Digital BTSC Encoder
with Integrated ADC and DAC
AD1970
APPLICATIONS
FEATURES
Digital set top box
DVD player
DVD recorder
Complete BTSC encoder
Pilot tone generator
Includes subcarrier modulation
Channel separation: 30 dB
Bandwidth up to 14 kHz
Stereo analog or digital input
Phat-Stereo™ algorithm for stereo image enhancement
Dialog enhancement function for playing wide dynamic
range video sources over built-in TV speakers
Includes L − R dual-band compressor
I2C port for control of modes, effects, and parameters
Analog input performance
74 dB dynamic range
−72 dB THD + N
Digital input performance
87 dB dynamic range
−83 dB THD + N
Integrated op amps for analog inputs and outputs
Single-ended output reduces external part count
Integrated PLL generates all clocks from composite video,
48 kHz sample clock, or high speed master clock
Sync stripper to recover video clock from composite
video signal
Output level control for setting aural carrier deviation
GENERAL DESCRIPTION
The AD1970 is a complete analog or digital-in, analog-out
BTSC encoder which includes pilot-tone generation and subcarrier mixing functions. The stereo ADC provides the means
for digitization of the analog baseband audio signal. A built-in
high performance DAC is provided to output the BTSC baseband composite signal. The output of the AD1970 can be
connected with minimal external circuitry to the input of a
4.5 MHz aural FM modulator.
In addition to the digital BTSC encoder, the AD1970 includes a
stereo image enhancement function, Phat Stereo, to increase the
sense of spaciousness available from closely spaced TV
loudspeakers. A dialog enhancement algorithm solves the
problem of playing wide dynamic range sources over limitedperformance TV speakers and amplifiers. An I2C port allows
control of the AD1970’s registers and parameters.
The AD1970 utilizes ADI’s patented multibit Σ-Δ architecture to
provide BTSC performance of up to 87 dB dynamic range and a
THD+N of −83 dB.
Macrovision™-compliant
The AD1970 includes patented BTSC stereo TV technology
licensed from THAT Corporation.
Dolby™ RF mode-compatible
48-pin LQFP plastic package
FUNCTIONAL BLOCK DIAGRAM
AD1970
ADC
DECIMATION
FILTER
ADC
DIGITAL AUDIO
INTERFACE
SYNC
STRIPPER
COMPOSITE
VIDEO
I2C I/O
GROUP
BTSC
ENCODER
CORE
3
4
PLL
BTSC
ENCODED
OUTPUT
CONTROL
REGISTERS
I2C PORT
ADC
VOLUME
CONTROL
DAC
ANALOG
BIAS
05500-001
ANALOG L/R
INPUTS
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD1970
TABLE OF CONTENTS
Specifications..................................................................................... 3
Power-Up Sequence ................................................................... 11
Absolute Maximum Ratings............................................................ 6
Control Port .................................................................................... 12
Package Characteristics (48-Lead LQFP).................................. 6
I2C Port Overview ...................................................................... 12
ESD Caution.................................................................................. 6
I2C Address Decoding................................................................ 12
Pin Configuration and Function Descriptions............................. 7
Input Level Control.................................................................... 13
Theory of Operation ........................................................................ 9
Output Level Control................................................................. 13
Signal Processing ............................................................................ 10
I2C Read/Write Data Formats................................................... 14
Background of BTSC ................................................................. 10
Analog Input/Output ..................................................................... 16
Performance Factors .................................................................. 10
ADC Input................................................................................... 16
Separation Alignment ................................................................ 11
DAC Output................................................................................ 16
Phase Linearity of the External Analog Filter......................... 11
Serial Data Port........................................................................... 16
Input Levels ................................................................................. 11
Serial Data Modes ...................................................................... 16
Clocking and PLL....................................................................... 11
Typical Applications Circuit.......................................................... 18
Crystal Oscillator........................................................................ 11
Outline Dimensions ....................................................................... 19
General Purpose Input/Output (GPIO) Pins ......................... 11
Ordering Guide .......................................................................... 19
REVISION HISTORY
4/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD1970
SPECIFICATIONS
Test conditions, unless otherwise noted
Table 1.
Parameters
Supply Voltages (AVDD, DVDD)
Ambient Temperature
Input Signal
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance
Load Current
Input Voltage High
Input Voltage Low
Conditions
3.3
25
1 kHz, 0.8 VRMS analog, 0 dBFS digital
48
20 Hz to 14 kHz
24
50
±1
2.0
0.8
Unit
V
°C
Hz, V rms, dBFS
kHz
kHz
Bits
pF
mA
V
V
Table 2. Analog Input Performance
Parameter
Maximum Input Level
Output Level
Dynamic Range (20 Hz to 14 kHz, –60 dB Input) (Encoded Output, Left = Right)
THD + Noise (Encoded Output, Left = Right, 20 Hz to 14 kHz)
VIN = 0 dBV rms
Min
Typ
1.0 (2.8)
250
74
Max
Unit
V rms (V p-p)
mV rms
dB
–72
–65
dB
Typ
24
250
87
Max
Unit
Bits
mV rms
dB
–83
–74
dB
Min
0.35
Typ
1.0
2
Max
Unit
VP-P
kΩ
Min
7
Typ
10
Max
13
Unit
mmhos
68
Table 3. Digital Input Performance
Parameter
Resolution
Output Level
Dynamic Range (20 Hz to 14 kHz, –60 dB Input) (Encoded Output, Left = Right)
THD + Noise (Encoded Output, Left = Right, 20 Hz to 14 kHz)
VIN = 0 dBFS
Min
81
Table 4. Video Input
Parameter
Input Signal Level
Input Impedance
Table 5. Crystal Oscillator
Parameter
Transconductance
Rev. 0 | Page 3 of 20
AD1970
Table 6. BTSC Encoder Performance
Parameter
CHANNEL SEPARATION (–25 dB INPUT)
30 Hz to 500 Hz
500 Hz to 5 kHz
5 kHz to 13.5 kHz
CHANNEL SEPARATION AT 1 kHz
0 dB Input
–2 dB Input
FREQUENCY RESPONSE
30 Hz to 10 kHz
30 Hz to 13.5 kHz
Min
Typ
24
18
14
30
21
15
25
24
27
26
–1
–1.5
Max
Unit
dB
dB
dB
+0.5
+0.5
dB
dB
Table 7. Digital I/O
Parameter
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.4 V)
High Level Output Voltage (VOH) IOH = 2 mA (except VID_PRES)
Low Level Output Voltage (VOL) IOL = 2 mA
Min
2.0
Typ
Max
0.4
Unit
V
V
µA
µA
V
V
0.8
10
10
DVDD − 0.6
Table 8. Power
Parameter
SUPPLIES
Voltage, Analog, Digital, PLL
Analog Current
Digital Current
PLL Current
DISSIPATION
All Supplies
Analog Supply
Digital Supply
PLL Supply
Min
Typ
Max
Unit
3.0
30
30
1
3.3
41
38
5
3.6
50
48
8
V
mA
mA
mA
277
135
125
17
mW
mW
mW
mW
Table 9. Temperature Range
Parameter
Specifications Guaranteed
Functionality Guaranteed
Storage
Min
0
–55
Rev. 0 | Page 4 of 20
Typ
25
Max
70
+125
Unit
°C
°C
°C
AD1970
Table 10. Digital Timing
Parameter
tDMD
tDBL
tDBH
tDBL
tDBH
tDLS
tDLH
tDDS
tDDH
tIBC
tISST
tIH
tSDS
tSDH
tSDF
tSDR
tPWS
tPDRP
MCLK Duty Cycle, External 512 fS Mode
MCLK Low Pulse Width, External 512 fS Mode
MCLK High Pulse Width, External 512 fS Mode
MCLK Low Pulse Width, PLL, 256 fS or fS Mode
MCLK High Pulse Width, PLL, 256 fS or fS Mode
LRCLK Setup
LRCLK Hold
SDATA Setup
SDATA Hold
I2C Bus Clock Frequency
I2C Setup Time for Start Condition
I2C Hold Time for Start Condition
SDA Setup Time
SDA Hold Time
SDA Fall Time at 3 mA Sink and 400 pF Load
SDA Rise Time
Pulse Width of Spikes Supressed by the Input Filter
RESETB Low Pulse Width
Rev. 0 | Page 5 of 20
Min
40
15
15
15
15
10
10
10
10
Typ
50
Max
60
400
10
30
50
25
25
300
50
15
Unit
%
ns
ns
ns
ns
ns
ns
ns
ns
kHz
ns
ns
ns
ns
ns
ns
ns
ns
AD1970
ABSOLUTE MAXIMUM RATINGS
Table 11.
DVDD to DGND
ODVDD to DGND
AVDD to AGND
Digital Inputs
Analog Inputs
AGND to DGND
Reference Voltage
Maximum Junction
Temperature
Storage Temperature
Range
Min
–0.3
–0.3
–0.3
DGND – 0.3
AGND – 0.3
–0.3
Max
+3.95
+3.95
+3.95
DVDD + 0.3
AVDD + 0.3
+0.3
(AVDD + 0.3)/2
Unit
V
V
V
V
V
V
V
+125
+150
°C
°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE CHARACTERISTICS (48-LEAD LQFP)
Table 12.
–65
Min
θJA (Thermal Resistance
[Junction-to-Ambient])
θJC (Thermal Resistance
[Junction-to-Case])
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
Typ
72
19.5
Max
Unit
°C/W
°C/W
AD1970
48 47 46 45
44 43
42 41 40 39
DVDD
GPIO2
GPIO3
SDATA
BCLK
LRCLK
DIG_IN_EN
SDA
SCL
ADR1
ADR0
DGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
38 37
DVDD 1
36
DGND
RESETB 2
35
GPIO1
DGND 3
34
GPIO0
DVDD 4
33
XIN
RSVD 5
32
XOUT
31
VID_PRES
30
MCLK
AVDD 8
29
PLL_MODE1
BTSC_OUT 9
28
PLL_MODE0
AGND 10
27
NC
VREF 11
26
VID_IN
FILTCAP 12
25
PGND
AD1970
NC = NO CONNECT
PLL_LF
PVDD
CAPRN
CAPLN
CAPRP
20 21 22 23 24
CAPLP
17 18 19
VIN_IAMPR
AVDD
VIN_IAMPL
14 15 16
VOUT_IAMPL
13
AGND
VIN_OAMP 7
VOUT_IAMPR
TOP VIEW
(Not to Scale)
05500-002
VOUT_OAMP 6
Figure 2. Pin Configuration
Table 13. Pin Function Descriptions
Pin No.
1
2
Pin Name
DVDD
RESETB
Input/Output
3
4
5
6
7
8
9
DGND
DVDD
RSVD
VOUT_OAMP
VIN_OAMP
AVDD
BTSC_OUT
10
11
AGND
VREF
OUT
12
FILTCAP
OUT
13
AVDD
14
15
16
17
AGND
VOUT_IAMPL
VIN_IAMPL
VOUT_IAMPR
IN
OUT
IN
OUT
OUT
IN
OUT
Description
Digital Power.
Reset—Active Low. After RESETB transitions from low to high, the AD1970 BTSC encoder
core goes through an initialization sequence where all registers are set to 0. The
initialization is completed after 1024 MCLK cycles. New values should not be written to
the control port until the initialization is complete.
Digital Ground.
Digital Power. 3.3 V nominal.
Reserved—Connect to DGND.
Output voltage of internal op amp to be used for BTSC output low pass filter.
Negative input of internal op amp to be used for BTSC output low pass filter.
Analog Power.
Encoded BTSC Output. The nominal output voltage for a 300 Hz, 0 dB mono input signal is
250 mV rms.
Analog Ground.
Connection for voltage reference noise reduction capacitor. The nominal VREF voltage is
1.5 V; the analog gain scales directly with the voltage on this pin. Any ac signal on this pin
causes distortion and therefore a large decoupling capacitor should be used to ensure the
voltage on VREF is clean.
Connection for DAC noise reduction capacitor. A 10 µF capacitor should be connected to
this pin to reduce the noise on an internal DAC biasing point to provide the highest
performance. It may not be necessary to connect this pin, depending on the quality of the
layout and grounding used in the application circuit.
Analog Power. 3.3 V nominal. Bypass capacitors should be placed close to the pins and
connected directly to the analog ground plane.
Analog Ground.
Output of internal op amp for left channel input amplifier.
Negative input of internal op amp for left channel input amplifier.
Output of internal op amp for right channel input amplifier.
Rev. 0 | Page 7 of 20
AD1970
Pin No.
18
19
Pin Name
VIN_IAMPR
CAPLP
Input/Output
IN
I/O
20
CAPLN
I/O
21
CAPRP
I/O
22
CAPRN
I/O
23
PVDD
24
25
26
PLL_LF
PGND
VID_IN
IN
27
28
NC
PLL_MODE0
IN
29
PLL_MODE1
IN
30
MCLK
IN
31
VID_PRES
OUT
32
XOUT
OUT
33
XIN
IN
34
GPIO0
IN/OUT
35
GPIO1
IN/OUT
36
37
38
DGND
DVDD
GPIO2
IN/OUT
39
GPIO3
IN/OUT
40
SDATA
IN/OUT
41
BCLK
IN/OUT
42
LRCLK
IN/OUT
43
44
45
46
47
48
DIG_IN_EN
SDA
SCL
ADR1
ADR0
DGND
IN
IN/OUT
IN
IN
IN
Description
Negative input of internal op amp for right channel input amplifier.
ADC Filter Capacitor Connection (positive left-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
ADC Filter Capacitor Connection (negative left-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
ADC Filter Capacitor Connection (positive right-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
ADC Filter Capacitor Connection (negative right-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
PLL Power. 3.3 V nominal. Bypass capacitors should be placed close to this pin and
connected directly to the PLL ground.
PLL Loop Filter Connection.
PLL Ground. Connect to DGND.
Composite Video Input. Composite video signal input to the sync separator. The sync
output is connected to a PLL that generates the clocks for the AD1970. This pin has an
input impedance of 2 kΩ.
No Connect.
PLL Mode Select Pin 0. The setting of these pins indicates the source and frequency of the
input clock to generate the internal MCLK for the AD1970.
PLL Mode Select Pin 1. The setting of these pins indicates the source and frequency of the
input clock to generate the internal MCLK for the AD1970.
Master Clock Input. This input is used to generate the internal master clock if it is not
derived from the composite video signal on VID_IN. The master clock frequency must be
either fs or 256 × fs, where fs is the input sampling frequency. The PLL_CTRLx pins should
be set to accept the appropriate MCLK input frequency.
Video Present Flag. A high logic level on this pin indicates that a valid composite video
signal is present on the VID_IN pin. Open-drain output.
Crystal Oscillator Output. This pin is the output of the on-board oscillator and should be
connected to one side of a crystal.
Crystal Oscillator Input. This pin is the input to the on-board oscillator and should be
connected to one side of a crystal.
General Purpose I/O 0. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
General Purpose I/O 1. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
Digital Ground.
Digital Power.
General Purpose I/O 2. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
General Purpose I/O 3. This pin can be set to be either a static input or output, with levels
and direction controlled through the I2C port.
Serial Data Input/Output (Before BTSC Encoding). Digital input to the BTSC encoder or
output of the ADC. The serial format is selected by writing to Bits 3:2 of Control Register 1.
Bit Clock Input/Output. Serial bit clock for clocking in the serial data. The interpretation of
BCLK changes according to the serial mode, which is set by writing to the control
registers.
Left/Right Clock Input/Output. Left/right clock for framing the serial input data. The
interpretation of the LRCLK changes according to the serial mode, set by writing to the
control registers.
Digital Input Enable (active high).
I2C Serial Data Input/Output.
I2C Serial Clock Input.
I2C Address 1. The address of the I2C port is set by these pins according to Table 16.
I2C Address 0. The address of the I2C port is set by these pins according to Table 16.
Digital Ground.
Rev. 0 | Page 8 of 20
AD1970
THEORY OF OPERATION
The AD1970 is comprised of a BTSC encoder with stereo
analog inputs and a sync separator to derive the pilot signal
from the composite video stream. Figure 1 shows the block
diagram of the device.
Signal processing parameters are stored in a parameter RAM,
which is initialized on power-up by an internal boot ROM. The
values stored in the parameter RAM control all the filter coefficients, mixing, and dynamics-processing code used in the
BTSC algorithm.
The AD1970 has an I2C port that supports complete read/write
capability of the parameter RAM, as well as a control port and
several other registers that allow the various signal processing
parameters to be controlled. The AD1970 can run as a standalone processor without external control.
The AD1970 has a very flexible serial data input port that allows
for glueless interconnection to a variety of digital signal sources.
The AD1970 can be configured in left-justified, I2S, rightjustified, or DSP serial port-compatible modes. It can support
16, 20, and 24 bits in all modes. The AD1970 accepts serial
audio data in MSB first, twos complement format.
The AD1970 operates from a single 3.3 V power supply. It is
fabricated on a single monolithic integrated circuit and is
housed in a 48-pin LQFP package for operation over the
temperature range of 0°C to 70°C.
Rev. 0 | Page 9 of 20
AD1970
SIGNAL PROCESSING
BACKGROUND OF BTSC
For the receiver to recover this L − R signal, a pilot tone at the
horizontal rate is added to the signal. The receiver has a PLL
that locks to this pilot and generates a signal at the carrier
frequency. This signal is then used to multiply the composite
BTSC-encoded signal, which translates this component back
down to baseband. Once the L + R and L − R signals are
recovered, a simple addition/subtraction circuit (sometimes
referred to as the matrix) can be used to recover the right signal.
Since the pilot tone is added at 15.734 kHz, it is necessary to
reduce the bandwidth of the signal so that audio signals cannot
interfere with the pilot tone. In the AD1970, the bandwidth is
limited to 14 kHz; above this frequency, the response decays
very rapidly.
BTSC is the name of the standard for adding stereo audio capability to the US television system. It is in many ways similar to
the algorithm used for FM stereo broadcasts, with the addition
of a sophisticated compressor circuit to improve the signal-tonoise ratio.
To maintain compatibility with non-BTSC TV receivers, the
processing of mono (L = R) signals is unchanged from the
original pre-BTSC system. The L + R signal is applied to a 75 µs
pre-emphasis filter, and is then applied to a 4.5 MHz FM modulator, which is later added to the video signal to create a
composite video signal.
PERFORMANCE FACTORS
Stereo capability is added by taking the L − R signal, applying it
to a 2-band dynamic compressor, and then multiplying this
signal by a carrier signal at twice the horizontal scanning rate
(Fh), or about 2 × 15.734 kHz. This multiplication is known as
double sideband, suppressed-carrier modulation, and it
effectively translates the compressed L − R spectrum up in
frequency so that it sits above the audio band (see Figure 3).
L–R
To maintain good separation between the left and right
channels, it is necessary to closely match the filtering and
companding standards set forth in the standard (FCC OET60).
Even small errors can result in poor performance. The AD1970
has been programmed to match these standards as accurately as
possible. Typical separation numbers range from 30 dB at
frequencies below 500 Hz to 15 dB at 13.5 kHz. Measuring these
numbers can be difficult, since significant differences exist
between many units sold as reference decoders, which are all
implemented with analog components.
COMPRESSOR
2× Fh CARRIER
L
OSCILLATOR
MATRIX
MAIN
ALGORITHM
FLOW
75µs
PRE-EMPH
FILTER
1/X
RMS
DETECT
GAIN
BANDPASS
SECOND
ORDER
NONLINEAR
FORMULA
RMS
DETECT
GAIN
BANDPASS
FOURTH
ORDER
LPF
EIGHT
ORDER
PRE-EMPH
SECOND
ORDER
SPECTRAL TILT
FILTER
Figure 3. Signal Processing Flow
Rev. 0 | Page 10 of 20
05500-003
L+R
L-R IN
TO
DAC
Fh PILOT
R
AD1970
SEPARATION ALIGNMENT
The BTSC encoder outputs are all specified in terms of the
deviation of the FM 4.5 MHz carrier. For the AD1970, a digital
input level of 0 dB (mono signal) should cause a carrier deviation of ±25 kHz without the 75 µs pre-emphasis filter. In
practice, the pre-emphasis filter can be left in for this adjustment, as long as the frequency is low enough to not be affected
by the filter. It is critical to maintain the proper gain relationship
between the BTSC encoder and the 4.5 MHz FM modulator. A
common mistake is to assume that changing the gain between
the BTSC encoder output and the FM modulator input has the
same effect as changing the audio input level going in to the
BTSC encoder. The presence of a complicated 2-band nonlinear
dynamics processor means that the encoder output must be
connected to the decoder input (through the FM modulation/
demodulation process) with a known gain. If this gain is
changed, then the separation significantly suffers.
When measuring the AD1970 on the bench, it is possible to use
a BTSC reference decoder box, so that the FM modulation/
demodulation process can be skipped. These units have a
method of adjusting the input voltage sensitivity to achieve best
separation. The output level of the AD1970 can also be adjusted
over a wide range using either the I2C control port or by
adjusting the values of the components used in the external
analog low-pass filter that is between the BTSC encoder output
and the input to the FM modulator.
PHASE LINEARITY OF THE EXTERNAL ANALOG
FILTER
If the time-alignment of the pilot to the carrier signal is not
close to 0°, a loss of separation can occur. This means that the
external analog low-pass filter should be a linear-phase design
to provide constant group delay over the range from dc to
50 kHz. A Bessel filter is recommended for this application. The
typical applications circuit (see Figure 8) shows a recommended
design for this filter.
INPUT LEVELS
The maximum input level to the AD1970 changes across
frequency. Table 14 shows the maximum allowable input level
for different frequencies. These values are part of the BTSC
specification, not a function of this chip.
Table 14. Maximum Input Levels to the BTSC Encoder
across Frequency
Frequency (Hz)
20 to 1000
1600
2500
3150
5000
8000
12500
Maximum Input Level (dBFS)
0
−1
−3
−5
−8
−11
−15
CLOCKING AND PLL
The AD1970’s master clock either can be directly fed to the
MCLK pin or generated by a PLL from a composite video signal
input on the VID_IN pin. If the clock input is on the MCLK pin,
the PLL can synthesize the internal clocks from either a clock at
the digital audio frame sync frequency (fS = 48 kHz) or 256 × fS.
The PLL mode is controlled by Pins PLL_MODE0 and
PLL_MODE1. The settings are shown in Table 15.
Table 15. PLL Modes
PLL_MODE1
0
PLL_MODE0
0
0
1
1
1
0
1
Setting
Composite video input (on
VID_IN)
256 × fs (on MCLK)
fs (on MCLK)
PLL bypass
CRYSTAL OSCILLATOR
The AD1970 has an on-board crystal oscillator to generate a
clock that can be used by an RF modulator or other application.
For example, a 4 MHz crystal can be connected as shown in the
application circuit (see Figure 8). The AD1970 does not use this
clock itself, so if it is not needed in an application the XIN pin
should be grounded and the XOUT pin left unconnected.
GENERAL PURPOSE INPUT/OUTPUT (GPIO) PINS
Pins GPIO0, GPIO1, GPIO2, and GPIO3 are set to be inputs or
outputs by Bits 19:16 of Control Register 2. All four default to
input state. These pins do not take an input to or send an output
from the main signal flow. When set as an output, the binary
value on the pins is set according to Bits 15:12 of Control
Register 2. These pins can be used to interface with I/O pins on
a microcontroller and allow hardware control via the I2C bus.
POWER-UP SEQUENCE
The AD1970 has a built-in power-up sequence that initializes
the contents of all internal RAMs. During this time, the
parameter RAM is filled with values from its associated boot
ROM. The data memories are also cleared during this time.
The boot sequence lasts for 1024 MCLK cycles and starts on the
rising edge of the RESETB pin. The user should avoid writing to
or reading from the I2C registers during this period of time.
Rev. 0 | Page 11 of 20
AD1970
CONTROL PORT
I2C PORT OVERVIEW
The AD1970 can be controlled using the I2C port. In general,
there are three parameters that can be controlled: the encoder
output level, the Phat Stereo image enhancement algorithm, and
the dialog enhancement algorithm. It is also possible to write
new data into the parameter RAM to alter the filter coefficients
used in the BTSC encoding process. Since this is a fairly
complex topic and is unnecessary for normal operation of the
chip, the details are not included in this data sheet; please
contact ADI sales if modifications to the BTSC filters are
required.
2
The I C port uses a 2-wire interface consisting of SDA, the
bidirectional data line, and SCL, the clock.
The R/W bit is low for a write operation and high for a read
operation. The 10-bit address word is decoded into either a
location in the parameter RAM or one of the registers. The
number of data bytes varies according to the register or
memory being accessed. The detailed data format diagram for
continuous-mode operation is given in the section.
I2C ADDRESS DECODING
Table 16 shows the address decoding used in the I2C port. Four
different addresses are available to avoid conflicting addresses
on an I2C bus. The I2C address space encompasses a set a
registers and the parameter RAM. The parameter RAM is
loaded on power-up from an on-board boot ROM.
Table 16. I2C Address Settings
ADR1
0
0
1
1
ADR0
0
1
0
1
I2C Address
0x20
0x21
0x22
0x23
Table 17. I2C Port Address Decoding
Register Address
0
Register Name
Input Level Control
Read/Write Word Length
Write: 22 bits
Read: 22 bits
1 to 254
255
256
Parameter RAM
Output Level Control
Control Register 1
257
258
259
260
Control Register 2
ADC Volume Control
Stereo Spreading Control
Dialog Enhancement Control
Rev. 0 | Page 12 of 20
Write: 11 bits
Read: 6 bits
Write: 22 bits
AD1970
Table 18. Control Register 1 Write
INPUT LEVEL CONTROL
This register location controls the input level of both the left
and right channels to the AD1970 BTSC encoding algorithm.
The register defaults to a value of 1.0 (0100000000000000000000
in binary 2.20 format) and allows a maximum of 12 dB of gain
at a full-scale value. This feature allows compatibility with the
Dolby digital specification for proper operation in both RF
mode and line mode. In RF mode, the dialog level is specified at
11 dB higher than the dialog level in line mode. A gain of 11 dB
can be achieved by writing 1.8836 to Address 0.
Register Bits
10:8
7
6
5:4
3:2
1:0
OUTPUT LEVEL CONTROL
The level control of the BTSC-encoded output is controlled
in this register location. The default value is 0.5 (–6 dB,
0010000000000000000000 in binary 2.20 format), or 250 mV
on the DAC output. The output level should not be used as a
volume control. Its intended use, in conjunction with the output
filter, is to match the level with the expected input of the BTSC
decoder. Matching these allows maximum separation between
the left and right encoded channels.
Control Register 1
Control Register 1 is an 11-bit register that controls serial
modes, de-emphasis, mute, power-down, and I2C-to-memory
transfers. Table 18 documents the contents of this register.
Function
Reserved, set to 000
Soft mute (1 = start mute sequence)
Soft power-down (1 = power-down)
Reserved, set to 00
Serial-In mode
00 = I2S
01 = Right-justified
10 = DSP
11 = Left-justified
Word length
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = 16 bits
Table 19. Control Register 1 Read
Register Bits
5:2
1:0
Function
GPIO 3:0 read back
Reserved
Control Register 2
Control Register 2 is a 22-bit write-only register that controls
power down modes, PLL and sync separator controls, and
digital I/O pin functions.
Bits 5:4 and 10:8 are reserved and should be set to 0 at all times.
Table 20. Control Register 2
The audio signal is muted with Bit 7 of the control register.
Register Bits
21
20
19:16
15:12
11:9
8:4
3
2
1
0
The soft power-down bit (Bit 6) stops the internal clocks to the
DSP core, but does not reset the part. The digital power
consumption is reduced to a low level when this bit is asserted.
Reset can only be asserted using the external reset pin.
Bits 3:2 select the serial format from one of four modes. These
different formats are discussed in the section of this data sheet.
The word length bits (1:0) are used in right-justified serial
modes to determine where the MSB is located relative to the
start of the audio frame.
Function
Enable ADC output on serial audio interface
Reserved
GPIO output enable 3:0
GPIO data
PLL shift, default 100
Sync separator slicer voltage; default 10111
ADC power-down
Reference power-down
DAC power-down
PLL power-down
ADC Volume Control Register
This controls the input level of both ADC channels. The default
value is 1.0 (0100000000000000000000 in binary 2.20 format).
Stereo Spreading Register
This register controls ADI’s patented Phat Stereo spatial
enhancement algorithm. The default is all 0s, which
corresponds to no effect. The maximum setting is
0100000000000000000000 or a twos complement fractional
value of 1.0. Note that the bass energy in each channel is
increased using this algorithm, which may cause some digital
clipping on full-scale signal peaks, especially at low frequencies.
Rev. 0 | Page 13 of 20
AD1970
Dialog Enhancement Register
I2C READ/WRITE DATA FORMATS
This controls the built-in dialog enhancement algorithm, and
defaults to 0. The maximum setting is 0100000000000000000000
or a twos complement fractional value of 1.0. This algorithm is
intended to solve the problem of playing back high dynamic
range digital audio signals over a television’s built-in speakers. It
provides an amplitude boost to signals that are in the range
where dialog signals are usually found, while at the same time
preventing loud special effects passages from overloading the
speakers or amplifiers.
The read/write formats of the I2C port are designed to be byte
oriented. This allows for easy programming of common microcontroller chips. In order to fit into a byte oriented format, 0s
are appended to the data fields in order to extend the data word
to the next multiple of 8 bits. For example, 22-bit words written
to the parameter RAM are appended with two leading zeroes in
order to reach 24 bits (3 bytes). These zero-extended data fields
are appended to a 2-byte field consisting of a read/write bit and
a 10-bit address. The I2C port knows how many data bytes to
expect based on the address received in the first two bytes.
SCL
0
SDA
0
1
0
0
AD1
0
AD0 R/W
0
ACK. BY
I2C
WRITE AD1970
START BY
MASTER
0
0
R/W
0
FRAME 1
CHIP ADDRESS BYTE
0
1
0
0
0
0
0
0
0
1
ACK. BY
AD1970
ACK. BY
AD1970
REGISTER
WRITE
FRAME 2
REGISTER ADDRESS UPPER BYTE
FRAME 3
REGISTER ADDRESS LOWER BYTE
SCL
(CONTINUED)
D15
D14
D11
D12
D13
D10
D9
D8
D7
D5
D6
D4
D3
D2
D1
D0
ACK. BY
AD1970
ACK. BY STOP BY
AD1970 MASTER
FRAME 4
REGISTER DATA UPPER BYTE
05500-009
SDA
(CONTINUED)
FRAME 5
REGISTER DATA LOWER BYTE
Figure 4. Sample of I2C Write Format (Control Register 1 Write)
SCL
SDA
0
1
0
0
0
AD1
AD0 R/W
0
ACK. BY
I2C
WRITE AD1970
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
0
0
0
0
R/W
0
0
1
REGISTER
READ
FRAME 2
REGISTER ADDRESS UPPER BYTE
0
0
0
0
0
0
ACK. BY
AD1970
1
ACK. BY
AD1970
FRAME 3
REGISTER ADDRESS LOWER BYTE
SCL
(CONTINUED)
0
REPEATED START
BY MASTER
1
0
0
0
AD1 AD0 R/W
FRAME 4
CHIP ADDRESS BYTE
D7
I2C ACK. BY
READ AD1970
D6
D5
D4
D3
D2
FRAME 5
REGISTER DATA BYTE
D1
D0
ACK. BY STOP BY
MASTER MASTER
Figure 5. Sample of I2C Read Format (Control Register 1 Read)
Rev. 0 | Page 14 of 20
05500-008
SDA
(CONTINUED)
AD1970
Table 21. Control Register 1 Write Format
Byte 0
00000, R/W = 0, Adr [9:8]
Byte1
Adr [7:0]
Byte 2
00000, Bit [10:8]
Byte 3
Bit [7:0]
Table 22. Control Register 1 Read Format
Byte 0
00000, R/W = 1, Adr [9:8]
Byte 1
Adr [7:0]
Byte 2
00, Bit [5:0]
Table 23. Control Register 2 Write Format
Byte 0
00000, R/W = 0, Adr [9:8]
Byte 1
Adr [7:0]
Byte 2
00, Bit [21:16]
Byte 3
Bit [15:8]
Byte 4
Bit [7:0]
Table 24. Input/Output Level Control, ADC Volume Control, Stereo Spreading, and Dialog Enhancement Registers Write Format
Byte 0
00000, R/W = 0, Adr [9:8]
Byte 1
Adr [7:0]
Byte 2
00, Level [21:16]
Rev. 0 | Page 15 of 20
Byte 3
Level [15:8]
Byte 4
Level [7:0]
AD1970
ANALOG INPUT/OUTPUT
ADC INPUT
SERIAL DATA PORT
The AD1970 accepts an analog left-right signal on its input.
The AD1970’s flexible serial audio interface accepts and sends
data in twos complement, MSB first format. The left channel
data field always precedes the right channel data field. The serial
mode is set by using mode select bits in the control register. In
all modes except for the right justified mode, the serial port
accepts an arbitrary number of bits up to a limit of 24 (extra bits
do not cause an error, but they are truncated internally). In the
right-justified mode, control register bits are used to set the
word length to 16, 20, or 24 bits. The default on power-up is 24bit mode. Proper operation of the right justified mode requires
that there be exactly 64 BCLKs per audio frame.
DAC OUTPUT
Figure 6 shows the block diagram of the analog output. A series
of current sources are controlled by a digital Σ-Δ modulator.
Depending on the digital code from the modulator, each current source is connected to the summing junction of either a
positive I-to-V converter or a negative I-to-V converter. Two
extra current sources that push instead of pull are added to set
the midscale common-mode voltage.
All current sources are derived from the VREF input pin. The
gain of the AD1970 is directly proportional to the magnitude of
the current sources, and therefore the gain of the AD1970 is
proportional to the voltage generated on the VREF pin. The
nominal VREF voltage is 1.5 V.
IREF
Figure 7 shows the left-justified mode. LRCLK is high for the
left channel, and low for the right channel. Data is sampled on
the rising edge of BCLK. The MSB is left-justified to a LRCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.
IREF
OUT+
Figure 7 shows the I2S mode, which is the default setting.
LRCLK is low for the left channel and the MSB is delayed from
the edge of the LRCLK by a single BCLK period. The I2S mode
can be used to accept any number of bits up to 24.
OUT–
VREF IN
IREF + DIG_IN
IREF – DIG_IN
Figure 7 shows the right-justified mode of the AD1970. LRCLK
is high for the left channel, low for the right channel. Data is
sampled on the rising edge of BCLK. The start of data is delayed
from the LRCLK edge by 16, 12, or 8 BCLK intervals, depending
on the selected word length. The default word length is 24 bits;
other word lengths are set by writing to Bits 1:0 of the control
register. In right-justified mode, it is assumed that there are 64
BCLKs per frame.
SWITCHED CURRENT
SOURCES
05500-005
BIAS
FROM DIGITAL
Σ–∆ MODULATOR
(DIG_IN)
SERIAL DATA MODES
Figure 6. Internal DAC Analog Architecture
Since the VREF input effectively multiplies the signal, care must
be taken to insure that no ac signals appear on this pin. This can
be accomplished by using a large decoupling capacitor connected to VREF.
The AD1970 should be used with an external third order filter
on each output channel, as shown in Figure 8. The values shown
are for a 100 kHz Bessel filter. The use of a Bessel filter is important to maintain the time-alignment of the pilot to the carrier. If
these signals are not in phase, a loss of separation occurs.
Figure 7 shows the DSP serial port mode. LRCLK must pulse
high for at least one bit clock period before the MSB of the left
channel is valid and LRCLK must pulse high again for at least
one bit clock period before the MSB of the right channel is
valid. Data is sampled on the falling edge of BCLK. The DSP
serial port mode can be used with any word length up to 24 bits.
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse and that
synchronism is maintained from that point forward.
For best performance, a large (>10 µF) capacitor should be
connected between the FILTCAP pin and analog ground.
Rev. 0 | Page 16 of 20
AD1970
RIGHT CHANNEL
LRCLK
LEFT CHANNEL
BCLK
SDATA
MSB
MSB
LSB
LSB
LEFT JUSTIFIED MODE: 16 TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
MSB
SDATA
I2S
LSB
LSB
MSB
MODE: 16 TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
SDATA
LSB
MSB
MSB
LSB
RIGHT JUSTIFIED MODE: SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
DSP MODE: 16 TO 24 BITS PER CHANNEL
1/FS
NOTES:
1. DSP MODE DOESN'T IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT Fs EXCEPT FOR DSP MODE WHICH IS 2xFs.
3. BCLK FREQUENCY IS NORMALLY 64xLRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 7. Serial Data Formats
Rev. 0 | Page 17 of 20
05500-006
SDATA
AD1970
TYPICAL APPLICATIONS CIRCUIT
3.3V
C21
0.1µF
C20
0.1µF
L1
600Z
L2
600Z
C22
0.1µF
C19
0.1µF
C23
0.1µF
C18
4.7µF
+
R2
10kΩ
C3
1nF
C4
1nF
C5
1nF
PLL_LF
ADR0
ADR1
SCL
SDA
43
DIG_IN_EN
42
LRCLK
41
BCLK
40
SDATA
GPIO3 39
38
GPIO2
35
GPIO1
34
GPIO0
C6
1nF
AD1970
R11
10kΩ
28
PLL_MODE0
29
PLL_MODE1
31
VID_PRES
26
VIDEO_IN
C27
470pF
C7
1nF
30
PLL_MODE0
PLL_MODE1
VID_PRES
VID_IN
RESET
MCLK
3
AGND
2
11
VREF
12
FILTCAP
27
NC
5
RSVD
AGND
DGND
DGND
C15
270pF
ADR0
ADR1
R6
11kΩ
DIG_IN_EN
LRCLK_INTF
BCLK_INTF
SDATA_INTF
GPIO3
GPIO2
GPIO1
GPIO0
R9
604Ω
R7
11kΩ
C14
68pF
R8
3.01kΩ
C13
10µF
BTSC
+
R10
49.9kΩ
C12
2.2nF
RESET
C10
10µF
+
+
C11
10µF
OPTIONAL
AUXILIARY
OSCILLATOR
C9
22pF
05500-007
C8
22pF
48
Y1
4MHz
4MHz
36
R13
1kΩ
DGND
33
XIN
32 XOUT
24
47
46
45
44
SDA
C16
2.2µF
BTSC_OUT 9
7
VIN_OAMP
VOUT_OAMP 6
3.3V
R12
1kΩ
SCL
C17 +
0.1µF
14
+
C25
4.7µF
R15
2kΩ
23
15 VOUT_IAMPL
16
VIN_IAMPL
17 VOUT_IAMPR
18
VIN_IAMPR
19
CAPLP
20 CAPLN
21
CAPRP
22 CAPRN
+
R14
2kΩ
R5
1.6kΩ
PVDD
R1
10kΩ
10
AUDIO_IN_RIGHT
C2
82pF
PGND
AUDIO_IN_LEFT
R4
10kΩ
25
C26
4.7µF
C1
82pF
8
AVDD
13
AVDD
R3
10kΩ
1
DVDD
4
DVDD
37
DVDD
C24
0.1µF
3.3V
Figure 8. Typical Applications Circuit
Rev. 0 | Page 18 of 20
AD1970
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00
BSC SQ
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.00
BSC SQ
TOP VIEW
1.45
1.40
1.35
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 9. 48-Lead Low-Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions are shown in millimeters
ORDERING GUIDE
Model
AD1970JSTZ1
AD1970JSTZRL1
1
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
48-Lead LQFP
48-Lead LQFP on 13-inch Reel
Z = Pb-free part.
Rev. 0 | Page 19 of 20
Package Option
ST-48
ST-48
AD1970
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05500–0–4/05(0)
Rev. 0 | Page 20 of 20
Similar pages